AMDGPU: mark SET_INACTIVE_* as convergent operation

[ruiling]

Summary

set_inactive is actually a kind of operation that is passing certain
value from active threads to inactive threads. In later WWM operation,
the activated threads which were disabled before would read such
values passed to them by set_inactive operation. So I think the
set_inactive is a convergent operation.

[nhaehnle]

Makes sense. The intrinsic was already marked convergent.

[arsenm]

Does tablegen not infer convergent instructions from the source pattern? I assume not (but I always found this to be a dubious feature)

[ruiling]

In D147683#4250292, @arsenm wrote:

Does tablegen not infer convergent instructions from the source pattern? I assume not (but I always found this to be a dubious feature)

I am not familiar with that part. Maybe we still prefer the convergent property being explicitly managed. But I think it might be helpful to at least generate warning if the pattern selection drops convergent property.

[nhaehnle]

I don't think TableGen makes those kind of inferences, does it?

What it does do in some cases (around MayRead/MayWrite etc.) is complain if there is a mismatch between how the intrinsic is defined vs. how the instruction is defined in a pattern.

llvm/lib/Target/AMDGPU/SIInstructions.td

 
 def FPTRUNC_DOWNWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
   (ins VGPR_32:$src0),
   [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
 } // End Uses = [MODE, EXEC]
 
 // Invert the exec mask and overwrite the inactive lanes of dst with inactive,
 // restoring it after we're done.
-let Defs = [SCC] in {
+let Defs = [SCC], isConvergent = 1 in {
 def V_SET_INACTIVE_B32 : VPseudoInstSI <(outs VGPR_32:$vdst),
   (ins VSrc_b32: $src, VSrc_b32:$inactive),
   [(set i32:$vdst, (int_amdgcn_set_inactive i32:$src, i32:$inactive))]> {
 }
 
 def V_SET_INACTIVE_B64 : VPseudoInstSI <(outs VReg_64:$vdst),
   (ins VSrc_b64: $src, VSrc_b64:$inactive),
   [(set i64:$vdst, (int_amdgcn_set_inactive i64:$src, i64:$inactive))]> {

llvm/test/CodeGen/AMDGPU/should-not-hoist-set-inactive.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
 
 define amdgpu_cs void @should_not_hoist_set_inactive(<4 x i32> inreg %i14, i32 inreg %v, i32 %lane, i32 %f, i32 %f2) #0 {
 ; GCN-LABEL: should_not_hoist_set_inactive:
 ; GCN:       ; %bb.0: ; %.entry
 ; GCN-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 3, v1
-; GCN-NEXT:    v_cmp_eq_u32_e64 s6, 0, v0
-; GCN-NEXT:    v_cmp_ne_u32_e64 s5, 0, v2
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    s_not_b32 exec_lo, exec_lo
-; GCN-NEXT:    v_mov_b32_e32 v3, 0
-; GCN-NEXT:    s_not_b32 exec_lo, exec_lo
-; GCN-NEXT:    s_mov_b32 s4, 0
+; GCN-NEXT:    v_cmp_eq_u32_e64 s5, 0, v0
+; GCN-NEXT:    v_cmp_ne_u32_e64 s6, 0, v2
+; GCN-NEXT:    s_mov_b32 s7, 0
 ; GCN-NEXT:    s_branch .LBB0_2
 ; GCN-NEXT:  .LBB0_1: ; %bb4
 ; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=1
 ; GCN-NEXT:    s_waitcnt_depctr 0xffe3
-; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s7
-; GCN-NEXT:    s_andn2_b32 exec_lo, exec_lo, s4
+; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s8
+; GCN-NEXT:    s_andn2_b32 exec_lo, exec_lo, s7
 ; GCN-NEXT:    s_cbranch_execz .LBB0_5
 ; GCN-NEXT:  .LBB0_2: ; %bb
 ; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT:    s_and_b32 s7, exec_lo, s5
-; GCN-NEXT:    s_or_b32 s4, s7, s4
-; GCN-NEXT:    s_and_saveexec_b32 s7, vcc_lo
+; GCN-NEXT:    s_and_b32 s8, exec_lo, s6
+; GCN-NEXT:    s_or_b32 s7, s8, s7
+; GCN-NEXT:    s_and_saveexec_b32 s8, vcc_lo
 ; GCN-NEXT:    s_cbranch_execz .LBB0_1
 ; GCN-NEXT:  ; %bb.3: ; %bb1
 ; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=1
-; GCN-NEXT:    s_or_saveexec_b32 s8, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, s4
+; GCN-NEXT:    s_not_b32 exec_lo, exec_lo
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_not_b32 exec_lo, exec_lo
+; GCN-NEXT:    s_or_saveexec_b32 s9, -1
 ; GCN-NEXT:    v_mov_b32_e32 v4, 0
 ; GCN-NEXT:    v_mov_b32_dpp v4, v3 row_xmask:1 row_mask:0xf bank_mask:0xf
-; GCN-NEXT:    s_mov_b32 exec_lo, s8
+; GCN-NEXT:    s_mov_b32 exec_lo, s9
 ; GCN-NEXT:    v_mov_b32_e32 v0, v4
-; GCN-NEXT:    s_and_b32 exec_lo, exec_lo, s6
+; GCN-NEXT:    s_and_b32 exec_lo, exec_lo, s5
 ; GCN-NEXT:    s_cbranch_execz .LBB0_1
 ; GCN-NEXT:  ; %bb.4: ; %bb2
 ; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=1
 ; GCN-NEXT:    buffer_atomic_add v0, off, s[0:3], 0
 ; GCN-NEXT:    s_branch .LBB0_1
 ; GCN-NEXT:  .LBB0_5: ; %bb5
 ; GCN-NEXT:    s_endpgm
 .entry: