[AArch64][SME] Disable ZA LDR/STR addressing optimisations

[david-arm]

Summary

Since the same encoded offset is used for both the vector
select offset and the address offset we have to spot two
patterns simulatenously in the ldr/str intrinsic inputs, i.e.

vector select = base + off
address = base + (off * VL)

whereas currently we only look for the address pattern. I
don't think this is possible in tablegen, so I suspect we'll
have to do this manually as part of lowering or as a target
DAG combine. For now, I've removed these tablegen patterns
so that we at least do the correct thing even if the code
quality isn't great.

I've also changed some of the ldr/str tests to pass in the
same vector select pattern (base + off) as the address
pattern.

[CarolineConcatto]

llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

267

I am still able to compiler these tests, without any change in this one. The only change is in the str_with_off_15mulvl, because it does not use the mul vl.
Is this correct?

[CarolineConcatto]

I believe we should push this patch soon in order to avoid wrong optmization

llvm/lib/Target/AArch64/SMEInstrFormats.td

 multiclass sme_spill<string opcodestr> {
   def NAME : sme_spill_inst<opcodestr>;
   def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
                   (!cast<Instruction>(NAME) MatrixOp:$ZAt,
                    MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0), 1>;
   // base
   def : Pat<(int_aarch64_sme_str MatrixIndexGPR32Op12_15:$idx, GPR64sp:$base),
             (!cast<Instruction>(NAME) ZA, $idx, 0, $base, 0)>;
-  // scalar + immediate (mul vl)
-  let AddedComplexity = 2 in {
-    def : Pat<(int_aarch64_sme_str MatrixIndexGPR32Op12_15:$idx,
-                                   (am_sme_indexed_b4 GPR64sp:$base, imm0_15:$imm4)),
-              (!cast<Instruction>(NAME) ZA, $idx, 0, $base, $imm4)>;
-  }
 }
 
 multiclass sme_fill<string opcodestr> {
   def NAME : sme_fill_inst<opcodestr>;
   def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
                   (!cast<Instruction>(NAME) MatrixOp:$ZAt,
                    MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0), 1>;
   def NAME # _PSEUDO
       : Pseudo<(outs),
                (ins MatrixIndexGPR32Op12_15:$idx, imm0_15:$imm4,
                     GPR64sp:$base), []>,
         Sched<[]> {
     // Translated to actual instruction in AArch64ISelLowering.cpp
     let usesCustomInserter = 1;
     let mayLoad = 1;
   }
   // base
   def : Pat<(int_aarch64_sme_ldr MatrixIndexGPR32Op12_15:$idx, GPR64sp:$base),
             (!cast<Instruction>(NAME # _PSEUDO) $idx, 0, $base)>;
-  // scalar + immediate (mul vl)
-  let AddedComplexity = 2 in {
-    def : Pat<(int_aarch64_sme_ldr MatrixIndexGPR32Op12_15:$idx,
-                                   (am_sme_indexed_b4 GPR64sp:$base, imm0_15:$imm4)),
-              (!cast<Instruction>(NAME # _PSEUDO) $idx, $imm4, $base)>;
-  }
 }
 
 //===----------------------------------------------------------------------===//
 // Move instructions
 //===----------------------------------------------------------------------===//
 
 class sme_vector_to_tile_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
                               string mnemonic, string argstr>

llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll

 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sme.ldr(i32 0, ptr %ptr)
   ret void;
 }
 
 define void @ldr_with_off_15(ptr %ptr) {
 ; CHECK-LABEL: ldr_with_off_15:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
+; CHECK-NEXT:    mov w12, #15 // =0xf
 ; CHECK-NEXT:    add x8, x0, #15
 ; CHECK-NEXT:    ldr za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr i8, ptr %ptr, i64 15
-  call void @llvm.aarch64.sme.ldr(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.ldr(i32 15, ptr %base)
   ret void;
 }
 
 define void @ldr_with_off_15mulvl(ptr %ptr) {
 ; CHECK-LABEL: ldr_with_off_15mulvl:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
-; CHECK-NEXT:    ldr za[w12, 15], [x0, #15, mul vl]
+; CHECK-NEXT:    mov w12, #15 // =0xf
+; CHECK-NEXT:    addvl x8, x0, #15
+; CHECK-NEXT:    ldr za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %mulvl = mul i64 %vscale, 240
   %base = getelementptr i8, ptr %ptr, i64 %mulvl
-  call void @llvm.aarch64.sme.ldr(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.ldr(i32 15, ptr %base)
   ret void;
 }
 
 define void @ldr_with_off_16mulvl(ptr %ptr) {
 ; CHECK-LABEL: ldr_with_off_16mulvl:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
+; CHECK-NEXT:    mov w12, #16 // =0x10
 ; CHECK-NEXT:    addvl x8, x0, #16
 ; CHECK-NEXT:    ldr za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %mulvl = mul i64 %vscale, 256
   %base = getelementptr i8, ptr %ptr, i64 %mulvl
-  call void @llvm.aarch64.sme.ldr(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.ldr(i32 16, ptr %base)
   ret void;
 }
 
 ; Ensure that the tile offset is sunk, given that this is likely to be an 'add'
 ; that's decomposed into a base + offset in ISel.
 define void @test_ld1_sink_tile0_offset_operand(<vscale x 4 x i1> %pg, ptr %src, i32 %base, i32 %N) {
 ; CHECK-LABEL: test_ld1_sink_tile0_offset_operand:
 ; CHECK:       // %bb.0: // %entry

llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

 ; CHECK-NEXT:    ret
   call void @llvm.aarch64.sme.str(i32 0, ptr %ptr)
   ret void;
 }
 
 define void @str_with_off_15(ptr %ptr) {
 ; CHECK-LABEL: str_with_off_15:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
+; CHECK-NEXT:    mov w12, #15 // =0xf
 ; CHECK-NEXT:    add x8, x0, #15
 ; CHECK-NEXT:    str za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %base = getelementptr i8, ptr %ptr, i64 15
-  call void @llvm.aarch64.sme.str(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.str(i32 15, ptr %base)
   ret void;
 }
 
 define void @str_with_off_15mulvl(ptr %ptr) {
 ; CHECK-LABEL: str_with_off_15mulvl:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
-; CHECK-NEXT:    str za[w12, 0], [x0, #15, mul vl]
+; CHECK-NEXT:    mov w12, #15 // =0xf
+; CHECK-NEXT:    addvl x8, x0, #15
+; CHECK-NEXT:    str za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %mulvl = mul i64 %vscale, 240
   %base = getelementptr i8, ptr %ptr, i64 %mulvl
-  call void @llvm.aarch64.sme.str(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.str(i32 15, ptr %base)
   ret void;
 }
 
 define void @str_with_off_16mulvl(ptr %ptr) {
 ; CHECK-LABEL: str_with_off_16mulvl:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w12, wzr
+; CHECK-NEXT:    mov w12, #16 // =0x10
 ; CHECK-NEXT:    addvl x8, x0, #16
 ; CHECK-NEXT:    str za[w12, 0], [x8]
 ; CHECK-NEXT:    ret
   %vscale = call i64 @llvm.vscale.i64()
   %mulvl = mul i64 %vscale, 256
   %base = getelementptr i8, ptr %ptr, i64 %mulvl
-  call void @llvm.aarch64.sme.str(i32 0, ptr %base)
+  call void @llvm.aarch64.sme.str(i32 16, ptr %base)
   ret void;
 }
 
 ; Ensure that the tile offset is sunk, given that this is likely to be an 'add'
 ; that's decomposed into a base + offset in ISel.
 define void @test_sink_tile0_offset_operand(<vscale x 4 x i1> %pg, ptr %src, i32 %base, i32 %N) {
 ; CHECK-LABEL: test_sink_tile0_offset_operand:
 ; CHECK:       // %bb.0: // %entry