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Differential D147279

[HeterogeneousDWARF] Implement AMDGPU CFI, DebugInfo
Needs ReviewPublic

Authored by scott.linder on Mar 30 2023, 2:59 PM.

Details

Reviewers
None
Group Reviewers
debug-info
Summary

Add -amdgpu-spill-cfi-saved-regs to enable complete debug info even when
codegen would otherwise not spill the EXEC mask. This is a workaround
until a solution to describe the EXEC mask without spills is integrated
based on the new structurizer.

Support emitting eh_frame for debug-info even when the target does not
support exceptions.

Extend MCAsmInfo to reflect whether a target opts in to the
heterogeneous DWARF extensions.

Diff Detail

Large Diff

This large diff affects 102 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

PathSize
clang/
lib/
Driver/
ToolChains/
4 lines
5 lines
llvm/
include/
llvm/
MC/
12 lines
lib/
CodeGen/
AsmPrinter/
10 lines
6 lines
MC/
8 lines
Target/
AMDGPU/
MCTargetDesc/
1 line
61 lines
532 lines
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test/
CodeGen/
AMDGPU/
GlobalISel/
8 lines
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DebugInfo/
AMDGPU/
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MC/
ELF/
AMDGPU/
15 lines

Diff 509832

clang/lib/Driver/ToolChains/Clang.cpp

clang/lib/Driver/ToolChains/HIPAMD.cpp

llvm/include/llvm/MC/MCAsmInfo.h

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h

llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

llvm/lib/MC/MCDwarf.cpp

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp

llvm/lib/Target/AMDGPU/SIFrameLowering.h

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

llvm/lib/Target/AMDGPU/SIInstrInfo.h

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/lib/Target/AMDGPU/SIInstructions.td

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll

llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir

llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll

llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir

llvm/test/CodeGen/AMDGPU/amdgpu-spill-cfi-saved-regs.ll

llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir

llvm/test/CodeGen/AMDGPU/bf16.ll

llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll

llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll

llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir

llvm/test/CodeGen/AMDGPU/debug-frame.ll

llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll

llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir

llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll

llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir

llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir

llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir

llvm/test/CodeGen/AMDGPU/frame-index.mir

llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll

llvm/test/CodeGen/AMDGPU/indirect-call.ll

llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir

llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll

llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/nested-calls.ll

llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll

llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir

llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir

llvm/test/CodeGen/AMDGPU/pei-build-spill.mir

llvm/test/CodeGen/AMDGPU/pei-cfi-saves-bug.ll

llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir

llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir

llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir

llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir

llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir

llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir

llvm/test/CodeGen/AMDGPU/prologue-epilogue-markers.ll

llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll

llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir

llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir

llvm/test/CodeGen/AMDGPU/sgpr-spill.mir

llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll

llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir

llvm/test/CodeGen/AMDGPU/sibling-call.ll

llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir

llvm/test/CodeGen/AMDGPU/spill-agpr.mir

llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir

llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir

llvm/test/CodeGen/AMDGPU/split-arg-dbg-value.ll

llvm/test/CodeGen/AMDGPU/stack-realign.ll

llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll

llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir

llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll

llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll

llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir

llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir

llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir

llvm/test/CodeGen/AMDGPU/vgpr-spill.mir

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

llvm/test/CodeGen/AMDGPU/wave32.ll

llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

llvm/test/DebugInfo/AMDGPU/cfi.ll

llvm/test/DebugInfo/AMDGPU/cu-augmentation.ll

llvm/test/MC/ELF/AMDGPU/cfi.s