[LegalizeTypes][TargetLowering][RISCV] Fix regressions from D146786.

[craig.topper]

Summary

Add some special cases for UADDO to recover codegen after D146786.

[craig.topper]

clang-format

[reames]

LGTM

[liaolucy]

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

663

RV32 and RV64 each add an mv(COPY) instruction, the instruction is added by virtregrewriter.

But the whole is good, maybe we can add a todo, lest we forget.

[craig.topper]

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

663

Functions this small aren’t representative of register allocation on longer functions. I would hope this function would be inlined.

[liaolucy]

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

663

thanks, LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (HasCarryOp) {
     SplitInteger(Sum, Lo, Hi);
 
     if (N->getOpcode() == ISD::UADDO && isOneConstant(RHS)) {
       // Special case: uaddo X, 1 overflowed if X+1 == 0. We can detect this
       // with (Lo | Hi) == 0.
       SDValue Or = DAG.getNode(ISD::OR, dl, Lo.getValueType(), Lo, Hi);
       Ovf = DAG.getSetCC(dl, N->getValueType(1), Or,
                          DAG.getConstant(0, dl, Lo.getValueType()), ISD::SETEQ);
+    } else if (N->getOpcode() == ISD::UADDO && isAllOnesConstant(RHS)) {
+      // Special case: uaddo X, -1 overflows if X == 0. We can detect this
+      Ovf = DAG.getSetCC(dl, N->getValueType(1), LHS,
+                         DAG.getConstant(0, dl, LHS.getValueType()), ISD::SETNE);
     } else {
       // Calculate the overflow: addition overflows iff a + b < a, and
       // subtraction overflows iff a - b > a.
       Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
     }
   }
 
   // Legalized the flag result - switch anything that used the old flag to

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (IsAdd && isOneConstant(RHS)) {
     // Special case: uaddo X, 1 overflowed if X+1 is 0. This potential reduces
     // the live range of X. We assume comparing with 0 is cheap.
     // The general case (X + C) < C is not necessarily beneficial. Although we
     // reduce the live range of X, we may introduce the materialization of
     // constant C.
     SetCC =
         DAG.getSetCC(dl, SetCCType, Result,
                      DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETEQ);
+  } else if (IsAdd && isAllOnesConstant(RHS)) {
+    // Special case: uaddo X, -1 overflows if X != 0.
+    SetCC =
+        DAG.getSetCC(dl, SetCCType, LHS,
+                     DAG.getConstant(0, dl, Node->getValueType(0)), ISD::SETNE);
   } else {
     ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
     SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC);
   }
   Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType);
 }
 
 void TargetLowering::expandSADDSUBO(

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

; RV64-NEXT:    ret
   %ov = icmp eq i64 %x, -1
   %a = add i64 %x, 1
   store i64 %a, ptr %p
   ret i1 %ov
 }
 
 ; The overflow check may be against the input rather than the sum.
 
 define i1 @uaddo_i64_decrement_alt(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a3, a0, -1
+; RV32-NEXT:    or a3, a0, a1
+; RV32-NEXT:    snez a3, a3
 ; RV32-NEXT:    seqz a4, a0
-; RV32-NEXT:    sub a4, a1, a4
-; RV32-NEXT:    bnez a0, .LBB18_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    sltu a0, a4, a1
-; RV32-NEXT:    j .LBB18_3
-; RV32-NEXT:  .LBB18_2:
-; RV32-NEXT:    sltu a0, a3, a0
-; RV32-NEXT:  .LBB18_3:
-; RV32-NEXT:    sw a3, 0(a2)
-; RV32-NEXT:    sw a4, 4(a2)
+; RV32-NEXT:    sub a1, a1, a4
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    sw a1, 4(a2)
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi a2, a0, -1
-; RV64-NEXT:    sltu a0, a2, a0
-; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    snez a2, a0
+; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    sd a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
   %a = add i64 %x, -1
   store i64 %a, ptr %p
   %ov = icmp ne i64 %x, 0
   ret i1 %ov
 }
 
 ; Make sure insertion is done correctly based on dominance.
 
 define i1 @uaddo_i64_decrement_alt_dom(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a3, a0, -1
+; RV32-NEXT:    or a3, a0, a1
+; RV32-NEXT:    snez a3, a3
 ; RV32-NEXT:    seqz a4, a0
-; RV32-NEXT:    sub a4, a1, a4
-; RV32-NEXT:    bnez a0, .LBB19_2
-; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    sltu a0, a4, a1
-; RV32-NEXT:    j .LBB19_3
-; RV32-NEXT:  .LBB19_2:
-; RV32-NEXT:    sltu a0, a3, a0
-; RV32-NEXT:  .LBB19_3:
-; RV32-NEXT:    sw a3, 0(a2)
-; RV32-NEXT:    sw a4, 4(a2)
+; RV32-NEXT:    sub a1, a1, a4
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    sw a1, 4(a2)
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    addi a2, a0, -1
-; RV64-NEXT:    sltu a0, a2, a0
-; RV64-NEXT:    sd a2, 0(a1)
+; RV64-NEXT:    snez a2, a0
+; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    sd a0, 0(a1)
+; RV64-NEXT:    mv a0, a2
 ; RV64-NEXT:    ret
   %ov = icmp ne i64 %x, 0
   %a = add i64 %x, -1
   store i64 %a, ptr %p
   ret i1 %ov
 }
 
 ; No transform for illegal types.