[RISCV] Enable usubo formation in CodeGenPrepare.

[craig.topper]

Summary

The default behavior of shouldFormOverflowOp is to only enable
for uaddo.

This patch enables it for consistency. We can work on other fixes to
improve the generated code.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.h

499

Doesn't this also enable multiply as well? Do we want to?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.h

499

You might think that from the name but its never called with ISD::UMULO. I can add an assert?

[reames]

LGTM w/comment

llvm/lib/Target/RISCV/RISCVISelLowering.h

496

Should this maybe be checking that VT is legal? Forming a 64 bit op on RV32 or a 32 bit op on RV64 seems slightly suspect.

499

Yes please.

[asb]

I start writing a comment grumbling that this adds undesirably tight coupling between with the implementation details of TargetLowering::shouldFormOverflowOp, but when I got to the end of it figured it wasn't that bad. If the comment had just said "Allow the transform whenever it would be allowed for UADDO" I might not have commented. LGTM. Though an assert like you suggest probably makes sense.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.h

496

We seem to do ok with W instructions for i32 on RV64.

For i64 on RV32, there was a proposed patch that disabled it, but then required other patches. I applied a couple patches to type legalization for uaddo and add that fixed the motivating case. I haven't seen evidence of other problems yet.

[liaolucy]

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

781

This regression cannot to be solved by adding a special case.

It seems we can modify ExpandIntRes_UADDSUBO by referring to ExpandIntRes_ADDSUB, I'm not sure.

[craig.topper]

Moving to Plan Changes until I circle back to look at the regressions.

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                      SDNode *Node) const override;
 
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
 
   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
                             bool MathUsed) const override {
     if (VT == MVT::i8 || VT == MVT::i16)
       return false;
 
-    return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
+    // Pass ISD::UADDO to bypass the default behavior disabling ISD::USUBO.
+    return TargetLowering::shouldFormOverflowOp(ISD::UADDO, VT, MathUsed);
   }
 
   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     return VT.isScalarInteger();
   }
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool preferZeroCompareBranch() const override { return true; }

llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

 ; RV32I-NEXT:    li a3, 5
 ; RV32I-NEXT:    li a4, 5
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __atomic_compare_exchange_4@plt
 ; RV32I-NEXT:    lw a3, 0(sp)
 ; RV32I-NEXT:    bnez a0, .LBB6_4
 ; RV32I-NEXT:  .LBB6_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    seqz a0, a3
-; RV32I-NEXT:    sltu a1, s1, a3
-; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    addi a0, a3, -1
+; RV32I-NEXT:    sltu a1, a3, a0
+; RV32I-NEXT:    sltu a2, s1, a3
+; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    mv a2, s1
-; RV32I-NEXT:    bnez a0, .LBB6_1
+; RV32I-NEXT:    bnez a1, .LBB6_1
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB6_2 Depth=1
-; RV32I-NEXT:    addi a2, a3, -1
+; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    j .LBB6_1
 ; RV32I-NEXT:  .LBB6_4: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IA-NEXT:    bnez a5, .LBB6_5
 ; RV32IA-NEXT:  .LBB6_7: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB6_2 Depth=1
 ; RV32IA-NEXT:    beq a2, a3, .LBB6_4
 ; RV32IA-NEXT:  .LBB6_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Loop Header: Depth=1
 ; RV32IA-NEXT:    # Child Loop BB6_5 Depth 2
 ; RV32IA-NEXT:    mv a3, a2
-; RV32IA-NEXT:    seqz a2, a2
-; RV32IA-NEXT:    sltu a4, a1, a3
-; RV32IA-NEXT:    or a2, a2, a4
+; RV32IA-NEXT:    addi a2, a2, -1
+; RV32IA-NEXT:    sltu a4, a3, a2
+; RV32IA-NEXT:    sltu a5, a1, a3
+; RV32IA-NEXT:    or a5, a4, a5
 ; RV32IA-NEXT:    mv a4, a1
-; RV32IA-NEXT:    bnez a2, .LBB6_1
+; RV32IA-NEXT:    bnez a5, .LBB6_1
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB6_2 Depth=1
-; RV32IA-NEXT:    addi a4, a3, -1
+; RV32IA-NEXT:    mv a4, a2
 ; RV32IA-NEXT:    j .LBB6_1
 ; RV32IA-NEXT:  .LBB6_4: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_udec_wrap_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48

 ; RV64I-NEXT:    li a3, 5
 ; RV64I-NEXT:    li a4, 5
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __atomic_compare_exchange_4@plt
 ; RV64I-NEXT:    lw a3, 12(sp)
 ; RV64I-NEXT:    bnez a0, .LBB6_4
 ; RV64I-NEXT:  .LBB6_2: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    seqz a0, a3
-; RV64I-NEXT:    sltu a1, s2, a3
-; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addiw a0, a3, -1
+; RV64I-NEXT:    sltu a1, a3, a0
+; RV64I-NEXT:    sltu a2, s2, a3
+; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    mv a2, s1
-; RV64I-NEXT:    bnez a0, .LBB6_1
+; RV64I-NEXT:    bnez a1, .LBB6_1
 ; RV64I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB6_2 Depth=1
-; RV64I-NEXT:    addiw a2, a3, -1
+; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    j .LBB6_1
 ; RV64I-NEXT:  .LBB6_4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_udec_wrap_i32:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    lw a2, 0(a0)
 ; RV64IA-NEXT:    sext.w a3, a1
 ; RV64IA-NEXT:    j .LBB6_2
 ; RV64IA-NEXT:  .LBB6_1: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB6_2 Depth=1
 ; RV64IA-NEXT:  .LBB6_5: # %atomicrmw.start
 ; RV64IA-NEXT:    # Parent Loop BB6_2 Depth=1
 ; RV64IA-NEXT:    # => This Inner Loop Header: Depth=2
 ; RV64IA-NEXT:    lr.w.aqrl a2, (a0)
 ; RV64IA-NEXT:    bne a2, a4, .LBB6_7
 ; RV64IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB6_5 Depth=2
-; RV64IA-NEXT:    sc.w.aqrl a6, a5, (a0)
-; RV64IA-NEXT:    bnez a6, .LBB6_5
+; RV64IA-NEXT:    sc.w.aqrl a5, a6, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB6_5
 ; RV64IA-NEXT:  .LBB6_7: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB6_2 Depth=1
 ; RV64IA-NEXT:    beq a2, a4, .LBB6_4
 ; RV64IA-NEXT:  .LBB6_2: # %atomicrmw.start
 ; RV64IA-NEXT:    # =>This Loop Header: Depth=1
 ; RV64IA-NEXT:    # Child Loop BB6_5 Depth 2
+; RV64IA-NEXT:    addiw a5, a2, -1
 ; RV64IA-NEXT:    sext.w a4, a2
-; RV64IA-NEXT:    seqz a5, a4
+; RV64IA-NEXT:    sltu a2, a4, a5
 ; RV64IA-NEXT:    sltu a6, a3, a4
-; RV64IA-NEXT:    or a6, a5, a6
-; RV64IA-NEXT:    mv a5, a1
-; RV64IA-NEXT:    bnez a6, .LBB6_1
+; RV64IA-NEXT:    or a2, a2, a6
+; RV64IA-NEXT:    mv a6, a1
+; RV64IA-NEXT:    bnez a2, .LBB6_1
 ; RV64IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB6_2 Depth=1
-; RV64IA-NEXT:    addiw a5, a2, -1
+; RV64IA-NEXT:    mv a6, a5
 ; RV64IA-NEXT:    j .LBB6_1
 ; RV64IA-NEXT:  .LBB6_4: # %atomicrmw.end
 ; RV64IA-NEXT:    mv a0, a2
 ; RV64IA-NEXT:    ret
   %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst
   ret i32 %result
 }
 

 ; RV32I-NEXT:    sw a5, 12(sp)
 ; RV32I-NEXT:    addi a1, sp, 8
 ; RV32I-NEXT:    li a4, 5
 ; RV32I-NEXT:    li a5, 5
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __atomic_compare_exchange_8@plt
 ; RV32I-NEXT:    lw a5, 12(sp)
 ; RV32I-NEXT:    lw a4, 8(sp)
-; RV32I-NEXT:    bnez a0, .LBB7_7
+; RV32I-NEXT:    bnez a0, .LBB7_9
 ; RV32I-NEXT:  .LBB7_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    beq a5, s1, .LBB7_4
+; RV32I-NEXT:    addi a0, a4, -1
+; RV32I-NEXT:    seqz a1, a4
+; RV32I-NEXT:    sub a1, a5, a1
+; RV32I-NEXT:    bnez a4, .LBB7_5
 ; RV32I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32I-NEXT:    sltu a0, s1, a5
-; RV32I-NEXT:    j .LBB7_5
+; RV32I-NEXT:    sltu a2, a5, a1
+; RV32I-NEXT:    bne a5, s1, .LBB7_6
 ; RV32I-NEXT:  .LBB7_4: # in Loop: Header=BB7_2 Depth=1
-; RV32I-NEXT:    sltu a0, s2, a4
-; RV32I-NEXT:  .LBB7_5: # %atomicrmw.start
+; RV32I-NEXT:    sltu a3, s2, a4
+; RV32I-NEXT:    j .LBB7_7
+; RV32I-NEXT:  .LBB7_5: # in Loop: Header=BB7_2 Depth=1
+; RV32I-NEXT:    sltu a2, a4, a0
+; RV32I-NEXT:    beq a5, s1, .LBB7_4
+; RV32I-NEXT:  .LBB7_6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32I-NEXT:    or a1, a4, a5
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    sltu a3, s1, a5
+; RV32I-NEXT:  .LBB7_7: # %atomicrmw.start
+; RV32I-NEXT:    # in Loop: Header=BB7_2 Depth=1
+; RV32I-NEXT:    or a6, a2, a3
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:    mv a3, s1
-; RV32I-NEXT:    bnez a0, .LBB7_1
-; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
+; RV32I-NEXT:    bnez a6, .LBB7_1
+; RV32I-NEXT:  # %bb.8: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32I-NEXT:    seqz a0, a4
-; RV32I-NEXT:    sub a3, a5, a0
-; RV32I-NEXT:    addi a2, a4, -1
+; RV32I-NEXT:    mv a2, a0
+; RV32I-NEXT:    mv a3, a1
 ; RV32I-NEXT:    j .LBB7_1
-; RV32I-NEXT:  .LBB7_7: # %atomicrmw.end
+; RV32I-NEXT:  .LBB7_9: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret

 ; RV32IA-NEXT:    sw a5, 12(sp)
 ; RV32IA-NEXT:    addi a1, sp, 8
 ; RV32IA-NEXT:    li a4, 5
 ; RV32IA-NEXT:    li a5, 5
 ; RV32IA-NEXT:    mv a0, s0
 ; RV32IA-NEXT:    call __atomic_compare_exchange_8@plt
 ; RV32IA-NEXT:    lw a5, 12(sp)
 ; RV32IA-NEXT:    lw a4, 8(sp)
-; RV32IA-NEXT:    bnez a0, .LBB7_7
+; RV32IA-NEXT:    bnez a0, .LBB7_9
 ; RV32IA-NEXT:  .LBB7_2: # %atomicrmw.start
 ; RV32IA-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32IA-NEXT:    beq a5, s1, .LBB7_4
+; RV32IA-NEXT:    addi a0, a4, -1
+; RV32IA-NEXT:    seqz a1, a4
+; RV32IA-NEXT:    sub a1, a5, a1
+; RV32IA-NEXT:    bnez a4, .LBB7_5
 ; RV32IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32IA-NEXT:    sltu a0, s1, a5
-; RV32IA-NEXT:    j .LBB7_5
+; RV32IA-NEXT:    sltu a2, a5, a1
+; RV32IA-NEXT:    bne a5, s1, .LBB7_6
 ; RV32IA-NEXT:  .LBB7_4: # in Loop: Header=BB7_2 Depth=1
-; RV32IA-NEXT:    sltu a0, s2, a4
-; RV32IA-NEXT:  .LBB7_5: # %atomicrmw.start
+; RV32IA-NEXT:    sltu a3, s2, a4
+; RV32IA-NEXT:    j .LBB7_7
+; RV32IA-NEXT:  .LBB7_5: # in Loop: Header=BB7_2 Depth=1
+; RV32IA-NEXT:    sltu a2, a4, a0
+; RV32IA-NEXT:    beq a5, s1, .LBB7_4
+; RV32IA-NEXT:  .LBB7_6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32IA-NEXT:    or a1, a4, a5
-; RV32IA-NEXT:    seqz a1, a1
-; RV32IA-NEXT:    or a0, a1, a0
+; RV32IA-NEXT:    sltu a3, s1, a5
+; RV32IA-NEXT:  .LBB7_7: # %atomicrmw.start
+; RV32IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
+; RV32IA-NEXT:    or a6, a2, a3
 ; RV32IA-NEXT:    mv a2, s2
 ; RV32IA-NEXT:    mv a3, s1
-; RV32IA-NEXT:    bnez a0, .LBB7_1
-; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
+; RV32IA-NEXT:    bnez a6, .LBB7_1
+; RV32IA-NEXT:  # %bb.8: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV32IA-NEXT:    seqz a0, a4
-; RV32IA-NEXT:    sub a3, a5, a0
-; RV32IA-NEXT:    addi a2, a4, -1
+; RV32IA-NEXT:    mv a2, a0
+; RV32IA-NEXT:    mv a3, a1
 ; RV32IA-NEXT:    j .LBB7_1
-; RV32IA-NEXT:  .LBB7_7: # %atomicrmw.end
+; RV32IA-NEXT:  .LBB7_9: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a4
 ; RV32IA-NEXT:    mv a1, a5
 ; RV32IA-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret

 ; RV64I-NEXT:    li a3, 5
 ; RV64I-NEXT:    li a4, 5
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __atomic_compare_exchange_8@plt
 ; RV64I-NEXT:    ld a3, 0(sp)
 ; RV64I-NEXT:    bnez a0, .LBB7_4
 ; RV64I-NEXT:  .LBB7_2: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    seqz a0, a3
-; RV64I-NEXT:    sltu a1, s1, a3
-; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addi a0, a3, -1
+; RV64I-NEXT:    sltu a1, a3, a0
+; RV64I-NEXT:    sltu a2, s1, a3
+; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    mv a2, s1
-; RV64I-NEXT:    bnez a0, .LBB7_1
+; RV64I-NEXT:    bnez a1, .LBB7_1
 ; RV64I-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV64I-NEXT:    addi a2, a3, -1
+; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    j .LBB7_1
 ; RV64I-NEXT:  .LBB7_4: # %atomicrmw.end
 ; RV64I-NEXT:    mv a0, a3
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret

 ; RV64IA-NEXT:    bnez a5, .LBB7_5
 ; RV64IA-NEXT:  .LBB7_7: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
 ; RV64IA-NEXT:    beq a2, a3, .LBB7_4
 ; RV64IA-NEXT:  .LBB7_2: # %atomicrmw.start
 ; RV64IA-NEXT:    # =>This Loop Header: Depth=1
 ; RV64IA-NEXT:    # Child Loop BB7_5 Depth 2
 ; RV64IA-NEXT:    mv a3, a2
-; RV64IA-NEXT:    seqz a2, a2
-; RV64IA-NEXT:    sltu a4, a1, a3
-; RV64IA-NEXT:    or a2, a2, a4
+; RV64IA-NEXT:    addi a2, a2, -1
+; RV64IA-NEXT:    sltu a4, a3, a2
+; RV64IA-NEXT:    sltu a5, a1, a3
+; RV64IA-NEXT:    or a5, a4, a5
 ; RV64IA-NEXT:    mv a4, a1
-; RV64IA-NEXT:    bnez a2, .LBB7_1
+; RV64IA-NEXT:    bnez a5, .LBB7_1
 ; RV64IA-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; RV64IA-NEXT:    addi a4, a3, -1
+; RV64IA-NEXT:    mv a4, a2
 ; RV64IA-NEXT:    j .LBB7_1
 ; RV64IA-NEXT:  .LBB7_4: # %atomicrmw.end
 ; RV64IA-NEXT:    mv a0, a2
 ; RV64IA-NEXT:    ret
   %result = atomicrmw udec_wrap ptr %ptr, i64 %val seq_cst
   ret i64 %result
 }

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

; RV64-NEXT:    ret
   %s = sub i64 %x, %y
   %ov = icmp ult i64 %x, %y
   ret i1 %ov
 }
 
 define i1 @usubo_ult_i64_math_overflow_used(i64 %x, i64 %y, ptr %p) {
 ; RV32-LABEL: usubo_ult_i64_math_overflow_used:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    mv a5, a0
-; RV32-NEXT:    sltu a0, a0, a2
-; RV32-NEXT:    sub a6, a1, a3
-; RV32-NEXT:    sub a6, a6, a0
-; RV32-NEXT:    sub a5, a5, a2
-; RV32-NEXT:    sw a5, 0(a4)
-; RV32-NEXT:    sw a6, 4(a4)
-; RV32-NEXT:    beq a1, a3, .LBB22_2
+; RV32-NEXT:    sltu a5, a0, a2
+; RV32-NEXT:    sub a3, a1, a3
+; RV32-NEXT:    sub a3, a3, a5
+; RV32-NEXT:    sub a2, a0, a2
+; RV32-NEXT:    beq a3, a1, .LBB22_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sltu a0, a1, a3
+; RV32-NEXT:    j .LBB22_3
 ; RV32-NEXT:  .LBB22_2:
+; RV32-NEXT:    sltu a0, a0, a2
+; RV32-NEXT:  .LBB22_3:
+; RV32-NEXT:    sw a2, 0(a4)
+; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo_ult_i64_math_overflow_used:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    sub a3, a0, a1
+; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    sltu a0, a0, a1
-; RV64-NEXT:    sd a3, 0(a2)
+; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
   %s = sub i64 %x, %y
   store i64 %s, ptr %p
   %ov = icmp ult i64 %x, %y
   ret i1 %ov
 }
 
 ; Verify insertion point for single-BB. Toggle predicate.
 
 define i1 @usubo_ugt_i32(i32 %x, i32 %y, ptr %p) {
 ; RV32-LABEL: usubo_ugt_i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    sltu a3, a0, a1
-; RV32-NEXT:    sub a0, a0, a1
-; RV32-NEXT:    sw a0, 0(a2)
-; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    sub a1, a0, a1
+; RV32-NEXT:    sltu a0, a0, a1
+; RV32-NEXT:    sw a1, 0(a2)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo_ugt_i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a3, a1
-; RV64-NEXT:    sext.w a4, a0
-; RV64-NEXT:    sltu a3, a4, a3
-; RV64-NEXT:    subw a0, a0, a1
-; RV64-NEXT:    sw a0, 0(a2)
-; RV64-NEXT:    mv a0, a3
+; RV64-NEXT:    subw a1, a0, a1
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    sltu a0, a0, a1
+; RV64-NEXT:    sw a1, 0(a2)
 ; RV64-NEXT:    ret
   %ov = icmp ugt i32 %y, %x
   %s = sub i32 %x, %y
   store i32 %s, ptr %p
   ret i1 %ov
 }
 
 ; Constant operand should match.

 }
 
 ; Special-case: subtract 1 changes the compare predicate and constant.
 
 define i1 @usubo_eq_constant1_op1_i32(i32 %x, ptr %p) {
 ; RV32-LABEL: usubo_eq_constant1_op1_i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a2, a0, -1
-; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo_eq_constant1_op1_i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a2, a0
-; RV64-NEXT:    addiw a3, a0, -1
-; RV64-NEXT:    seqz a0, a2
-; RV64-NEXT:    sw a3, 0(a1)
+; RV64-NEXT:    addiw a2, a0, -1
+; RV64-NEXT:    sext.w a0, a0
+; RV64-NEXT:    sltu a0, a0, a2
+; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
   %s = add i32 %x, -1
   %ov = icmp eq i32 %x, 0
   store i32 %s, ptr %p
   ret i1 %ov
 }
 
 ; Special-case: subtract from 0 (negate) changes the compare predicate.
 
 define i1 @usubo_ne_constant0_op1_i32(i32 %x, ptr %p) {
 ; RV32-LABEL: usubo_ne_constant0_op1_i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    neg a2, a0
-; RV32-NEXT:    snez a0, a0
+; RV32-NEXT:    snez a0, a2
 ; RV32-NEXT:    sw a2, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo_ne_constant0_op1_i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a2, a0
-; RV64-NEXT:    negw a3, a0
+; RV64-NEXT:    negw a2, a0
 ; RV64-NEXT:    snez a0, a2
-; RV64-NEXT:    sw a3, 0(a1)
+; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
   %s = sub i32 0, %x
   %ov = icmp ne i32 %x, 0
   store i32 %s, ptr %p
   ret i1 %ov
 }
 
 ; This used to verify insertion point for multi-BB, but now we just bail out.

 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    .cfi_offset s1, -12
 ; RV32-NEXT:    .cfi_offset s2, -16
 ; RV32-NEXT:    .cfi_offset s3, -20
 ; RV32-NEXT:    .cfi_offset s4, -24
 ; RV32-NEXT:    .cfi_offset s5, -28
 ; RV32-NEXT:    .cfi_offset s6, -32
-; RV32-NEXT:    mv s4, a5
+; RV32-NEXT:    mv s1, a5
 ; RV32-NEXT:    andi a5, a5, 1
-; RV32-NEXT:    beqz a5, .LBB31_8
+; RV32-NEXT:    beqz a5, .LBB31_7
 ; RV32-NEXT:  # %bb.1: # %t
 ; RV32-NEXT:    mv s0, a4
-; RV32-NEXT:    mv s3, a3
-; RV32-NEXT:    mv s1, a2
-; RV32-NEXT:    mv s5, a1
-; RV32-NEXT:    mv s2, a0
+; RV32-NEXT:    mv s5, a3
+; RV32-NEXT:    mv s4, a2
+; RV32-NEXT:    mv s2, a1
+; RV32-NEXT:    mv s3, a0
 ; RV32-NEXT:    beq a1, a3, .LBB31_3
 ; RV32-NEXT:  # %bb.2: # %t
-; RV32-NEXT:    sltu s6, s5, s3
+; RV32-NEXT:    sltu s6, s2, s5
 ; RV32-NEXT:    j .LBB31_4
 ; RV32-NEXT:  .LBB31_3:
-; RV32-NEXT:    sltu s6, s2, s1
+; RV32-NEXT:    sltu s6, s3, s4
 ; RV32-NEXT:  .LBB31_4: # %t
 ; RV32-NEXT:    mv a0, s6
 ; RV32-NEXT:    call call@plt
-; RV32-NEXT:    beqz s6, .LBB31_8
+; RV32-NEXT:    beqz s6, .LBB31_7
 ; RV32-NEXT:  # %bb.5: # %end
-; RV32-NEXT:    sltu a1, s2, s1
-; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:    beq s5, s3, .LBB31_7
+; RV32-NEXT:    sltu a0, s3, s4
+; RV32-NEXT:    sub a1, s2, s5
+; RV32-NEXT:    sub a1, a1, a0
+; RV32-NEXT:    sub a2, s3, s4
+; RV32-NEXT:    beq a1, s2, .LBB31_8
 ; RV32-NEXT:  # %bb.6: # %end
-; RV32-NEXT:    sltu a0, s5, s3
-; RV32-NEXT:  .LBB31_7: # %end
-; RV32-NEXT:    sub a2, s5, s3
-; RV32-NEXT:    sub a2, a2, a1
-; RV32-NEXT:    sub a1, s2, s1
-; RV32-NEXT:    sw a1, 0(s0)
-; RV32-NEXT:    sw a2, 4(s0)
+; RV32-NEXT:    sltu a0, s2, a1
 ; RV32-NEXT:    j .LBB31_9
-; RV32-NEXT:  .LBB31_8: # %f
-; RV32-NEXT:    mv a0, s4
-; RV32-NEXT:  .LBB31_9: # %f
+; RV32-NEXT:  .LBB31_7: # %f
+; RV32-NEXT:    mv a0, s1
+; RV32-NEXT:    j .LBB31_10
+; RV32-NEXT:  .LBB31_8:
+; RV32-NEXT:    sltu a0, s3, a2
+; RV32-NEXT:  .LBB31_9: # %end
+; RV32-NEXT:    sw a2, 0(s0)
+; RV32-NEXT:    sw a1, 4(s0)
+; RV32-NEXT:  .LBB31_10: # %f
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo_ult_cmp_dominates_i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -48
 ; RV64-NEXT:    .cfi_def_cfa_offset 48
 ; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    .cfi_offset s1, -24
 ; RV64-NEXT:    .cfi_offset s2, -32
 ; RV64-NEXT:    .cfi_offset s3, -40
-; RV64-NEXT:    .cfi_offset s4, -48
 ; RV64-NEXT:    mv s0, a3
 ; RV64-NEXT:    andi a3, a3, 1
 ; RV64-NEXT:    beqz a3, .LBB31_3
 ; RV64-NEXT:  # %bb.1: # %t
 ; RV64-NEXT:    mv s1, a2
-; RV64-NEXT:    mv s2, a1
-; RV64-NEXT:    mv s3, a0
-; RV64-NEXT:    sltu s4, a0, a1
-; RV64-NEXT:    mv a0, s4
+; RV64-NEXT:    mv s3, a1
+; RV64-NEXT:    mv s2, a0
+; RV64-NEXT:    sltu a0, a0, a1
 ; RV64-NEXT:    call call@plt
-; RV64-NEXT:    bgeu s3, s2, .LBB31_3
+; RV64-NEXT:    bgeu s2, s3, .LBB31_3
 ; RV64-NEXT:  # %bb.2: # %end
-; RV64-NEXT:    sub a0, s3, s2
-; RV64-NEXT:    sd a0, 0(s1)
-; RV64-NEXT:    mv a0, s4
+; RV64-NEXT:    sub a1, s2, s3
+; RV64-NEXT:    sltu a0, s2, a1
+; RV64-NEXT:    sd a1, 0(s1)
 ; RV64-NEXT:    j .LBB31_4
 ; RV64-NEXT:  .LBB31_3: # %f
 ; RV64-NEXT:    mv a0, s0
 ; RV64-NEXT:  .LBB31_4: # %f
 ; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 48
 ; RV64-NEXT:    ret
 entry:
   br i1 %cond, label %t, label %f
 
 t:
   %ov = icmp ult i64 %x, %y
   call void @call(i1 %ov)