This is an archive of the discontinued LLVM Phabricator instance.

Differential D145142

[X86] Add test for `~x & x` -> `0` in DAG Lowering; NFC
ClosedPublic

Authored by goldstein.w.n on Mar 1 2023, 11:43 PM.

Details

Reviewers
RKSimon
pengfei
Commits
rGc622c1383abb: [X86] Add test for `~x & x` -> `0` and `~x + x` -> `-1` in DAG Lowering; NFC

Diff Detail

Event Timeline

goldstein.w.n created this revision.Mar 1 2023, 11:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 1 2023, 11:43 PM
Herald added a subscriber: pengfei. · View Herald Transcript
goldstein.w.n requested review of this revision.Mar 1 2023, 11:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 1 2023, 11:43 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
goldstein.w.n added reviewers: RKSimon, pengfei.Mar 1 2023, 11:44 PM
goldstein.w.n added a child revision: D145143: [DAGCombiner] Add fold for `~x & x` -> `0`.
Harbormaster completed remote builds in B216913: Diff 501762.Mar 2 2023, 12:26 AM
goldstein.w.n updated this revision to Diff 501771.Mar 2 2023, 12:29 AM

Rebase

Harbormaster completed remote builds in B216918: Diff 501771.Mar 2 2023, 1:24 AM
RKSimon accepted this revision.Mar 2 2023, 2:04 AM

LGTM - but maybe name this combine-andn.ll ? Or just add them to combine-and.ll?

This revision is now accepted and ready to land.Mar 2 2023, 2:04 AM
goldstein.w.n updated this revision to Diff 501947.Mar 2 2023, 12:27 PM

Move and tests, add add tests

goldstein.w.n added a comment.Mar 2 2023, 12:27 PM
In D145142#4164133, @RKSimon wrote:

LGTM - but maybe name this combine-andn.ll ? Or just add them to combine-and.ll?

Done (also updated with ~x + x cases in combine-add.ll as we are missing combine there as well.

Harbormaster completed remote builds in B217030: Diff 501947.Mar 2 2023, 1:30 PM
goldstein.w.n updated this revision to Diff 502060.Mar 2 2023, 11:39 PM

Rebase

Harbormaster completed remote builds in B217117: Diff 502060.Mar 3 2023, 1:16 AM
Closed by commit rGc622c1383abb: [X86] Add test for `~x & x` -> `0` and `~x + x` -> `-1` in DAG Lowering; NFC (authored by goldstein.w.n). · Explain WhyMar 6 2023, 6:31 PM
This revision was automatically updated to reflect the committed changes.
goldstein.w.n added a commit: rGc622c1383abb: [X86] Add test for `~x & x` -> `0` and `~x + x` -> `-1` in DAG Lowering; NFC.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
62 lines
54 lines

Diff 502060

llvm/test/CodeGen/X86/combine-add.ll

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ny = xor i8 %y, -1 %ny = xor i8 %y, -1
%nz = xor i8 %z, -1 %nz = xor i8 %z, -1
%minxz = select i1 %b, i8 %x, i8 %nz %minxz = select i1 %b, i8 %x, i8 %nz
%cmpyz = icmp ult i8 %ny, %nz %cmpyz = icmp ult i8 %ny, %nz
%r = add i1 %cmpyz, true %r = add i1 %cmpyz, true
ret i1 %r ret i1 %r
} }
define <2 x i64> @add_vec_x_notx(<2 x i64> %v0) nounwind {
; SSE-LABEL: add_vec_x_notx:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm1
; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: add_vec_x_notx:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%x = xor <2 x i64> %v0, <i64 -1, i64 -1>
%y = add <2 x i64> %v0, %x
ret <2 x i64> %y
}
define <2 x i64> @add_vec_notx_x(<2 x i64> %v0) nounwind {
; SSE-LABEL: add_vec_notx_x:
; SSE: # %bb.0:
; SSE-NEXT: pcmpeqd %xmm1, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm1
; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: add_vec_notx_x:
; AVX: # %bb.0:
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpaddq %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
%x = xor <2 x i64> %v0, <i64 -1, i64 -1>
%y = add <2 x i64> %x, %v0
ret <2 x i64> %y
}
define i64 @add_x_notx(i64 %v0) nounwind {
; CHECK-LABEL: add_x_notx:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: retq
%x = xor i64 %v0, -1
%y = add i64 %v0, %x
ret i64 %y
}
define i64 @add_notx_x(i64 %v0) nounwind {
; CHECK-LABEL: add_notx_x:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: retq
%x = xor i64 %v0, -1
%y = add i64 %x, %v0
ret i64 %y
}

llvm/test/CodeGen/X86/combine-and.ll

Show First 20 Lines • Show All 1,170 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = xor i32 %a0, -1 %1 = xor i32 %a0, -1
%2 = insertelement <4 x i32> undef, i32 %1, i64 0 %2 = insertelement <4 x i32> undef, i32 %1, i64 0
%3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> zeroinitializer %3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> zeroinitializer
store <4 x i32> %3, ptr %a2, align 16 store <4 x i32> %3, ptr %a2, align 16
%4 = and <4 x i32> %3, %a1 %4 = and <4 x i32> %3, %a1
ret <4 x i32> %4 ret <4 x i32> %4
} }
define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {
; SSE-LABEL: andnp_xx:
; SSE: # %bb.0:
; SSE-NEXT: andnps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: andnp_xx:
; AVX: # %bb.0:
; AVX-NEXT: vandnps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%x = xor <2 x i64> %v0, <i64 -1, i64 -1>
%y = and <2 x i64> %v0, %x
ret <2 x i64> %y
}
define <2 x i64> @andnp_xx_2(<2 x i64> %v0) nounwind {
; SSE-LABEL: andnp_xx_2:
; SSE: # %bb.0:
; SSE-NEXT: andnps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: andnp_xx_2:
; AVX: # %bb.0:
; AVX-NEXT: vandnps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%x = xor <2 x i64> %v0, <i64 -1, i64 -1>
%y = and <2 x i64> %x, %v0
ret <2 x i64> %y
}
define i64 @andn_xx(i64 %v0) nounwind {
; CHECK-LABEL: andn_xx:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: andq %rdi, %rax
; CHECK-NEXT: retq
%x = xor i64 %v0, -1
%y = and i64 %v0, %x
ret i64 %y
}
define i64 @andn_xx_2(i64 %v0) nounwind {
; CHECK-LABEL: andn_xx_2:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: andq %rdi, %rax
; CHECK-NEXT: retq
%x = xor i64 %v0, -1
%y = and i64 %x, %v0
ret i64 %y
}