[AMDGPU][AsmParser][NFC] Refine immediate operand definitions.

[kosarev]

Rework smrd_literal_offset as well.

[kosarev]

@dp Ping.

[dp]

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

137

This redefinition is unnecessary, 'let' would suffice.

llvm/lib/Target/AMDGPU/SMInstructions.td

750

Shouldn't this operand be optional?

[kosarev]

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

137

Can you elaborate? I'm not sure I understand the suggestion.

llvm/lib/Target/AMDGPU/SMInstructions.td

750

Nope, isSMRDLiteralOffset() doesn't accept zeroes.

[dp]

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

137

It looks like the code

AsmOperandClass ParserMatchClass = ImmOperandClass<name, optional>;

may be simplified as follows:

let ParserMatchClass = ImmOperandClass<name, optional>;

llvm/lib/Target/AMDGPU/SMInstructions.td

750

Oh I see, thanks.

[kosarev]

The redefinition fixed.

[dp]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

 def NoFP64Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
 }
 
 def FMA : Predicate<"Subtarget->hasFMA()">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 
-def u16ImmTarget : AsmOperandClass {
-  let Name = "U16Imm";
+class ImmOperandClass<string name, bit optional> : AsmOperandClass {
+  let Name = name;
+  let PredicateMethod = "is"#name;
+  let ParserMethod = "";
   let RenderMethod = "addImmOperands";
+  let IsOptional = optional;
+  let DefaultMethod = "default"#name;
 }
 
-def s16ImmTarget : AsmOperandClass {
-  let Name = "S16Imm";
-  let RenderMethod = "addImmOperands";
-}
-
-let OperandType = "OPERAND_IMMEDIATE" in {
-
-def u16imm : Operand<i16> {
-  let PrintMethod = "printU16ImmOperand";
-  let ParserMatchClass = u16ImmTarget;
-}
-
-def s16imm : Operand<i16> {
-  let PrintMethod = "printU16ImmOperand";
-  let ParserMatchClass = s16ImmTarget;
+class ImmOperand<ValueType type, string name, bit optional = 0,
+                 string printer = "print"#name> : Operand<type> {
+  AsmOperandClass ParserMatchClass = ImmOperandClass<name, optional>;
+  let PrintMethod = printer;
+  let OperandType = "OPERAND_IMMEDIATE";
 }
 
-} // End OperandType = "OPERAND_IMMEDIATE"
+def s16imm : ImmOperand<i16, "S16Imm", 0, "printU16ImmOperand">;
+def u16imm : ImmOperand<i16, "U16Imm", 0, "printU16ImmOperand">;
 
 //===--------------------------------------------------------------------===//
 // Custom Operands
 //===--------------------------------------------------------------------===//
 def brtarget   : Operand<OtherVT>;
 
 //===----------------------------------------------------------------------===//
 // Misc. PatFrags

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 // It appears to be necessary to create a separate operand for this to
 // be able to parse attr<num> with no space.
 def Attr : Operand<i32> {
   let PrintMethod = "printInterpAttr";
   let ParserMatchClass = AttrMatchClass;
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
-def AttrChanMatchClass : AsmOperandClass {
-  let Name = "AttrChan";
-  let PredicateMethod = "isAttrChan";
-  let RenderMethod = "addImmOperands";
-}
-
-def AttrChan : Operand<i32> {
-  let PrintMethod = "printInterpAttrChan";
-  let ParserMatchClass = AttrChanMatchClass;
-  let OperandType = "OPERAND_IMMEDIATE";
-}
+def AttrChan : ImmOperand<i32, "AttrChan", 0, "printInterpAttrChan">;
 
 def SendMsgMatchClass : AsmOperandClass {
   let Name = "SendMsg";
   let PredicateMethod = "isSendMsg";
   let ParserMethod = "parseSendMsgOp";
   let RenderMethod = "addImmOperands";
 }
 

llvm/lib/Target/AMDGPU/SMInstructions.td

 //===---- SMInstructions.td - Scalar Memory Instruction Definitions -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
-                                  NamedMatchClass<"SMRDOffset8">> {
-  let OperandType = "OPERAND_IMMEDIATE";
-}
+def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
 
 let OperandType = "OPERAND_IMMEDIATE",
     EncoderMethod = "getSMEMOffsetEncoding",
     DecoderMethod = "decodeSMEMOffset" in {
-def smem_offset : NamedOperandU32<"SMEMOffset", NamedMatchClass<"SMEMOffset">>;
+def smem_offset : ImmOperand<i32, "SMEMOffset", 1>;
 def smem_offset_mod : NamedIntOperand<i32, "offset", "SMEMOffsetMod">;
 }
 
 //===----------------------------------------------------------------------===//
 // Scalar Memory classes
 //===----------------------------------------------------------------------===//
 
 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :

 
 defm S_DCACHE_DISCARD    : SM_Real_Discard_vi <0x28, "S_DCACHE_DISCARD">;
 defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29, "S_DCACHE_DISCARD_X2">;
 
 //===----------------------------------------------------------------------===//
 // CI
 //===----------------------------------------------------------------------===//
 
-def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
-                                          NamedMatchClass<"SMRDLiteralOffset">> {
-  let OperandType = "OPERAND_IMMEDIATE";
-}
+def smrd_literal_offset : ImmOperand<i32, "SMRDLiteralOffset">;
 
 class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
   SM_Real<ps>,
   Enc64 {
 
   let AssemblerPredicate = isGFX7Only;
   let DecoderNamespace = "GFX7";
   let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);