[SPARC][IAS] Add support for v9 DONE, RETRY, SAVED, & RESTORED

[koakuma]

Summary

Add support for DONE, RETRY, SAVED, and RESTORED (v9 §A.11 & §A.47).
Those instructions are used for low-level interrupt handling and register window management by OS kernels.

[jrtc27]

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

667

Shouldn't this be impossible due to the predicate, and thus be an assert?

674

isUInt<32>(ImmValue)?

680

Use MCInstBuilder throughout? Avoids all the { ... } below, too...

1149

Use a TableGen GenericTable for this to avoid having to define the forward mapping here and the backward mapping later? (See RISCVSystemOperands.td for an example).

[koakuma]

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

667

Probably just me misunderstanding it but during testing I found out that even with 32-bit -mtriple=sparc it still recognizes SETX anyway, that's why I'm putting the condition as a normal error instead of an assert.

[koakuma]

Implement review suggestions:

• Use isUInt<32>(ImmValue) instead of manually checking ranges
• Use MCInstBuilder to expand setx pseudoinstruction
• Create a table to hold ASI symbolic names

[koakuma]

Ping?

[arsenm]

llvm/lib/Target/Sparc/SparcInstrInfo.td

1834–1838

I'm confused by what this comment means, as you're defining a new instruction. Is the intent to define an assembler alias only?

[koakuma]

llvm/lib/Target/Sparc/SparcInstrInfo.td

1834–1838

Yeah, my intent is to define a rdpr %fq, $rd alias, but the encoding of %fq is different between v8 and v9 versions of the ISA, so I had to do that to convince the assembler to encode it properly when emitting code for v9.
Should I do it in a different way?

[koakuma]

Ping?

[barannikov88]

It looks like there are several independent changes. A few smaller diffs would be much easier to review.

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

442

It should have its own Kind and union member. Not sure if tablegen provides you with an enum, but if it does, the enum could be used.
This is "safer" and allows you to avoid converting to MCExpr and back.

1138

Why not just getTok().is(AsmToken::Integer) and getTok().getIntVal() on success?

1146

Is space after '#' allowed? If not, getLexer().peekToken(false) should be used.

1165

The location is not precise. It points before the last whitespace (there may be several).
Ideally, you would getTok().getEndLoc() before Lex()ing the indentifier or the number.

1276

This should return MatchOperand_ParseFail. NoMatch implies no tokens were consumed.

1291

Missing return?

1295

Why is LParen here?

1661–1724

Do you know why Sparc does not use autogenerated MatchRegisterName? (ShouldEmitMatchRegisterName = 0 in Sparc.td.)

llvm/lib/Target/Sparc/SparcASITags.td

16–21 ↗

(On Diff #510183)

It looks like all tags have an alternative name, just pass it as template parameter.

llvm/lib/Target/Sparc/SparcInstrAliases.td

513

It should be simm13Op, though it does not currently matter that much as it is missing AsmOperandClass, so no overflow checking is done.

[koakuma]

In D144936#4325027, @barannikov88 wrote:

It looks like there are several independent changes. A few smaller diffs would be much easier to review.

Any advice on how to split it? This is basically just a bunch of instruction definitions, the complication mostly arises since some of the parsing needs to be handled on the C++ side.

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

442

Not entirely sure if I can/how to do this, any example code I can refer to?

1138

Same reason with the LParen matcher, this is to handle constant expressions for ASI identifier.
We want to evaluate those expressions before proceeding further.

1291

Should be no problem since it'll fall through the if check below it, but will anyway for clarity, thanks.

1295

Because using a constant expression for ASI identifier value (for example ldxa [%o0] (0x80 + 0x08), %o1) is also legal.
Is there a better way to detect/process it?

1661–1724

Unfortunately no. I am still new to the backend so for these parts of the code I'm just following what the original code already does.
I guess I'll try it out and see if I could use autogenerated MatchRegisterName.
(But it's probably better to do it in a separate patch? I'm not sure)

[koakuma]

Implement suggested changes.

[MaskRay]

llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

18

The indentation seems unnecessary. It seems that we can unindent all instructions. That's the more common style for instruction encoding in other targets' testing as well.

[barannikov88]

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

442

Roughly:

• Add a new enum member to KindTy, e.g. k_ASITag
• Make isASITag return true if the kind is k_ASITag
• Add a new member to the anonymous union in SparcOperand that will hold the ASI tag number (unsigned integer probably)
• Add SparcOperand::CreateASITag accepting ASI tag number, use this method in parseASITag instead of CreateImm
• Update SparcOperand::print and addASITagOperands accordingly

1138

I'd personally prefer parseExpression() instead of parseSparcAsmOperand() if the first token is not '#'. Up to you.

1291

Actually there was a problem because parseSparcAsmOperand consumes tokens :)
I think there is another issue now -- what happens if there was a '%' but parseSparcAsmOperand didn't return success?

1295

Because using a constant expression for ASI identifier value (for example ldxa [%o0] (0x80 + 0x08), %o1) is also legal.

That's weird. Can you add a couple of testcases using this syntax?

Is there a better way to detect/process it?

I think not.

[koakuma]

• Implement formatting suggestions for new testfile
• Add constant expression forms of tests
• Fix return value for CAS operands parsing
• Add separate enum kind for ASI tags

llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

18

I can do that with new testfiles, but for old ones I feel like it's better to follow old formattings?
At least I feel like for those files it's better to reformat in a new patch instead of here.

[barannikov88]

Looks fine to me. It would still be better to create separate revisions for independent changes.

[brad]

@arsenm Ping.

[arsenm]

Code seems mostly fine but I know nothing about sparc

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

688–692

Initialize with ternary operator?

1284

needing allocation for MC operands seems unusual?

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

245

Single quotes

[koakuma]

Apply code change suggestions.

[brad]

@arsenm @jrtc27 Ping.

[brad]

In D144936#4525415, @brad wrote:

@arsenm @jrtc27 Ping.

@arsenm @jrtc27 Ping.

[barannikov88]

I still think the best way forward is to split this set of changes into several. It would be much easier to review, ensure test coverage is sufficient and commit messages would be more helpful.
I can see several independent changes here (I may have missed something):

• Adding DONE/RETRY/SAVED/RESTORED instructions
• Adding RDFQ variant
• Adding CAS variants
• Adding SETX pseudo instruction
• Adding reg+imm mode to some memory instructions
• Adding new mnemonics to control registers
• Supporting ASI tags
• Other minor changes

[arsenm]

I think the code looks fine but I know nothing about SPARC. Don't really care about splitting this up or not, though I generally prefer minimal patches

[koakuma]

Split other changes into D157230, D157231, D157232, D157233, D157234, D157235, and D157236.

[barannikov88]

LGTM

[barannikov88]

Please add a disassembler test.

[koakuma]

Add disassembly tests.

[glaubitz]

@barannikov88 Can you land this change?

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

#include "SparcGenAsmMatcher.inc"
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   // Custom parse functions for Sparc specific operands.
   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
 
   OperandMatchResultTy parseMembarTag(OperandVector &Operands);
 
+  OperandMatchResultTy parseASITag(OperandVector &Operands);
+
   template <TailRelocKind Kind>
   OperandMatchResultTy parseTailRelocSym(OperandVector &Operands);
 
   template <unsigned N>
   OperandMatchResultTy parseShiftAmtImm(OperandVector &Operands);
 
   OperandMatchResultTy parseCallTarget(OperandVector &Operands);
 
#include "SparcGenAsmMatcher.inc"
 
   bool is64Bit() const {
     return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
   }
 
   bool expandSET(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandSETX(MCInst &Inst, SMLoc IDLoc,
+                  SmallVectorImpl<MCInst> &Instructions);
+
   SMLoc getLoc() const { return getParser().getTok().getLoc(); }
 
 public:
   SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII,
                 const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
     Parser.addAliasForDirective(".half", ".2byte");
public:
 
   bool isToken() const override { return Kind == k_Token; }
   bool isReg() const override { return Kind == k_Register; }
   bool isImm() const override { return Kind == k_Immediate; }
   bool isMem() const override { return isMEMrr() || isMEMri(); }
   bool isMEMrr() const { return Kind == k_MemoryReg; }
   bool isMEMri() const { return Kind == k_MemoryImm; }
   bool isMembarTag() const { return Kind == k_Immediate; }
+  bool isASITag() const { return Kind == k_Immediate; }
   bool isTailRelocSym() const { return Kind == k_Immediate; }
 
   bool isCallTarget() const {
     if (!isImm())
       return false;
 
     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val))
       return CE->getValue() % 4 == 0;
public:
   }
 
   void addMembarTagOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCExpr *Expr = getImm();
     addExpr(Inst, Expr);
   }
 
+  void addASITagOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCExpr *Expr = getImm();
+    addExpr(Inst, Expr);
+  }
+
   void addCallTargetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
   }
 
   void addTailRelocSymOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
     TmpInst.addOperand(MCRegOp);
     TmpInst.addOperand(PrevReg);
     TmpInst.addOperand(MCOperand::createExpr(Expr));
     Instructions.push_back(TmpInst);
   }
   return false;
 }
 
+bool SparcAsmParser::expandSETX(MCInst &Inst, SMLoc IDLoc,
+                                SmallVectorImpl<MCInst> &Instructions) {
+  MCOperand MCRegOp = Inst.getOperand(0);
+  MCOperand MCValOp = Inst.getOperand(1);
+  MCOperand MCTmpOp = Inst.getOperand(2);
+  assert(MCRegOp.isReg() && MCTmpOp.isReg());
+  assert(MCValOp.isImm() || MCValOp.isExpr());
+
+  if (!is64Bit())
+    return Error(IDLoc, "setx is only available in 64-bit mode");
+
+  // the imm operand can be either an expression or an immediate.
+  bool IsImm = Inst.getOperand(1).isImm();
+  int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
+
+  // Small positive immediates effectively becomes a `set`.
+  if (ImmValue > 0LL && ImmValue <= 4294967295LL)
+    return expandSET(Inst, IDLoc, Instructions);
+
+  // Small negative immediates can be expressed directly as a single `or`.
+  bool IsSmallNegative = ImmValue >= -4096 && ImmValue <= 0;
+  if (IsImm && IsSmallNegative) {
+    MCInst TmpInst;
+    const MCExpr *Expr = MCConstantExpr::create(ImmValue, getContext());
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::ORri);
+    TmpInst.addOperand(MCRegOp);
+    TmpInst.addOperand(MCOperand::createReg(Sparc::G0));
+    TmpInst.addOperand(MCOperand::createExpr(Expr));
+    Instructions.push_back(TmpInst);
+    return false;
+  }
+
+  // All other cases simply expand to a fixed sequence.
+  const MCExpr *ValExpr;
+  if (IsImm)
+    ValExpr = MCConstantExpr::create(ImmValue, getContext());
+  else
+    ValExpr = MCValOp.getExpr();
+
+  // sethi %hh(val), tmp
+  {
+    MCInst TmpInst;
+    const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HH, ValExpr);
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::SETHIi);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(MCOperand::createExpr(Expr));
+    Instructions.push_back(TmpInst);
+  }
+
+  // sethi %hi(val), rd
+  {
+    MCInst TmpInst;
+    const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr);
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::SETHIi);
+    TmpInst.addOperand(MCRegOp);
+    TmpInst.addOperand(MCOperand::createExpr(Expr));
+    Instructions.push_back(TmpInst);
+  }
+
+  // or    tmp, %hm(val), tmp
+  {
+    MCInst TmpInst;
+    const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HM, ValExpr);
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::ORri);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(MCOperand::createExpr(Expr));
+    Instructions.push_back(TmpInst);
+  }
+
+  // or    rd, %lo(val), rd
+  {
+    MCInst TmpInst;
+    const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::ORri);
+    TmpInst.addOperand(MCRegOp);
+    TmpInst.addOperand(MCRegOp);
+    TmpInst.addOperand(MCOperand::createExpr(Expr));
+    Instructions.push_back(TmpInst);
+  }
+
+  // sllx  tmp, 32, tmp
+  {
+    MCInst TmpInst;
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::SLLXri);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(
+        MCOperand::createExpr(MCConstantExpr::create(32, getContext())));
+    Instructions.push_back(TmpInst);
+  }
+
+  // or    tmp, rd, rd
+  {
+    MCInst TmpInst;
+    TmpInst.setLoc(IDLoc);
+    TmpInst.setOpcode(SP::ORrr);
+    TmpInst.addOperand(MCRegOp);
+    TmpInst.addOperand(MCTmpOp);
+    TmpInst.addOperand(MCRegOp);
+    Instructions.push_back(TmpInst);
+  }
+
+  return false;
+}
+
 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                              OperandVector &Operands,
                                              MCStreamer &Out,
                                              uint64_t &ErrorInfo,
                                              bool MatchingInlineAsm) {
   MCInst Inst;
   SmallVector<MCInst, 8> Instructions;
   unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
                                               MatchingInlineAsm);
   switch (MatchResult) {
   case Match_Success: {
     switch (Inst.getOpcode()) {
     default:
       Inst.setLoc(IDLoc);
       Instructions.push_back(Inst);
       break;
     case SP::SET:
       if (expandSET(Inst, IDLoc, Instructions))
         return true;
       break;
+    case SP::SETX:
+      if (expandSETX(Inst, IDLoc, Instructions))
+        return true;
+      break;
     }
 
     for (const MCInst &I : Instructions) {
       Out.emitInstruction(I, getSTI());
     }
     return false;
   }
 
OperandMatchResultTy SparcAsmParser::parseMembarTag(OperandVector &Operands) {
   }
 
   EVal = MCConstantExpr::create(ImmVal, getContext());
   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(SparcOperand::CreateImm(EVal, S, E));
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy SparcAsmParser::parseASITag(OperandVector &Operands) {
+  SMLoc S = Parser.getTok().getLoc();
+  const MCExpr *EVal;
+  int64_t ASIVal = 0;
+
+  std::unique_ptr<SparcOperand> Mask;
+  if (parseSparcAsmOperand(Mask) == MatchOperand_Success) {
+    if (!Mask->isImm() || !Mask->getImm()->evaluateAsAbsolute(ASIVal) ||
+        ASIVal < 0 || ASIVal > 255) {
+      Error(S, "invalid ASI number");
+      return MatchOperand_ParseFail;
+    }
+  } else if (getLexer().getKind() == AsmToken::Hash) {
+    SMLoc TagStart = getLexer().getLoc();
+    Parser.Lex(); // Eat the '#'.
+
+    ASIVal = StringSwitch<int64_t>(Parser.getTok().getString())
+                 .Case("ASI_N", 0x4)
+                 .Case("ASI_N_L", 0xC)
+                 .Case("ASI_AIUP", 0x10)
+                 .Case("ASI_AIUS", 0x11)
+                 .Case("ASI_AIUP_L", 0x18)
+                 .Case("ASI_AIUS_L", 0x19)
+                 .Case("ASI_P", 0x80)
+                 .Case("ASI_S", 0x81)
+                 .Case("ASI_PNF", 0x82)
+                 .Case("ASI_SNF", 0x83)
+                 .Case("ASI_P_L", 0x88)
+                 .Case("ASI_S_L", 0x89)
+                 .Case("ASI_PNF_L", 0x8A)
+                 .Case("ASI_SNF_L", 0x8B)
+                 .Case("ASI_NUCLEUS", 0x4)
+                 .Case("ASI_NUCLEUS_L", 0xC)
+                 .Case("ASI_AS_IF_USER_PRIMARY", 0x10)
+                 .Case("ASI_AS_IF_USER_SECONDARY", 0x11)
+                 .Case("ASI_AS_IF_USER_PRIMARY_LITTLE", 0x18)
+                 .Case("ASI_AS_IF_USER_SECONDARY_LITTLE", 0x19)
+                 .Case("ASI_PRIMARY", 0x80)
+                 .Case("ASI_SECONDARY", 0x81)
+                 .Case("ASI_PRIMARY_NOFAULT", 0x82)
+                 .Case("ASI_SECONDARY_NOFAULT", 0x83)
+                 .Case("ASI_PRIMARY_LITTLE", 0x88)
+                 .Case("ASI_SECONDADY_LITTLE", 0x89)
+                 .Case("ASI_PRIMARY_NOFAULT_LITTLE", 0x8A)
+                 .Case("ASI_SECONDARY_NOFAULT_LITTLE", 0x8B)
+                 .Default(-1);
+    Parser.Lex(); // Eat the identifier token.
+
+    if (ASIVal == -1) {
+      Error(TagStart, "unknown ASI tag");
+      return MatchOperand_ParseFail;
+    }
+  } else {
+    Error(S, "malformed ASI tag");
+    return MatchOperand_ParseFail;
+  }
+
+  EVal = MCConstantExpr::create(ASIVal, getContext());
+  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+  Operands.push_back(SparcOperand::CreateImm(EVal, S, E));
+  return MatchOperand_Success;
+}
+
 OperandMatchResultTy SparcAsmParser::parseCallTarget(OperandVector &Operands) {
   SMLoc S = Parser.getTok().getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
 
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;
   case AsmToken::LParen:
if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
     return ResTy;
 
   if (getLexer().is(AsmToken::LBrac)) {
     // Memory operand
     Operands.push_back(SparcOperand::CreateToken("[",
                                                  Parser.getTok().getLoc()));
     Parser.Lex(); // Eat the [
 
-    if (Mnemonic == "cas" || Mnemonic == "casx" || Mnemonic == "casa") {
+    if (Mnemonic == "cas" || Mnemonic == "casl" || Mnemonic == "casa" ||
+        Mnemonic == "casx" || Mnemonic == "casxl" || Mnemonic == "casxa") {
       SMLoc S = Parser.getTok().getLoc();
       if (getLexer().getKind() != AsmToken::Percent)
         return MatchOperand_NoMatch;
       Parser.Lex(); // eat %
 
       MCRegister RegNo;
       unsigned RegKind;
       if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
if (getLexer().is(AsmToken::LBrac)) {
     if (!getLexer().is(AsmToken::RBrac))
       return MatchOperand_ParseFail;
 
     Operands.push_back(SparcOperand::CreateToken("]",
                                                  Parser.getTok().getLoc()));
     Parser.Lex(); // Eat the ]
 
     // Parse an optional address-space identifier after the address.
-    if (getLexer().is(AsmToken::Integer)) {
+    // This will be either the %asi register, or an immediate constant
+    // expression, or a named tag.
+    if (getLexer().is(AsmToken::Percent)) {
       std::unique_ptr<SparcOperand> Op;
-      ResTy = parseSparcAsmOperand(Op, false);
-      if (ResTy != MatchOperand_Success || !Op)
+      if (parseSparcAsmOperand(Op) == MatchOperand_Success && Op) {
+        if (!Op->isReg() || Op->getReg() != Sparc::ASI)
+          return MatchOperand_NoMatch;
+        // Here we patch the MEM operand from [base + %g0] into [base + 0]
+        // as memory operations with ASI tag stored in %asi register needs
+        // to use immediate offset.
+        SparcOperand &OldMemOp = (SparcOperand &)*Operands[Operands.size() - 2];
+        if (OldMemOp.isMEMrr()) {
+          if (OldMemOp.getMemOffsetReg() != Sparc::G0)
             return MatchOperand_ParseFail;
+          std::unique_ptr<SparcOperand> NewMemOp = SparcOperand::MorphToMEMri(
+              OldMemOp.getMemBase(),
+              SparcOperand::CreateImm(MCConstantExpr::create(0, getContext()),
+                                      OldMemOp.getStartLoc(),
+                                      OldMemOp.getEndLoc()));
+          Operands[Operands.size() - 2] = std::move(NewMemOp);
+        }
         Operands.push_back(std::move(Op));
       }
+    }
+
+    if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::LParen) ||
+        getLexer().is(AsmToken::Hash))
+      return parseASITag(Operands);
     return MatchOperand_Success;
   }
 
   std::unique_ptr<SparcOperand> Op;
 
   ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
   if (ResTy != MatchOperand_Success || !Op)
     return MatchOperand_ParseFail;
if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
         Op = SparcOperand::CreateToken("%cq", S);
         break;
       case Sparc::WIM:
         Op = SparcOperand::CreateToken("%wim", S);
         break;
       case Sparc::TBR:
         Op = SparcOperand::CreateToken("%tbr", S);
         break;
-      case Sparc::PC:
-        Op = SparcOperand::CreateToken("%pc", S);
-        break;
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
       }
       break;
if (Tok.is(AsmToken::Identifier)) {
 
     if (name.substr(0, 3).equals_insensitive("asr") &&
         !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
       RegNo = ASRRegs[intVal];
       RegKind = SparcOperand::rk_Special;
       return true;
     }
 
-    // %fprs is an alias of %asr6.
     if (name.equals("fprs")) {
-      RegNo = ASRRegs[6];
+      RegNo = Sparc::FPRS;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     if (name.equals("icc")) {
       RegNo = Sparc::ICC;
       RegKind = SparcOperand::rk_Special;
       return true;
if (name.equals("wstate")) {
       RegNo = Sparc::WSTATE;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
     if (name.equals("pc")) {
       RegNo = Sparc::PC;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
+    if (name.equals("asi")) {
+      RegNo = Sparc::ASI;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("ccr")) {
+      RegNo = Sparc::CCR;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("gl")) {
+      RegNo = Sparc::GL;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("ver")) {
+      RegNo = Sparc::VER;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+
+    // JPS1 extension - aliases for ASRs
+    // Section A.51 - Read State Register
+    if (name.equals("pcr")) {
+      RegNo = Sparc::ASR16;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("pic")) {
+      RegNo = Sparc::ASR17;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("dcr")) {
+      RegNo = Sparc::ASR18;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("gsr")) {
+      RegNo = Sparc::ASR19;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("softint")) {
+      RegNo = Sparc::ASR22;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("tick_cmpr")) {
+      RegNo = Sparc::ASR23;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("stick") || name.equals("sys_tick")) {
+      RegNo = Sparc::ASR24;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("stick_cmpr") || name.equals("sys_tick_cmpr")) {
+      RegNo = Sparc::ASR25;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
   }
   return false;
 }
 
 // Determine if an expression contains a reference to the symbol
 // "_GLOBAL_OFFSET_TABLE_".
 static bool hasGOTReference(const MCExpr *Expr) {
   switch (Expr->getKind()) {

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

static const unsigned QFPRegDecoderTable[] = {
   SP::Q5,  SP::Q13,  ~0U,  ~0U,
   SP::Q6,  SP::Q14,  ~0U,  ~0U,
   SP::Q7,  SP::Q15,  ~0U,  ~0U } ;
 
 static const unsigned FCCRegDecoderTable[] = {
   SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
 
 static const unsigned ASRRegDecoderTable[] = {
-  SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
-  SP::ASR4,  SP::ASR5,  SP::ASR6,  SP::ASR7,
-  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
-  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
-  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
-  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
-  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
+    SP::Y,     SP::ASR1,  SP::CCR,   SP::ASI,   SP::TICK,  SP::PC,    SP::FPRS,
+    SP::ASR7,  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,
+    SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,
+    SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
     SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
 
 static const unsigned PRRegDecoderTable[] = {
-  SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
-  SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
-  SP::OTHERWIN, SP::WSTATE, SP::PC
-};
+    SP::TPC,     SP::TNPC,       SP::TSTATE,   SP::TT,       SP::TICK,
+    SP::TBA,     SP::PSTATE,     SP::TL,       SP::PIL,      SP::CWP,
+    SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE};
 
 static const uint16_t IntPairDecoderTable[] = {
   SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
   SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
   SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
   SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
 };
 
DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (STI.hasFeature(Sparc::FeatureV9))
   {
     Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
   }
   else
   {
     Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
   }
-  if (Result != MCDisassembler::Fail)
+  if (Result != MCDisassembler::Fail) {
+    Size = 4;
     return Result;
+  }
 
   Result =
       decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
 
   if (Result != MCDisassembler::Fail) {
     Size = 4;
     return Result;
   }

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h

public:
   void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                        raw_ostream &OS, const char *Modifier = nullptr);
   void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                       raw_ostream &OS);
   bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &OS);
   void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                       raw_ostream &O);
+  void printASITag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

void SparcInstPrinter::printMembarTag(const MCInst *MI, int opNum,
   bool First = true;
   for (unsigned i = 0; i < std::size(TagNames); i++) {
     if (Imm & (1 << i)) {
       O << (First ? "" : " | ") << TagNames[i];
       First = false;
     }
   }
 }
+
+void SparcInstPrinter::printASITag(const MCInst *MI, int opNum,
+                                   const MCSubtargetInfo &STI, raw_ostream &O) {
+  unsigned Imm = MI->getOperand(opNum).getImm();
+
+  switch (Imm) {
+  case 0x04:
+    O << "#ASI_N";
+    break;
+  case 0x0C:
+    O << "#ASI_N_L";
+    break;
+  case 0x10:
+    O << "#ASI_AIUP";
+    break;
+  case 0x11:
+    O << "#ASI_AIUS";
+    break;
+  case 0x18:
+    O << "#ASI_AIUP_L";
+    break;
+  case 0x19:
+    O << "#ASI_AIUS_L";
+    break;
+  case 0x80:
+    O << "#ASI_P";
+    break;
+  case 0x81:
+    O << "#ASI_S";
+    break;
+  case 0x82:
+    O << "#ASI_PNF";
+    break;
+  case 0x83:
+    O << "#ASI_SNF";
+    break;
+  case 0x88:
+    O << "#ASI_P_L";
+    break;
+  case 0x89:
+    O << "#ASI_S_L";
+    break;
+  case 0x8A:
+    O << "#ASI_PNF_L";
+    break;
+  case 0x8B:
+    O << "#ASI_SNF_L";
+    break;
+  default:
+    O << Imm;
+    break;
+  }
+}

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
 // Word).
 //
 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
 
 let Predicates = [Is64Bit] in {
 
 // 64-bit loads.
-defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
+defm LDX   : LoadA<"ldx", 0b001011, 0b011011, load, I64Regs, i64>;
 
 let mayLoad = 1, isAsmParserOnly = 1 in {
   def TLS_LDXrr : F3_1<3, 0b001011,
                        (outs IntRegs:$rd),
                        (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
                        "ldx [$addr], $rd, $sym",
                        [(set i64:$rd,
                            (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;

 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
 
 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
 def : Pat<(i64 (extloadi32 ADDRrr:$addr)),  (LDrr ADDRrr:$addr)>;
 def : Pat<(i64 (extloadi32 ADDRri:$addr)),  (LDri ADDRri:$addr)>;
 
 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
-defm LDSW   : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
+defm LDSW   : LoadA<"ldsw", 0b001000, 0b011000, sextloadi32, I64Regs, i64>;
 
 // 64-bit stores.
-defm STX    : Store<"stx", 0b001110, store,  I64Regs, i64>;
+defm STX    : StoreA<"stx", 0b001110, 0b011110, store, I64Regs, i64>;
 
 // Truncating stores from i64 are identical to the i32 stores.
 def : Pat<(truncstorei8  i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei8  i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr  ADDRrr:$addr, $src)>;
 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri  ADDRri:$addr, $src)>;

 let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
 def SETHIXi : F2_1<0b100,
                    (outs IntRegs:$rd), (ins i64imm:$imm22),
                    "sethi $imm22, $rd",
                    [(set i64:$rd, SETHIimm:$imm22)]>;
 }
 
 // ATOMICS.
-let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
+let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
+  let asi = 0b10000000 in
     def CASXrr: F3_1_asi<3, 0b111110,
                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
                                      I64Regs:$swap),
                  "casx [$rs1], $rs2, $rd",
                  [(set i64:$rd,
                      (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>;
 
+  let asi = 0b10001000 in
+    def CASXLrr: F3_1_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap),
+                 "casxl [$rs1], $rs2, $rd",
+                 []>;
+
+  def CASXArr: F3_1_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap, ASITag:$asi),
+                 "casxa [$rs1] $asi, $rs2, $rd",
+                 []>;
+
+  def CASXAri: F3_1_cas_asi<3, 0b111110,
+                (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
+                                     I64Regs:$swap, ASRRegs:$asr),
+                 "casxa [$rs1] $asr, $rs2, $rd",
+                 []>;
 } // Predicates = [Is64Bit], Constraints = ...
 
 let Predicates = [Is64Bit] in {
 
 // atomic_load_64 addr -> load addr
 def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
 def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>;
 

llvm/lib/Target/Sparc/SparcInstrAliases.td

 defm : int_cond_alias<"cs",   0b0101>;
 defm : int_cond_alias<"pos",  0b1110>;
 defm : int_cond_alias<"neg",  0b0110>;
 defm : int_cond_alias<"vc",   0b1111>;
 defm : int_cond_alias<"vs",   0b0111>;
 let EmitPriority = 0 in
 {
   defm : int_cond_alias<"",     0b1000>; // same as a; gnu asm, not in manual
+  defm : int_cond_alias<"gt",   0b0011>; // same as g; gnu asm, not in manual
+  defm : int_cond_alias<"lt",   0b0011>; // same as l; gnu asm, not in manual
   defm : int_cond_alias<"nz",   0b1001>; // same as ne
   defm : int_cond_alias<"eq",   0b0001>; // same as e
   defm : int_cond_alias<"z",    0b0001>; // same as e
   defm : int_cond_alias<"geu",  0b1101>; // same as cc
   defm : int_cond_alias<"lu",   0b0101>; // same as cs
 }
 defm : fp_cond_alias<"a",     0b1000>;
 defm : fp_cond_alias<"n",     0b0000>;

 // save -> restore %g0, %g0, %g0
 def : InstAlias<"save", (SAVErr G0, G0, G0)>;
 
 // set value, rd
 // (turns into a sequence of sethi+or, depending on the value)
 // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
 
+// setx value, tmp, rd
+// (turns into a sequence of sethi+or+shift, depending on the value)
+def SETX : AsmPseudoInst<(outs I64Regs:$rd),
+  (ins i64imm:$val, I64Regs:$tmp),
+  "setx $val, $tmp, $rd">,
+  Requires<[Is64Bit]>;
+
 // not rd -> xnor rd, %g0, rd
 def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
 
 // not reg, rd -> xnor reg, %g0, rd
 def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
 
 // neg rd -> sub %g0, rd, rd
 def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;

 // clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
 def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
 def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
 def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
 def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
 def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
 def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
 
-
 // mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
 
 // mov specialreg, rd -> rd specialreg, rd
 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
-def : InstAlias<"mov %pc, $rd", (RDPC IntRegs:$rd), 0>;
+def : InstAlias<"mov %pc, $rd", (RDASR IntRegs:$rd, PC), 0>;
 
 // mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
 
+// or imm, reg, rd -> or reg, imm, rd
+// Nonstandard GNU extension.
+let EmitPriority = 0 in
+  def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, i32imm:$simm13)>;
+
 // End of Section A.3
 
 // wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
 // (aka: omit the first arg when it's g0. This is not in the manual, but is
 // supported by gnu and solaris as)
 def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
 def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
 def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;

 def : MnemonicAlias<"stuba", "stba">;
 def : MnemonicAlias<"stsba", "stba">;
 
 def : MnemonicAlias<"stuh", "sth">;
 def : MnemonicAlias<"stsh", "sth">;
 
 def : MnemonicAlias<"stuha", "stha">;
 def : MnemonicAlias<"stsha", "stha">;
+
 def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>;
+def : MnemonicAlias<"stuw", "st">, Requires<[HasV9]>;
+def : MnemonicAlias<"stsw", "st">, Requires<[HasV9]>;
+
+def : MnemonicAlias<"stwa", "sta">, Requires<[HasV9]>;
+def : MnemonicAlias<"stuwa", "sta">, Requires<[HasV9]>;
+def : MnemonicAlias<"stswa", "sta">, Requires<[HasV9]>;
 
 def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
 def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
 
 def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
 
 def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
 def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;

llvm/lib/Target/Sparc/SparcInstrFormats.td

class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
   let op         = opVal;
   let op3        = op3val;
 
   let Inst{13}   = 0;     // i field = 0
   let Inst{12-5} = asi;   // address space identifier
   let Inst{4-0}  = rs2;
 }
 
+// CAS instructions does not use an immediate even when i=1
+class F3_1_cas_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+           string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
+   : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
+  let asi = 0;
+  let Inst{13}   = 1;     // i field = 1
+}
+
 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
        list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
   : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
   let asi = 0;
 }
 
 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
            string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>

llvm/lib/Target/Sparc/SparcInstrInfo.td

def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
              AssemblerPredicate<(all_of FeatureVIS2)>;
 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
              AssemblerPredicate<(all_of FeatureVIS3)>;
 
 // HasHardQuad - This is true when the target processor supports quad floating
 // point instructions.
 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
 
-// HasLeonCASA - This is true when the target processor supports the CASA
+// HasLeonCASA - This is true when the target processor supports the Leon CASA
 // instruction
 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
 
+// HasCAS - This is true when the target processor supports CASA instruction.
+def HasCAS : Predicate<"Subtarget->hasLeonCasa() || Subtarget->isV9()">;
+
 // HasPWRPSR - This is true when the target processor supports partial
 // writes to the PSR register that only affects the ET field.
 def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
                 AssemblerPredicate<(all_of FeaturePWRPSR)>;
 
 // HasUMAC_SMAC - This is true when the target processor supports the
 // UMAC and SMAC instructions
 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
def SparcMembarTagAsmOperand : AsmOperandClass {
   let ParserMethod = "parseMembarTag";
 }
 
 def MembarTag : Operand<i32> {
   let PrintMethod = "printMembarTag";
   let ParserMatchClass = SparcMembarTagAsmOperand;
 }
 
+def SparcASITagAsmOperand : AsmOperandClass {
+  let Name = "ASITag";
+  let ParserMethod = "parseASITag";
+}
+
+def ASITag : Operand<i32> {
+  let PrintMethod = "printASITag";
+  let ParserMatchClass = SparcASITagAsmOperand;
+}
+
 // Branch targets have OtherVT type.
 def brtarget : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValue";
 }
 
 def bprtarget : Operand<OtherVT> {
   let EncoderMethod = "getBranchPredTargetOpValue";
 }
def ri  : F3_2<3, Op3Val,
                  (outs RC:$rd), (ins (MEMri $rs1, $simm13):$addr),
                  !strconcat(OpcStr, " [$addr], $rd"),
                  [(set Ty:$rd, (OpNode ADDRri:$addr))],
                  itin>;
 }
 
 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
 // CodeGen's address spaces to use these is a future task.
-class LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> :
-  F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi),
+multiclass LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> {
+  def rr  : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
                      !strconcat(OpcStr, "a [$addr] $asi, $rd"),
                      []>;
 
+  let Predicates = [HasV9] in
+  def ri  : F3_2<3, Op3Val, (outs RC:$rd), (ins (MEMri $rs1, $simm13):$addr, ASRRegs:$asr),
+                 !strconcat(OpcStr, "a [$addr] $asr, $rd"),
+                 []>;
+}
+
 // LoadA multiclass - As above, but also define alternate address space variant
 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
                  InstrItinClass itin = NoItinerary> :
              Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
-  def Arr  : LoadASI<OpcStr, LoadAOp3Val, RC>;
+  defm A   : LoadASI<OpcStr, LoadAOp3Val, RC>;
 }
 
 // The LDSTUB instruction is supported for asm only.
 // It is unlikely that general-purpose code could make use of it.
 // CAS is preferred for sparc v9.
 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
                     "ldstub [$addr], $rd", []>;
 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
                     "ldstub [$addr], $rd", []>;
 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
-                         (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi),
+                         (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
                          "ldstuba [$addr] $asi, $rd", []>;
+let Predicates = [HasV9] in
+def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
+                         (ins (MEMrr $rs1, $simm13):$addr, ASRRegs:$asr),
+                         "ldstuba [$addr] $asr, $rd", []>;
 
 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
            RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
   def rr  : F3_1<3, Op3Val,
                  (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRrr:$addr)],
                  itin>;
   def ri  : F3_2<3, Op3Val,
                  (outs), (ins (MEMri $rs1, $simm13):$addr, RC:$rd),
                  !strconcat(OpcStr, " $rd, [$addr]"),
                  [(OpNode Ty:$rd, ADDRri:$addr)],
                  itin>;
 }
 
 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
 // CodeGen's address spaces to use these is a future task.
-class StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC,
-               InstrItinClass itin = IIC_st> :
-  F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, i8imm:$asi),
+multiclass StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC,
+               InstrItinClass itin = IIC_st> {
+  def rr : F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, ASITag:$asi),
            !strconcat(OpcStr, "a $rd, [$addr] $asi"),
            [],
            itin>;
 
+  let Predicates = [HasV9] in
+  def ri : F3_2<3, Op3Val, (outs), (ins (MEMri $rs1, $simm13):$addr, RC:$rd, ASRRegs:$asr),
+           !strconcat(OpcStr, "a $rd, [$addr] $asr"),
+           [],
+           itin>;
+}
+
 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
                   SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
              Store<OpcStr, Op3Val, OpNode, RC, Ty> {
-  def Arr : StoreASI<OpcStr, StoreAOp3Val, RC>;
+  defm A   : StoreASI<OpcStr, StoreAOp3Val, RC>;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 // Pseudo instructions.
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>

 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
 defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
 
 // Section B.2 - Load Floating-point Instructions, p. 92
-defm LDF   : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
-def LDFArr : LoadASI<"ld",  0b110000, FPRegs>,
-             Requires<[HasV9]>;
-
-defm LDDF   : Load<"ldd", 0b100011, load,    DFPRegs, f64, IIC_ldd>;
-def LDDFArr : LoadASI<"ldd", 0b110011, DFPRegs>,
-              Requires<[HasV9]>;
-defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
-             Requires<[HasV9, HasHardQuad]>;
+defm LDF     : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
+defm LDDF    : Load<"ldd", 0b100011, load,    DFPRegs, f64, IIC_ldd>;
+
+let DecoderNamespace = "SparcV9", Predicates = [HasV9] in {
+  defm LDFA    : LoadASI<"ld",  0b110000, FPRegs>;
+  defm LDDFA   : LoadASI<"ldd", 0b110011, DFPRegs>;
+  defm LDQF    : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
+                 Requires<[HasHardQuad]>;
+}
 
-defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
+// Coprocessor instructions were removed in v9.
+let DecoderNamespace = "SparcV8", Predicates = [HasNoV9] in {
+  defm LDC    : Load<"ld", 0b110000, load, CoprocRegs, i32>;
   defm LDDC   : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
+}
 
 let Defs = [CPSR] in {
   let rd = 0 in {
     def LDCSRrr : F3_1<3, 0b110001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
                        "ld [$addr], %csr", []>;
     def LDCSRri : F3_2<3, 0b110001, (outs), (ins (MEMri $rs1, $simm13):$addr),
                        "ld [$addr], %csr", []>;
   }

 // Section B.4 - Store Integer Instructions, p. 95
 defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
 defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
 defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
 defm STD   : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>;
 
 // Section B.5 - Store Floating-point Instructions, p. 97
 defm STF    : Store<"st",  0b100100, store,         FPRegs,  f32>;
-def STFArr  : StoreASI<"st",  0b110100, FPRegs>,
-              Requires<[HasV9]>;
 defm STDF   : Store<"std", 0b100111, store,         DFPRegs, f64, IIC_std>;
-def STDFArr : StoreASI<"std", 0b110111, DFPRegs>,
-              Requires<[HasV9]>;
-defm STQF   : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
-              Requires<[HasV9, HasHardQuad]>;
+
+let DecoderNamespace = "SparcV9", Predicates = [HasV9] in {
+  defm STFA  : StoreASI<"st",  0b110100, FPRegs>;
+  defm STDFA : StoreASI<"std", 0b110111, DFPRegs>;
+  defm STQF  : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
+              Requires<[HasHardQuad]>;
+}
 
+// Coprocessor instructions were removed in v9.
+let DecoderNamespace = "SparcV8", Predicates = [HasNoV9] in {
   defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>;
   defm STDC   : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
+}
 
 let rd = 0 in {
   let Defs = [CPSR] in {
     def STCSRrr : F3_1<3, 0b110101, (outs (MEMrr $rs1, $rs2):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
     def STCSRri : F3_2<3, 0b110101, (outs (MEMri $rs1, $simm13):$addr), (ins),
                        "st %csr, [$addr]", [], IIC_st>;
   }
def SWAPrr : F3_1<3, 0b001111,
                  (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),
                  "swap [$addr], $rd",
                  [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
   def SWAPri : F3_2<3, 0b001111,
                  (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr, IntRegs:$val),
                  "swap [$addr], $rd",
                  [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
   def SWAPArr : F3_1_asi<3, 0b011111,
-                 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, i8imm:$asi, IntRegs:$val),
+                 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, IntRegs:$val),
                  "swapa [$addr] $asi, $rd",
                  [/*FIXME: pattern?*/]>;
 }
 
 
 // Section B.9 - SETHI Instruction, p. 104
 def SETHIi: F2_1<0b100,
                  (outs IntRegs:$rd), (ins i32imm:$imm22),

 
 
 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
   def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
 
 let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in
   def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>;
 
-// Section B.28 - Read State Register Instructions
+// Section B.28 (v8) - Read State Register Instructions
+// Section A.44 (v9) - Read State Register
 let rs2 = 0 in
   def RDASR : F3_1<2, 0b101000,
                  (outs IntRegs:$rd), (ins ASRRegs:$rs1),
                  "rd $rs1, $rd", []>;
 
 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
 let Predicates = [HasNoV9] in {
   let rs2 = 0, rs1 = 0, Uses=[PSR] in
     def RDPSR : F3_1<2, 0b101001,
          (outs IntRegs:$rd), (ins),
          "rd %psr, $rd", []>;
 
   let rs2 = 0, rs1 = 0, Uses=[WIM] in
     def RDWIM : F3_1<2, 0b101010,
          (outs IntRegs:$rd), (ins),
          "rd %wim, $rd", []>;
 
   let rs2 = 0, rs1 = 0, Uses=[TBR] in
     def RDTBR : F3_1<2, 0b101011,
          (outs IntRegs:$rd), (ins),
          "rd %tbr, $rd", []>;
 }
 
-// PC don't exist on the SparcV8, only the V9.
-let Predicates = [HasV9] in {
-  let rs2 = 0, rs1 = 5 in
-    def RDPC : F3_1<2, 0b101000,
-         (outs IntRegs:$rd), (ins),
-         "rd %pc, $rd", []>;
-}
-
 // Section B.29 - Write State Register Instructions
 def WRASRrr : F3_1<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                  "wr $rs1, $rs2, $rd", []>;
 def WRASRri : F3_2<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                  "wr $rs1, $simm13, $rd", []>;
 
def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),
                     "membar $simm13", []>;
 
 let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in
   def SIR: F3_2<2, 0b110000, (outs),
                 (ins simm13Op:$simm13),
                  "sir $simm13", []>;
 
 // The CAS instruction, unlike other instructions, only comes in a
-// form which requires an ASI be provided. The ASI value hardcoded
-// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
-let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
+// form which requires an ASI be provided.
+let Predicates = [HasV9], Constraints = "$swap = $rd" in {
+  // The ASI value hardcoded here is ASI_PRIMARY, the default
+  // unprivileged ASI for SparcV9.
+  let asi = 0b10000000 in
     def CASrr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "cas [$rs1], $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
+  // SparcV9 also specifies a CASL alias, which uses ASI_PRIMARY_LITTLE.
+  let asi = 0b10001000 in
+    def CASLrr: F3_1_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap),
+                 "casl [$rs1], $rs2, $rd",
+                 []>;
+}
+
 
 // CASA is supported as an instruction on some LEON3 and all LEON4 processors.
 // This version can be automatically lowered from C code, selecting ASI 10
 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
   def CASAasi10: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
                                      IntRegs:$swap),
                  "casa [$rs1] 10, $rs2, $rd",
                  [(set i32:$rd,
                      (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
 
-// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
-// CASrr, above, but with a different ASI. This version is supported for
-// inline assembly lowering only.
-let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
+// CASA supported on all V9, some LEON3 and all LEON4 processors.
+// Same pattern as CASrr above, but with a different ASI.
+// This version is supported for inline assembly lowering only.
+let Predicates = [HasCAS], Constraints = "$swap = $rd" in
   def CASArr: F3_1_asi<3, 0b111100,
                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
-                                     IntRegs:$swap, i8imm:$asi),
+                                     IntRegs:$swap, ASITag:$asi),
                  "casa [$rs1] $asi, $rs2, $rd", []>;
 
+// On the other hand, CASA that takes its ASI from a register
+// is only supported on V9 processors.
+let Predicates = [HasV9], Constraints = "$swap = $rd" in
+  def CASAri: F3_1_cas_asi<3, 0b111100,
+                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
+                                     IntRegs:$swap, ASRRegs:$asr),
+                 "casa [$rs1] $asr, $rs2, $rd", []>;
+
 // TODO: Add DAG sequence to lower these instructions. Currently, only provided
 // as inline assembler-supported instructions.
 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
   def SMACrr :  F3_1<2, 0b111111,
                    (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
                    "smac $rs1, $rs2, $rd",
                    [], IIC_smac_umac>;
 

 defm TSUBCC   : F3_12np<"tsubcc",   0b100001>;
 
 let hasSideEffects = 1 in {
   defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
   defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
 }
 }
 
+// Section A.11 - DONE and RETRY
+// Section A.47 - SAVED and RESTORED
+let Predicates = [HasV9], rs1 = 0, rs2 = 0 in {
+  let rd = 0 in
+    def DONE : F3_1<2, 0b111110, (outs), (ins), "done", []>;
+
+  let rd = 1 in
+    def RETRY : F3_1<2, 0b111110, (outs), (ins), "retry", []>;
+
+  let rd = 0 in
+    def SAVED : F3_1<2, 0b110001, (outs), (ins), "saved", []>;
+
+  let rd = 1 in
+    def RESTORED : F3_1<2, 0b110001, (outs), (ins), "restored", []>;
+}
+
 // Section A.42 - Prefetch Data
 let Predicates = [HasV9] in {
   def PREFETCHr : F3_1<3, 0b101101,
                    (outs), (ins (MEMrr $rs1, $rs2):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
   def PREFETCHi : F3_2<3, 0b101101,
                    (outs), (ins (MEMri $rs1, $simm13):$addr, shift_imm5:$rd),
                    "prefetch [$addr], $rd", []>;
 }
 
 
 
 // Section A.43 - Read Privileged Register Instructions
 let Predicates = [HasV9] in {
 let rs2 = 0 in
   def RDPR : F3_1<2, 0b101010,
                  (outs IntRegs:$rd), (ins PRRegs:$rs1),
                  "rdpr $rs1, $rd", []>;
+
+// Special case %fq as the register is also used in V8
+// (albeit with different instructions and encoding)
+// This allows us to reuse the register definition and
+// the "%fq" designation while giving it a different encoding.
+let Uses = [FQ], rs1 = 15, rs2 = 0 in
+  def RDFQ : F3_1<2, 0b101010,
+                 (outs IntRegs:$rd), (ins),
+                 "rdpr %fq, $rd", []>;
 }
 
 // Section A.62 - Write Privileged Register Instructions
 let Predicates = [HasV9] in {
   def WRPRrr : F3_1<2, 0b110010,
                    (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                    "wrpr $rs1, $rs2, $rd", []>;
   def WRPRri : F3_2<2, 0b110010,

llvm/lib/Target/Sparc/SparcRegisterInfo.td

 def ASR29 : SparcCtrlReg<29, "ASR29">;
 def ASR30 : SparcCtrlReg<30, "ASR30">;
 def ASR31 : SparcCtrlReg<31, "ASR31">;
 
 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
 def PSR : SparcCtrlReg<0, "PSR">;
 def WIM : SparcCtrlReg<0, "WIM">;
 def TBR : SparcCtrlReg<0, "TBR">;
-// PC on the other hand is only available for SparcV9.
-def PC : SparcCtrlReg<5, "PC">;
 
-def TPC : SparcCtrlReg<0, "TPC">;
-def TNPC : SparcCtrlReg<1, "TNPC">;
-def TSTATE : SparcCtrlReg<2, "TSTATE">;
-def TT : SparcCtrlReg<3, "TT">;
-def TICK : SparcCtrlReg<4, "TICK">;
-def TBA : SparcCtrlReg<5, "TBA">;
-def PSTATE : SparcCtrlReg<6, "PSTATE">;
-def TL : SparcCtrlReg<7, "TL">;
-def PIL : SparcCtrlReg<8, "PIL">;
-def CWP : SparcCtrlReg<9, "CWP">;
-def CANSAVE : SparcCtrlReg<10, "CANSAVE">;
+// The rest of the state registers on the other hand is only available for SparcV9.
+// Unprivileged V9 state registers
+def CCR        : SparcCtrlReg<2, "CCR">;
+def ASI        : SparcCtrlReg<3, "ASI">;
+def PC         : SparcCtrlReg<5, "PC">;
+def FPRS       : SparcCtrlReg<6, "FPRS">;
+// %tick can be read by both privileged and unprivileged instructions,
+// but can only be written by privileged instructions.
+def TICK       : SparcCtrlReg<4, "TICK">;
+// Privileged V9 state registers
+def TPC        : SparcCtrlReg<0, "TPC">;
+def TNPC       : SparcCtrlReg<1, "TNPC">;
+def TSTATE     : SparcCtrlReg<2, "TSTATE">;
+def TT         : SparcCtrlReg<3, "TT">;
+def TBA        : SparcCtrlReg<5, "TBA">;
+def PSTATE     : SparcCtrlReg<6, "PSTATE">;
+def TL         : SparcCtrlReg<7, "TL">;
+def PIL        : SparcCtrlReg<8, "PIL">;
+def CWP        : SparcCtrlReg<9, "CWP">;
+def CANSAVE    : SparcCtrlReg<10, "CANSAVE">;
 def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">;
-def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">;
-def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
-def WSTATE : SparcCtrlReg<14, "WSTATE">;
+def CLEANWIN   : SparcCtrlReg<12, "CLEANWIN">;
+def OTHERWIN   : SparcCtrlReg<13, "OTHERWIN">;
+def WSTATE     : SparcCtrlReg<14, "WSTATE">;
+def GL         : SparcCtrlReg<16, "GL">;
+def VER        : SparcCtrlReg<31, "VER">;
 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]> {
   let isConstant = true;
 }
 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;

 def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;
 
 // Floating point control register classes.
 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
 
 let isAllocatable = 0 in {
   // Ancillary state registers
   def ASRRegs : RegisterClass<"SP", [i32], 32,
-                              (add Y, (sequence "ASR%u", 1, 31))>;
+                              (add Y, CCR, ASI, TICK, PC, FPRS,
+                               (sequence "ASR%u", 1, 31))>;
 
   // This register class should not be used to hold i64 values.
   def CoprocRegs : RegisterClass<"SP", [i32], 32,
                                 (add (sequence "C%u", 0, 31))>;
 
   // Should be in the same order as CoprocRegs.
   def CoprocPair : RegisterClass<"SP", [v2i32], 64,
     (add C0_C1,   C2_C3,   C4_C5,   C6_C7,
          C8_C9,   C10_C11, C12_C13, C14_C15,
          C16_C17, C18_C19, C20_C21, C22_C23,
          C24_C25, C26_C27, C28_C29, C30_C31)>;
 }
 
 // Privileged Registers
 def PRRegs : RegisterClass<"SP", [i64], 64,
     (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
-         CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;
-
+         CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE, GL, VER)>;

llvm/test/MC/Disassembler/Sparc/sparc-mem.txt

 # RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux | FileCheck %s
 
 # CHECK:      ldsb [%i0+%l6], %o2
 0xd4 0x4e 0x00 0x16
 
 # CHECK:      ldsb [%i0+32], %o2
 0xd4 0x4e 0x20 0x20
 
 # CHECK:      ldsb [%g1], %o4
 0xd8 0x48 0x60 0x00
 
 # CHECK:      ldsb [%g1], %o4
 0xd8 0x48 0x40 0x00
 
-# CHECK:      ldsba [%i0+%l6] 131, %o2
+# CHECK:      ldsba [%i0+%l6] #ASI_SNF, %o2
 0xd4 0xce 0x10 0x76
 
 # CHECK:      ldsh [%i0+%l6], %o2
 0xd4 0x56 0x00 0x16
 
 # CHECK:      ldsh [%i0+32], %o2
 0xd4 0x56 0x20 0x20
 
 # CHECK:      ldsh [%g1], %o4
 0xd8 0x50 0x60 0x00
 
 # CHECK:      ldsh [%g1], %o4
 0xd8 0x50 0x40 0x00
 
-# CHECK:      ldsha [%i0+%l6] 131, %o2
+# CHECK:      ldsha [%i0+%l6] #ASI_SNF, %o2
 0xd4 0xd6 0x10 0x76
 
 # CHECK:      ldub [%i0+%l6], %o2
 0xd4 0x0e 0x00 0x16
 
 # CHECK:      ldub [%i0+32], %o2
 0xd4 0x0e 0x20 0x20
 
 # CHECK:      ldub [%g1], %o2
 0xd4 0x08 0x60 0x00
 
 # CHECK:      ldub [%g1], %o2
 0xd4 0x08 0x40 0x00
 
-# CHECK:      lduba [%i0+%l6] 131, %o2
+# CHECK:      lduba [%i0+%l6] #ASI_SNF, %o2
 0xd4 0x8e 0x10 0x76
 
 # CHECK:      lduh [%i0+%l6], %o2
 0xd4 0x16 0x00 0x16
 
 # CHECK:      lduh [%i0+32], %o2
 0xd4 0x16 0x20 0x20
 
 # CHECK:      lduh [%g1], %o2
 0xd4 0x10 0x60 0x00
 
 # CHECK:      lduh [%g1], %o2
 0xd4 0x10 0x40 0x00
 
-# CHECK:      lduha [%i0+%l6] 131, %o2
+# CHECK:      lduha [%i0+%l6] #ASI_SNF, %o2
 0xd4 0x96 0x10 0x76
 
 # CHECK:      ld [%i0+%l6], %o2
 0xd4 0x06 0x00 0x16
 
 # CHECK:      ld [%i0+32], %o2
 0xd4 0x06 0x20 0x20
 
 # CHECK:      ld [%g1], %o2
 0xd4 0x00 0x60 0x00
 
 # CHECK:      ld [%g1], %o2
 0xd4 0x00 0x40 0x00
 
-# CHECK:      lda [%i0+%l6] 131, %o2
+# CHECK:      lda [%i0+%l6] #ASI_SNF, %o2
 0xd4 0x86 0x10 0x76
 
 # CHECK:     ld [%i0+%l6], %f2
 0xc5 0x06 0x00 0x16
 
 # CHECK:     ld [%i0+32], %f2
 0xc5 0x06 0x20 0x20
 
 # CHECK:     ld [%g1], %f2
 0xc5 0x00 0x60 0x00
 
 # CHECK:     ld [%g1], %f2
 0xc5 0x00 0x40 0x00
 
-# CHECK:     lda [%i0+%l6] 131, %f2
+# CHECK:     lda [%i0+%l6] #ASI_SNF, %f2
 0xc5 0x86 0x10 0x76
 
 # CHECK:     ldd [%i0+%l6], %f2
 0xc5 0x1e 0x00 0x16
 
 # CHECK:     ldd [%i0+32], %f2
 0xc5 0x1e 0x20 0x20
 
 # CHECK:     ldd [%g1], %f2
 0xc5 0x18 0x60 0x00
 
 # CHECK:     ldd [%g1], %f2
 0xc5 0x18 0x40 0x00
 
-# CHECK:     ldda [%i0+%l6] 131, %f2
+# CHECK:     ldda [%i0+%l6] #ASI_SNF, %f2
 0xc5 0x9e 0x10 0x76
 
 # CHECK:     ldq [%i0+%l6], %f4
 0xc9 0x16 0x00 0x16
 
 # CHECK:     ldq [%i0+32], %f4
 0xc9 0x16 0x20 0x20
 

 0xd4 0x2e 0x20 0x20
 
 # CHECK:      stb %o2, [%g1]
 0xd4 0x28 0x60 0x00
 
 # CHECK:      stb %o2, [%g1]
 0xd4 0x28 0x40 0x00
 
-# CHECK:      stba %o2, [%i0+%l6] 131
+# CHECK:      stba %o2, [%i0+%l6] #ASI_SNF
 0xd4 0xae 0x10 0x76
 
 # CHECK:      sth %o2, [%i0+%l6]
 0xd4 0x36 0x00 0x16
 
 # CHECK:      sth %o2, [%i0+32]
 0xd4 0x36 0x20 0x20
 
 # CHECK:      sth %o2, [%g1]
 0xd4 0x30 0x60 0x00
 
 # CHECK:      sth %o2, [%g1]
 0xd4 0x30 0x40 0x00
 
-# CHECK:      stha %o2, [%i0+%l6] 131
+# CHECK:      stha %o2, [%i0+%l6] #ASI_SNF
 0xd4 0xb6 0x10 0x76
 
 # CHECK:      st %o2, [%i0+%l6]
 0xd4 0x26 0x00 0x16
 
 # CHECK:      st %o2, [%i0+32]
 0xd4 0x26 0x20 0x20
 
 # CHECK:      st %o2, [%g1]
 0xd4 0x20 0x60 0x00
 
 # CHECK:      st %o2, [%g1]
 0xd4 0x20 0x40 0x00
 
-# CHECK:      sta %o2, [%i0+%l6] 131
+# CHECK:      sta %o2, [%i0+%l6] #ASI_SNF
 0xd4 0xa6 0x10 0x76
 
 # CHECK:      st %f2, [%i0+%l6]
 0xc5 0x26 0x00 0x16
 
 # CHECK:      st %f2, [%i0+32]
 0xc5 0x26 0x20 0x20
 
 # CHECK:      st %f2, [%g1]
 0xc5 0x20 0x60 0x00
 
 # CHECK:      st %f2, [%g1]
 0xc5 0x20 0x40 0x00
 
-# CHECK:      sta %f2, [%i0+%l6] 131
+# CHECK:      sta %f2, [%i0+%l6] #ASI_SNF
 0xc5 0xa6 0x10 0x76
 
 # CHECK:      std %f2, [%i0+%l6]
 0xc5 0x3e 0x00 0x16
 
 # CHECK:      std %f2, [%i0+32]
 0xc5 0x3e 0x20 0x20
 
 # CHECK:      std %f2, [%g1]
 0xc5 0x38 0x60 0x00
 
 # CHECK:      std %f2, [%g1]
 0xc5 0x38 0x40 0x00
 
-# CHECK:      stda %f2, [%i0+%l6] 131
+# CHECK:      stda %f2, [%i0+%l6] #ASI_SNF
 0xc5 0xbe 0x10 0x76
 
 # CHECK:      stq %f4, [%i0+%l6]
 0xc9 0x36 0x00 0x16
 
 # CHECK:      stq %f4, [%i0+32]
 0xc9 0x36 0x20 0x20
 

 0xd4 0x7e 0x20 0x20
 
 # CHECK:     swap [%g1], %o2
 0xd4 0x78 0x60 0x00
 
 # CHECK:     swap [%g1], %o2
 0xd4 0x78 0x40 0x00
 
-# CHECK:     swapa [%i0+%l6] 131, %o2
+# CHECK:     swapa [%i0+%l6] #ASI_SNF, %o2
 0xd4 0xfe 0x10 0x76
 
-# CHECK:     swapa [%g1] 131, %o2
+# CHECK:     swapa [%g1] #ASI_SNF, %o2
 0xd4 0xf8 0x50 0x60
 
 # CHECK:     ldd [%i0+%l6], %o2
 0xd4 0x1e 0x00 0x16
 
 # CHECK:     ldd [%i0+32], %o2
 0xd4 0x1e 0x20 0x20
 

 0xd4 0x3e 0x20 0x20
 
 # CHECK:     std %o2, [%g1]
 0xd4 0x38 0x60 0x00
 
 # CHECK:     std %o2, [%g1]
 0xd4 0x38 0x40 0x00
 
-# CHECK:     stda %o2, [%i0+%l6] 131
+# CHECK:     stda %o2, [%i0+%l6] #ASI_SNF
 0xd4 0xbe 0x10 0x76
 
 # CHECK:     ldstub [%i0+%l6], %o2
 0xd4 0x6e 0x00 0x16
 
 # CHECK:     ldstub [%i0+32], %o2
 0xd4 0x6e 0x20 0x20
 
 # CHECK:     ldstub [%g1], %o2
 0xd4 0x68 0x60 0x00
 
 # CHECK:     ldstub [%g1], %o2
 0xd4 0x68 0x40 0x00
 
-# CHECK:     ldstuba [%i0+%l6] 131, %o2
+# CHECK:     ldstuba [%i0+%l6] #ASI_SNF, %o2
 0xd4 0xee 0x10 0x76
 
-# CHECK:     ldstuba [%g1] 131, %o2
+# CHECK:     ldstuba [%g1] #ASI_SNF, %o2
 0xd4 0xe8 0x50 0x60
 
 # CHECK:     flush %g1+%g2
 0x81 0xd8 0x40 0x02
 
 # CHECK:     flush %g1+8
 0x81 0xd8 0x60 0x08
 

llvm/test/MC/Sparc/sparc-atomic-instructions.s

 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
 
         ! CHECK: stbar                 ! encoding: [0x81,0x43,0xc0,0x00]
         stbar
 
         ! CHECK: swap [%i0+%l6], %o2   ! encoding: [0xd4,0x7e,0x00,0x16]
         swap [%i0+%l6], %o2
 
         ! CHECK: swap [%i0+32], %o2    ! encoding: [0xd4,0x7e,0x20,0x20]
         swap [%i0+32], %o2
 
-        ! CHECK: swapa [%i0+%l6] 131, %o2   ! encoding: [0xd4,0xfe,0x10,0x76]
+        ! CHECK: swapa [%i0+%l6] #ASI_SNF, %o2   ! encoding: [0xd4,0xfe,0x10,0x76]
         swapa [%i0+%l6] 131, %o2
 
         ! CHECK: ldstub [%i0+40], %g1 ! encoding: [0xc2,0x6e,0x20,0x28]
         ldstub [%i0+40], %g1
 
         ! CHECK: ldstub [%i0+%i2], %g1 ! encoding: [0xc2,0x6e,0x00,0x1a]
         ldstub [%i0+%i2], %g1
 
-        ! CHECK: ldstuba [%i0+%i2] 131, %g1 ! encoding: [0xc2,0xee,0x10,0x7a]
+        ! CHECK: ldstuba [%i0+%i2] #ASI_SNF, %g1 ! encoding: [0xc2,0xee,0x10,0x7a]
         ldstuba [%i0+%i2] 131, %g1

llvm/test/MC/Sparc/sparc-mem-instructions.s

 ! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 
         ! CHECK: ldsb [%i0+%l6], %o2  ! encoding: [0xd4,0x4e,0x00,0x16]
         ldsb [%i0 + %l6], %o2
         ! CHECK: ldsb [%i0+32], %o2   ! encoding: [0xd4,0x4e,0x20,0x20]
         ldsb [%i0 + 32], %o2
         ! CHECK: ldsb [%g1], %o4      ! encoding: [0xd8,0x48,0x40,0x00]
         ldsb [%g1], %o4
-        ! CHECK: ldsba [%i0+%l6] 131, %o2  ! encoding: [0xd4,0xce,0x10,0x76]
+        ! CHECK: ldsba [%i0+%l6] #ASI_SNF, %o2  ! encoding: [0xd4,0xce,0x10,0x76]
         ldsba [%i0 + %l6] 131, %o2
 
         ! CHECK: ldsh [%i0+%l6], %o2  ! encoding: [0xd4,0x56,0x00,0x16]
         ldsh [%i0 + %l6], %o2
         ! CHECK: ldsh [%i0+32], %o2   ! encoding: [0xd4,0x56,0x20,0x20]
         ldsh [%i0 + 32], %o2
         ! CHECK: ldsh [%g1], %o4      ! encoding: [0xd8,0x50,0x40,0x00]
         ldsh [%g1], %o4
-        ! CHECK: ldsha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0xd6,0x10,0x76]
+        ! CHECK: ldsha [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0xd6,0x10,0x76]
         ldsha [%i0 + %l6] 131, %o2
 
         ! CHECK: ldub [%i0+%l6], %o2  ! encoding: [0xd4,0x0e,0x00,0x16]
         ldub [%i0 + %l6], %o2
         ! CHECK: ldub [%i0+32], %o2   ! encoding: [0xd4,0x0e,0x20,0x20]
         ldub [%i0 + 32], %o2
         ! CHECK: ldub [%g1], %o2      ! encoding: [0xd4,0x08,0x40,0x00]
         ldub [%g1], %o2
-        ! CHECK: lduba [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x8e,0x10,0x76]
+        ! CHECK: lduba [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x8e,0x10,0x76]
         lduba [%i0 + %l6] 131, %o2
 
         ! CHECK: lduh [%i0+%l6], %o2  ! encoding: [0xd4,0x16,0x00,0x16]
         lduh [%i0 + %l6], %o2
         ! CHECK: lduh [%i0+32], %o2   ! encoding: [0xd4,0x16,0x20,0x20]
         lduh [%i0 + 32], %o2
         ! CHECK: lduh [%g1], %o2      ! encoding: [0xd4,0x10,0x40,0x00]
         lduh [%g1], %o2
-        ! CHECK: lduha [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x96,0x10,0x76]
+        ! CHECK: lduha [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x96,0x10,0x76]
         lduha [%i0 + %l6] 131, %o2
 
         ! CHECK: ld [%i0+%l6], %o2    ! encoding: [0xd4,0x06,0x00,0x16]
         ld [%i0 + %l6], %o2
         ! CHECK: ld [%i0+32], %o2     ! encoding: [0xd4,0x06,0x20,0x20]
         ld [%i0 + 32], %o2
         ! CHECK: ld [%g1], %o2        ! encoding: [0xd4,0x00,0x40,0x00]
         ld [%g1], %o2
-        ! CHECK: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
+        ! CHECK: lda [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
         lda [%i0 + %l6] 131, %o2
 
         ! CHECK: ldd [%i0+%l6], %o2    ! encoding: [0xd4,0x1e,0x00,0x16]
         ldd [%i0 + %l6], %o2
         ! CHECK: ldd [%i0+32], %o2     ! encoding: [0xd4,0x1e,0x20,0x20]
         ldd [%i0 + 32], %o2
         ! CHECK: ldd [%g1], %o2        ! encoding: [0xd4,0x18,0x40,0x00]
         ldd [%g1], %o2
-        ! CHECK: ldda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x9e,0x10,0x76]
+        ! CHECK: ldda [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x9e,0x10,0x76]
         ldda [%i0 + %l6] 131, %o2
 
         ! CHECK: stb %o2, [%i0+%l6]   ! encoding: [0xd4,0x2e,0x00,0x16]
         stb %o2, [%i0 + %l6]
         ! CHECK: stb %o2, [%i0+32]    ! encoding: [0xd4,0x2e,0x20,0x20]
         stb %o2, [%i0 + 32]
         ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x40,0x00]
         stb %o2, [%g1]
         ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x40,0x00]
         stub %o2, [%g1]
         ! CHECK: stb %o2, [%g1]       ! encoding: [0xd4,0x28,0x40,0x00]
         stsb %o2, [%g1]
-        ! CHECK: stba %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xae,0x10,0x76]
+        ! CHECK: stba %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xae,0x10,0x76]
         stba %o2, [%i0 + %l6] 131
-        ! CHECK: stba %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xae,0x10,0x76]
+        ! CHECK: stba %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xae,0x10,0x76]
         stuba %o2, [%i0 + %l6] 131
-        ! CHECK: stba %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xae,0x10,0x76]
+        ! CHECK: stba %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xae,0x10,0x76]
         stsba %o2, [%i0 + %l6] 131
 
         ! CHECK: sth %o2, [%i0+%l6]   ! encoding: [0xd4,0x36,0x00,0x16]
         sth %o2, [%i0 + %l6]
         ! CHECK: sth %o2, [%i0+32]    ! encoding: [0xd4,0x36,0x20,0x20]
         sth %o2, [%i0 + 32]
         ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x40,0x00]
         sth %o2, [%g1]
         ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x40,0x00]
         stuh %o2, [%g1]
         ! CHECK: sth %o2, [%g1]       ! encoding: [0xd4,0x30,0x40,0x00]
         stsh %o2, [%g1]
-        ! CHECK: stha %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xb6,0x10,0x76]
+        ! CHECK: stha %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xb6,0x10,0x76]
         stha %o2, [%i0 + %l6] 131
-        ! CHECK: stha %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xb6,0x10,0x76]
+        ! CHECK: stha %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xb6,0x10,0x76]
         stuha %o2, [%i0 + %l6] 131
-        ! CHECK: stha %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xb6,0x10,0x76]
+        ! CHECK: stha %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xb6,0x10,0x76]
         stsha %o2, [%i0 + %l6] 131
 
         ! CHECK: st %o2, [%i0+%l6]    ! encoding: [0xd4,0x26,0x00,0x16]
         st %o2, [%i0 + %l6]
         ! CHECK: st %o2, [%i0+32]     ! encoding: [0xd4,0x26,0x20,0x20]
         st %o2, [%i0 + 32]
         ! CHECK: st %o2, [%g1]        ! encoding: [0xd4,0x20,0x40,0x00]
         st %o2, [%g1]
-        ! CHECK: sta %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xa6,0x10,0x76]
+        ! CHECK: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
         sta %o2, [%i0 + %l6] 131
 
         ! CHECK: std %o2, [%i0+%l6]    ! encoding: [0xd4,0x3e,0x00,0x16]
         std %o2, [%i0 + %l6]
         ! CHECK: std %o2, [%i0+32]     ! encoding: [0xd4,0x3e,0x20,0x20]
         std %o2, [%i0 + 32]
         ! CHECK: std %o2, [%g1]        ! encoding: [0xd4,0x38,0x40,0x00]
         std %o2, [%g1]
-        ! CHECK: stda %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xbe,0x10,0x76]
+        ! CHECK: stda %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xbe,0x10,0x76]
         stda %o2, [%i0 + %l6] 131
 
         ! CHECK:  flush %g1+%g2         ! encoding: [0x81,0xd8,0x40,0x02]
         flush %g1 + %g2
         ! CHECK:  flush %g1+8           ! encoding: [0x81,0xd8,0x60,0x08]
         flush %g1 + 8
         ! CHECK:  flush %g1             ! encoding: [0x81,0xd8,0x40,0x00]
         flush %g1
         ! Not specified in manual, but accepted by gas.
         ! CHECK:  flush %g0             ! encoding: [0x81,0xd8,0x00,0x00]
         flush
         ! CHECK:  flush %g0             ! encoding: [0x81,0xd8,0x00,0x00]
         iflush

llvm/test/MC/Sparc/sparc-special-registers.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
         wr %i0, 5, %psr
 
         ! CHECK: wr %i0, 5, %wim          ! encoding: [0x81,0x96,0x20,0x05]
         wr %i0, 5, %wim
 
         ! CHECK: wr %i0, 5, %tbr          ! encoding: [0x81,0x9e,0x20,0x05]
         wr %i0, 5, %tbr
 
-        ! CHECK: rd %asr6, %i0         ! encoding: [0xb1,0x41,0x80,0x00]
+        ! CHECK: rd %fprs, %i0         ! encoding: [0xb1,0x41,0x80,0x00]
         rd %fprs, %i0
 
-        ! CHECK: wr %i0, 7, %asr6      ! encoding: [0x8d,0x86,0x20,0x07]
+        ! CHECK: wr %i0, 7, %fprs      ! encoding: [0x8d,0x86,0x20,0x07]
         wr %i0, 7, %fprs
 
         ! CHECK: ld [%g2+20], %fsr     ! encoding: [0xc1,0x08,0xa0,0x14]
         ld [%g2 + 20],%fsr
 
         ! CHECK: ld [%g2+%i5], %fsr    ! encoding: [0xc1,0x08,0x80,0x1d]
         ld [%g2 + %i5],%fsr
 
         ! CHECK: st %fsr, [%g2+20]     ! encoding: [0xc1,0x28,0xa0,0x14]
         st %fsr,[%g2 + 20]
 
         ! CHECK: st %fsr, [%g2+%i5]    ! encoding: [0xc1,0x28,0x80,0x1d]
         st %fsr,[%g2 + %i5]
 
         ! CHECK: std %fq, [%g6+%i2]    ! encoding: [0xc1,0x31,0x80,0x1a]
         std %fq, [%g6 + %i2]

llvm/test/MC/Sparc/sparcv9-atomic-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
         membar #LoadLoad | #StoreStore
 
         ! CHECK: membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync  ! encoding: [0x81,0x43,0xe0,0x7f]
         membar #LoadLoad | #StoreLoad | #LoadStore | #StoreStore | #Lookaside | #MemIssue | #Sync
 
         ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
         cas [%i0], %l6, %o2
 
+        ! CHECK: casl [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x11,0x16]
+        casl [%i0], %l6, %o2
+
+        ! CHECK: casa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
+        casa [%i0] #ASI_P, %l6, %o2
+
+        ! CHECK: casa [%i0] %asi, %l6, %o2   ! encoding: [0xd5,0xe6,0x20,0x16]
+        casa [%i0] %asi, %l6, %o2
+
         ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
         casx [%i0], %l6, %o2
+
+        ! CHECK: casxl [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x11,0x16]
+        casxl [%i0], %l6, %o2
+
+        ! CHECK: casxa [%i0] #ASI_P, %l6, %o2   ! encoding: [0xd5,0xf6,0x10,0x16]
+        casxa [%i0] #ASI_P, %l6, %o2
+
+        ! CHECK: casxa [%i0] %asi, %l6, %o2   ! encoding: [0xd5,0xf6,0x20,0x16]
+        casxa [%i0] %asi, %l6, %o2

llvm/test/MC/Sparc/sparcv9-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V9: ld [%i0+32], %o2     ! encoding: [0xd4,0x06,0x20,0x20]
         lduw [%i0 + 32], %o2
         ! V8:      error: invalid instruction mnemonic
         ! V8-NEXT: lduw [%g1], %o2
         ! V9: ld [%g1], %o2        ! encoding: [0xd4,0x00,0x40,0x00]
         lduw [%g1], %o2
         ! V8:      error: invalid instruction mnemonic
         ! V8-NEXT: lduwa [%i0 + %l6] 131, %o2
-        ! V9: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
+        ! V9: lda [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
         lduwa [%i0 + %l6] 131, %o2
 
+        ! V9: ldsw [%i0+%l6], %o2    ! encoding: [0xd4,0x46,0x00,0x16]
+        ldsw [%i0 + %l6], %o2
+        ! V9: ldsw [%i0+32], %o2     ! encoding: [0xd4,0x46,0x20,0x20]
+        ldsw [%i0 + 32], %o2
+        ! V9: ldsw [%g1], %o2        ! encoding: [0xd4,0x40,0x40,0x00]
+        ldsw [%g1], %o2
+        ! V9: ldswa [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0xc6,0x10,0x76]
+        ldswa [%i0 + %l6] 131, %o2
+
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: lda [%l0] 0xf0, %f29
         ! V9: lda [%l0] 240, %f29             ! encoding: [0xfb,0x84,0x1e,0x00]
         lda [%l0] 0xf0, %f29
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: ldda [%l0] 0xf0, %f48
         ! V9: ldda [%l0] 240, %f48            ! encoding: [0xe3,0x9c,0x1e,0x00]
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V9: ldx [%g2+20], %fsr    ! encoding: [0xc3,0x08,0xa0,0x14]
         ldx [%g2 + 20],%fsr
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: ldx [%g2 + %i5],%fsr
         ! V9: ldx [%g2+%i5], %fsr   ! encoding: [0xc3,0x08,0x80,0x1d]
         ldx [%g2 + %i5],%fsr
 
+        ! V9: ldxa [%g2+%i5] #ASI_SNF, %g0   ! encoding: [0xc0,0xd8,0x90,0x7d]
+        ldxa [%g2 + %i5] 131, %g0
+
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: stx %fsr,[%g2 + 20]
         ! V9: stx %fsr, [%g2+20]    ! encoding: [0xc3,0x28,0xa0,0x14]
         stx %fsr,[%g2 + 20]
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: stx %fsr,[%g2 + %i5]
         ! V9: stx %fsr, [%g2+%i5]   ! encoding: [0xc3,0x28,0x80,0x1d]
         stx %fsr,[%g2 + %i5]
 
+        ! V9: stxa %g0, [%g2+%i5] #ASI_SNF   ! encoding: [0xc0,0xf0,0x90,0x7d]
+        stxa %g0, [%g2 + %i5] 131
+
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: wrpr %g6,%i6,%tpc
         ! V9: wrpr %g6, %fp, %tpc        ! encoding: [0x81,0x91,0x80,0x1e]
         wrpr %g6,%i6,%tpc
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: wrpr %g6,%i6,%tnpc
         ! V9: wrpr %g6, %fp, %tnpc       ! encoding: [0x83,0x91,0x80,0x1e]
         wrpr %g6,%i6,%tnpc
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %otherwin,%i5
         ! V9: rdpr %otherwin, %i5       ! encoding: [0xbb,0x53,0x40,0x00]
         rdpr %otherwin,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %wstate,%i5
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
-
         ! V8:      error: instruction requires a CPU feature not currently enabled
-        ! V8-NEXT: rd %pc, %o7
+        ! V8-NEXT: rdpr %fq,%i5
+        ! V9: rdpr %fq, %i5             ! encoding: [0xbb,0x53,0xc0,0x00]
+        rdpr %fq,%i5
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rdpr %ver,%i5
+        ! V9: rdpr %ver, %i5            ! encoding: [0xbb,0x57,0xc0,0x00]
+        rdpr %ver,%i5
+
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
+        rd %asi, %g1
+        ! V9: rd %ccr, %g1              ! encoding: [0x83,0x40,0x80,0x00]
+        rd %ccr, %g1
+        ! V9: rd %tick, %i5             ! encoding: [0xbb,0x41,0x00,0x00]
+        rd %tick,%i5
+
+        ! V9: wr %i0, %i1, %asi         ! encoding: [0x87,0x86,0x00,0x19]
+        wr %i0, %i1, %asi
+        ! V9: wr %i0, 1, %asi           ! encoding: [0x87,0x86,0x20,0x01]
+        wr %i0, 1, %asi
+        ! V9: wr %i0, %i1, %ccr         ! encoding: [0x85,0x86,0x00,0x19]
+        wr %i0, %i1, %ccr
+        ! V9: wr %i0, 1, %ccr           ! encoding: [0x85,0x86,0x20,0x01]
+        wr %i0, 1, %ccr
 
         ! V9: st %o1, [%o0]             ! encoding: [0xd2,0x22,0x00,0x00]
         stw %o1, [%o0]
+        ! V9: st %o1, [%o0]             ! encoding: [0xd2,0x22,0x00,0x00]
+        stuw %o1, [%o0]
+        ! V9: st %o1, [%o0]             ! encoding: [0xd2,0x22,0x00,0x00]
+        stsw %o1, [%o0]
+
+        ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
+        stwa %o2, [%i0 + %l6] 131
+        ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
+        stuwa %o2, [%i0 + %l6] 131
+        ! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
+        stswa %o2, [%i0 + %l6] 131
+
+        !! SPARCv9 provides a new variant of ASI-tagged memory accesses.
+        ! V9: ldxa [%g2] %asi, %g0    ! encoding: [0xc0,0xd8,0xa0,0x00]
+        ldxa [%g2] %asi, %g0
+        ! V9: stxa %g0, [%g2] %asi    ! encoding: [0xc0,0xf0,0xa0,0x00]
+        stxa %g0, [%g2] %asi
+        ! V9: ldxa [%g2+5] %asi, %g0    ! encoding: [0xc0,0xd8,0xa0,0x05]
+        ldxa [%g2 + 5] %asi, %g0
+        ! V9: stxa %g0, [%g2+5] %asi    ! encoding: [0xc0,0xf0,0xa0,0x05]
+        stxa %g0, [%g2 + 5] %asi
+
+        !! Also make sure named ASI tags are parsed properly.
+        ! V9: ldxa [%g2+%i5] #ASI_SNF, %g0   ! encoding: [0xc0,0xd8,0x90,0x7d]
+        ldxa [%g2 + %i5] #ASI_SNF, %g0
+        ! V9: stxa %g0, [%g2+%i5] #ASI_SNF   ! encoding: [0xc0,0xf0,0x90,0x7d]
+        stxa %g0, [%g2 + %i5] #ASI_SNF
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: prefetch  [ %i1 + 0xf80 ], 1
         ! V9: prefetch  [%i1+3968], 1  ! encoding: [0xc3,0x6e,0x6f,0x80]
         prefetch  [ %i1 + 0xf80 ], 1
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: prefetch  [ %i1 + %i2 ], 1
         ! V9: prefetch  [%i1+%i2], 1  ! encoding: [0xc3,0x6e,0x40,0x1a]
         prefetch  [ %i1 + %i2 ], 1
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: done
+        ! V9: done      ! encoding: [0x81,0xf0,0x00,0x00]
+        done
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: retry
+        ! V9: retry     ! encoding: [0x83,0xf0,0x00,0x00]
+        retry
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: saved
+        ! V9: saved     ! encoding: [0x81,0x88,0x00,0x00]
+        saved
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: restored
+        ! V9: restored  ! encoding: [0x83,0x88,0x00,0x00]
+        restored

llvm/test/MC/Sparc/sparcv9-synthetic-instructions.s

+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+
+        ! V9: mov -1, %o1                     ! encoding: [0x92,0x10,0x3f,0xff]
+        setx -1, %g1, %o1
+
+        ! V9: sethi %hi(-1), %o1              ! encoding: [0x13,0b00AAAAAA,A,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %hi(-1), kind: fixup_sparc_hi22
+        ! V9: or %o1, %lo(-1), %o1            ! encoding: [0x92,0x12,0b011000AA,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %lo(-1), kind: fixup_sparc_lo10
+        setx 0xffffffff, %g1, %o1
+
+        ! V9: sethi %hh(81985529216486895), %g1       ! encoding: [0x03,0b00AAAAAA,A,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %hh(81985529216486895), kind: fixup_sparc_hh
+        ! V9: sethi %hi(81985529216486895), %o0       ! encoding: [0x11,0b00AAAAAA,A,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %hi(81985529216486895), kind: fixup_sparc_hi22
+        ! V9: or %g1, %hm(81985529216486895), %g1     ! encoding: [0x82,0x10,0b011000AA,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %hm(81985529216486895), kind: fixup_sparc_hm
+        ! V9: or %o0, %lo(81985529216486895), %o0     ! encoding: [0x90,0x12,0b001000AA,A]
+        ! V9:                                 !   fixup A - offset: 0, value: %lo(81985529216486895), kind: fixup_sparc_lo10
+        ! V9: sllx %g1, 32, %g1                       ! encoding: [0x83,0x28,0x70,0x20]
+        ! V9: or %g1, %o0, %o0                        ! encoding: [0x90,0x10,0x40,0x08]
+        setx 0x0123456789abcdef, %g1, %o0