[SPARC][MC] Fix encoding of backwards BPr branches

[koakuma]

Summary

Make sure that the upper bits of the offset is placed in bits 20-21 of the instruction word.
This fixes the encoding of backwards (negative offset) BPr branches.

(Previously, the upper two bits of the offset would overwrite parts of the rs1 field, causing it to branch on the wrong register, with the wrong offset)

[koakuma]

Ping?

[jrtc27]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

43–44

This doesn't make sense to me. Shouldn't it be (Value >> 16) & 0x3? The fixup tables are correctly specifying the 2 bits for BE and LE.

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

67

Isn't this going to create two relocations rather than one? Really there should be a single fixup for the whole thing.

[koakuma]

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

67

Yeah, I tried to merge the _14 and the _2 parts, but the MCFixupKindInfo table does not support split bits.
One thing that I can think of is to just emit the real ELF relocation with the _14 internal type and emit a R_SPARC_NONE instead with the _2 internal type but I'm not really sure if this is okay?

[koakuma]

• Fix calculation for fixup_sparc_br16_2.
• Make sure to properly shift fixup values as described in the fixup tables.
• Only emit one R_SPARC_WDISP16 relocation per one fixup_sparc_br16_14/2 pair.

[koakuma]

Remove stray include statement.

[koakuma]

Ping?

[jrtc27]

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

72

This is pretty gross, and wastes space in the result. Please just have a single fixup.

[koakuma]

Merge fixup_sparc_br16_2/fixup_sparc_br16_14 into a single fixup.

[brad]

@jrtc27 Ping?

[jrtc27]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

50

This looks good now

209

Could you please commit this reformatting separately? Combining significant reformatting with functional changes isn't great.

353

This seems unrelated?

llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h

15–111

If you're going to reformat this, deindent the namespace too to match every other target, and commit it all separately from the functional change.

llvm/test/MC/Sparc/sparc64-bpr-offset.s

4

for should be from or to

[koakuma]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

209

Okay, will remove the formatting changes from this patch.

353

I put this because I noticed that the offset/size values from the table is not used at all, so the upper part of the fixup bits aren't placed properly.
(This happens on the old version of the patch with split fixup_sparc_br16_2/fixup_sparc_br16_14, at least)

It's basically just adding what other architectures already do (but for some reason hasn't been done here in the SPARC backend)... should I submit this separately?

[koakuma]

Undo formatting changes and fix typo in test comment.

[brad]

@jrtc27 Ping?

[koakuma]

Ping?

[brad]

@jrtc27 Ping?

[brad]

@jrtc27 Ping?

[brad]

@arsenm Ping.

[arsenm]

Don't know anything about sparc but code seems fine

[vitalybuka]

https://lab.llvm.org/buildbot/#/builders/85/builds/15963

FAIL: LLVM :: DebugInfo/Sparc/gnu-window-save.ll (44906 of 74125)
******************** TEST 'LLVM :: DebugInfo/Sparc/gnu-window-save.ll' FAILED ********************
Script:
--
: 'RUN: at line 1';   /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/llc -filetype=obj -O0 < /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/test/DebugInfo/Sparc/gnu-window-save.ll -mtriple sparc64-unknown-linux-gnu | /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/llvm-dwarfdump -v - | /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/test/DebugInfo/Sparc/gnu-window-save.ll --check-prefix=SPARC64
: 'RUN: at line 2';   /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/llc -filetype=obj -O0 < /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/test/DebugInfo/Sparc/gnu-window-save.ll -mtriple sparc-unknown-linux-gnu   | /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/llvm-dwarfdump -v - | /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/FileCheck /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/test/DebugInfo/Sparc/gnu-window-save.ll --check-prefix=SPARC32
--
Exit Code: 2
Command Output (stderr):
--
/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp:357:15: runtime error: shift exponent 4294967264 is too large for 64-bit type 'uint64_t' (aka 'unsigned long')
    #0 0x562868ff62ff in (anonymous namespace)::ELFSparcAsmBackend::applyFixup(llvm::MCAssembler const&, llvm::MCFixup const&, llvm::MCValue const&, llvm::MutableArrayRef<char>, unsigned long, bool, llvm::MCSubtargetInfo const*) const /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
    #1 0x562869ff521f in llvm::MCAssembler::layout(llvm::MCAsmLayout&) /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/MC/MCAssembler.cpp:928:22
    #2 0x562869ff5f2d in llvm::MCAssembler::Finish() /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/MC/MCAssembler.cpp:938:3
    #3 0x56286a02453e in llvm::MCELFStreamer::finishImpl() /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/MC/MCELFStreamer.cpp:718:27
    #4 0x5628694200a5 in llvm::AsmPrinter::doFinalization(llvm::Module&) /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:2397:16
    #5 0x562869efba12 in llvm::FPPassManager::doFinalization(llvm::Module&) /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1499:41
    #6 0x562869ef1c8a in runOnModule /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1586:41
    #7 0x562869ef1c8a in llvm::legacy::PassManagerImpl::run(llvm::Module&) /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:44
    #8 0x5628672cf06c in compileModule(char**, llvm::LLVMContext&) /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/tools/llc/llc.cpp:756:8
    #9 0x5628672cc89b in main /b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm-project/llvm/tools/llc/llc.cpp:420:22
    #10 0x7fafb5c2350f  (/lib/x86_64-linux-gnu/libc.so.6+0x2350f) (BuildId: d1704d25fbbb72fa95d517b883131828c0883fe9)
    #11 0x7fafb5c235c8 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x235c8) (BuildId: d1704d25fbbb72fa95d517b883131828c0883fe9)
    #12 0x5628672a02e4 in _start (/b/sanitizer-x86_64-linux-bootstrap-ubsan/build/llvm_build_ubsan/bin/llc+0x5d892e4)

[koakuma]

Remove the offset shift calculation. We already took care of proper placement of BPr offset value through other means, so this is not needed anymore.

This should also takes care of the sanitizer errors.

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   case Sparc::fixup_sparc_call30:
     return (Value >> 2) & 0x3fffffff;
 
   case Sparc::fixup_sparc_br22:
     return (Value >> 2) & 0x3fffff;
 
   case Sparc::fixup_sparc_br19:
     return (Value >> 2) & 0x7ffff;
 
-  case Sparc::fixup_sparc_br16_2:
-    return (Value >> 2) & 0xc000;
-
-  case Sparc::fixup_sparc_br16_14:
-    return (Value >> 2) & 0x3fff;
+  case Sparc::fixup_sparc_br16: {
+    // A.3 Branch on Integer Register with Prediction (BPr)
+    // Inst{21-20} = d16hi;
+    // Inst{13-0}  = d16lo;
+    unsigned d16hi = (Value >> 16) & 0x3;
+    unsigned d16lo = (Value >> 2) & 0x3fff;
+    return (d16hi << 20) | d16lo;
+  }
 
   case Sparc::fixup_sparc_hix22:
     return (~Value >> 10) & 0x3fffff;
 
   case Sparc::fixup_sparc_pc22:
   case Sparc::fixup_sparc_got22:
   case Sparc::fixup_sparc_tls_gd_hi22:
   case Sparc::fixup_sparc_tls_ldm_hi22:
#undef ELF_RELOC
     }
 
     const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
       const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_sparc_br16",       0,     32,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",        19,     13,  0 },
         { "fixup_sparc_hi22",      10,     22,  0 },
         { "fixup_sparc_lo10",      22,     10,  0 },
         { "fixup_sparc_h44",       10,     22,  0 },
         { "fixup_sparc_m44",       22,     10,  0 },
         { "fixup_sparc_l44",       20,     12,  0 },
         { "fixup_sparc_hh",        10,     22,  0 },
         { "fixup_sparc_hm",        22,     10,  0 },
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
         { "fixup_sparc_tls_ie_add",     0,  0,  0 },
         { "fixup_sparc_tls_le_hix22",   0,  0,  0 },
         { "fixup_sparc_tls_le_lox10",   0,  0,  0 },
         { "fixup_sparc_hix22",         10, 22,  0 },
         { "fixup_sparc_lox10",         19, 13,  0 },
         { "fixup_sparc_gotdata_hix22",  0,  0,  0 },
         { "fixup_sparc_gotdata_lox10",  0,  0,  0 },
         { "fixup_sparc_gotdata_op",     0,  0,  0 },
       };
 
       const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16_2",    20,      2,  MCFixupKindInfo::FKF_IsPCRel },
-        { "fixup_sparc_br16_14",    0,     14,  MCFixupKindInfo::FKF_IsPCRel },
+        { "fixup_sparc_br16",      32,      0,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",         0,     13,  0 },
         { "fixup_sparc_hi22",       0,     22,  0 },
         { "fixup_sparc_lo10",       0,     10,  0 },
         { "fixup_sparc_h44",        0,     22,  0 },
         { "fixup_sparc_m44",        0,     10,  0 },
         { "fixup_sparc_l44",        0,     12,  0 },
         { "fixup_sparc_hh",         0,     22,  0 },
         { "fixup_sparc_hm",         0,     10,  0 },
public:
 
     void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                     const MCValue &Target, MutableArrayRef<char> Data,
                     uint64_t Value, bool IsResolved,
                     const MCSubtargetInfo *STI) const override {
 
       if (Fixup.getKind() >= FirstLiteralRelocationKind)
         return;
+      MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
       Value = adjustFixupValue(Fixup.getKind(), Value);
       if (!Value) return;           // Doesn't change encoding.
 
+      // Shift the value into position.
+      if (Endian == support::little)
+        Value <<= Info.TargetOffset;
+      else
+        Value <<= 32 - Info.TargetOffset - Info.TargetSize;
+
       unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
       unsigned Offset = Fixup.getOffset();
       // For each byte of the fragment that the fixup touches, mask in the bits
       // from the fixup value. The Value has been "split up" into the
       // appropriate bitfields above.
       for (unsigned i = 0; i != NumBytes; ++i) {
         unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
         Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

default:
       llvm_unreachable("Unimplemented fixup -> relocation");
     case FK_Data_1:                  return ELF::R_SPARC_DISP8;
     case FK_Data_2:                  return ELF::R_SPARC_DISP16;
     case FK_Data_4:                  return ELF::R_SPARC_DISP32;
     case FK_Data_8:                  return ELF::R_SPARC_DISP64;
     case Sparc::fixup_sparc_call30:  return ELF::R_SPARC_WDISP30;
     case Sparc::fixup_sparc_br22:    return ELF::R_SPARC_WDISP22;
     case Sparc::fixup_sparc_br19:    return ELF::R_SPARC_WDISP19;
+    case Sparc::fixup_sparc_br16:
+      return ELF::R_SPARC_WDISP16;
     case Sparc::fixup_sparc_pc22:    return ELF::R_SPARC_PC22;
     case Sparc::fixup_sparc_pc10:    return ELF::R_SPARC_PC10;
     case Sparc::fixup_sparc_wplt30:  return ELF::R_SPARC_WPLT30;
     }
   }
 
   switch(Fixup.getTargetKind()) {
   default:
     llvm_unreachable("Unimplemented fixup -> relocation");
   case FK_NONE:                  return ELF::R_SPARC_NONE;
   case FK_Data_1:                return ELF::R_SPARC_8;
   case FK_Data_2:                return ((Fixup.getOffset() % 2)
                                          ? ELF::R_SPARC_UA16
                                          : ELF::R_SPARC_16);

llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h

 //===-- SparcFixupKinds.h - Sparc Specific Fixup Entries --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H
 
 #include "llvm/MC/MCFixup.h"
 
 namespace llvm {
   namespace Sparc {
     enum Fixups {
       // fixup_sparc_call30 - 30-bit PC relative relocation for call
       fixup_sparc_call30 = FirstTargetFixupKind,
 
       /// fixup_sparc_br22 - 22-bit PC relative relocation for
       /// branches
       fixup_sparc_br22,
 
       /// fixup_sparc_br19 - 19-bit PC relative relocation for
       /// branches on icc/xcc
       fixup_sparc_br19,
 
       /// fixup_sparc_bpr  - 16-bit fixup for bpr
-      fixup_sparc_br16_2,
-      fixup_sparc_br16_14,
+      fixup_sparc_br16,
 
       /// fixup_sparc_13 - 13-bit fixup
       fixup_sparc_13,
 
       /// fixup_sparc_hi22  - 22-bit fixup corresponding to %hi(foo)
       /// for sethi
       fixup_sparc_hi22,
 
       /// fixup_sparc_lo10  - 10-bit fixup corresponding to %lo(foo)
       fixup_sparc_lo10,
 
       /// fixup_sparc_h44  - 22-bit fixup corresponding to %h44(foo)
       fixup_sparc_h44,
 
       /// fixup_sparc_m44  - 10-bit fixup corresponding to %m44(foo)
       fixup_sparc_m44,
 
       /// fixup_sparc_l44  - 12-bit fixup corresponding to %l44(foo)
       fixup_sparc_l44,
 
       /// fixup_sparc_hh  -  22-bit fixup corresponding to %hh(foo)
       fixup_sparc_hh,
 
       /// fixup_sparc_hm  -  10-bit fixup corresponding to %hm(foo)
       fixup_sparc_hm,
 
       /// fixup_sparc_lm  -  22-bit fixup corresponding to %lm(foo)
       fixup_sparc_lm,
 
       /// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo)
       fixup_sparc_pc22,
 
       /// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo)
       fixup_sparc_pc10,
 
       /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo)
       fixup_sparc_got22,
 
       /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo)
       fixup_sparc_got10,
 
       /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo)
       fixup_sparc_got13,
 
       /// fixup_sparc_wplt30
       fixup_sparc_wplt30,
 
       /// fixups for Thread Local Storage
       fixup_sparc_tls_gd_hi22,
       fixup_sparc_tls_gd_lo10,
       fixup_sparc_tls_gd_add,
       fixup_sparc_tls_gd_call,
       fixup_sparc_tls_ldm_hi22,
       fixup_sparc_tls_ldm_lo10,
       fixup_sparc_tls_ldm_add,
       fixup_sparc_tls_ldm_call,
       fixup_sparc_tls_ldo_hix22,
       fixup_sparc_tls_ldo_lox10,
       fixup_sparc_tls_ldo_add,
       fixup_sparc_tls_ie_hi22,
       fixup_sparc_tls_ie_lo10,
       fixup_sparc_tls_ie_ld,
       fixup_sparc_tls_ie_ldx,
       fixup_sparc_tls_ie_add,
       fixup_sparc_tls_le_hix22,
       fixup_sparc_tls_le_lox10,
 
       /// 22-bit fixup corresponding to %hix(foo)
       fixup_sparc_hix22,
       /// 13-bit fixup corresponding to %lox(foo)
       fixup_sparc_lox10,
 
       /// 22-bit fixup corresponding to %gdop_hix22(foo)
       fixup_sparc_gotdata_hix22,
       /// 13-bit fixup corresponding to %gdop_lox10(foo)
       fixup_sparc_gotdata_lox10,
       /// 32-bit fixup corresponding to %gdop(foo)
       fixup_sparc_gotdata_op,
 
       // Marker
       LastTargetFixupKind,
       NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
     };
   }
 }
 
 #endif

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

 unsigned SparcMCCodeEmitter::
 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
   if (MO.isReg() || MO.isImm())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   (MCFixupKind)Sparc::fixup_sparc_br16_2));
-  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
-                                   (MCFixupKind)Sparc::fixup_sparc_br16_14));
+  Fixups.push_back(
+      MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16));
 
   return 0;
 }
 
 #include "SparcGenMCCodeEmitter.inc"
 
 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
                                               MCContext &Ctx) {
   return new SparcMCCodeEmitter(MCII, Ctx);
 }

llvm/test/MC/Sparc/sparc64-bpr-offset.s

+! RUN: llvm-mc -arch=sparcv9 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=BIN
+
+        !! SPARCv9/SPARC64 BPr branches have different offset encoding from the others,
+        !! make sure that our offset bits don't trample on other fields.
+        !! This is particularly important with backwards branches.
+
+        ! BIN:  0: 02 c8 40 01    brz %g1, 1
+        ! BIN:  4: 04 c8 40 01    brlez %g1, 1
+        ! BIN:  8: 06 c8 40 01    brlz %g1, 1
+        ! BIN:  c: 0a c8 40 01    brnz %g1, 1
+        ! BIN: 10: 0c c8 40 01    brgz %g1, 1
+        ! BIN: 14: 0e c8 40 01    brgez %g1, 1
+        brz   %g1, .+4
+        brlez %g1, .+4
+        brlz  %g1, .+4
+        brnz  %g1, .+4
+        brgz  %g1, .+4
+        brgez %g1, .+4
+
+        ! BIN: 18: 02 f8 7f ff    brz %g1, 65535
+        ! BIN: 1c: 04 f8 7f ff    brlez %g1, 65535
+        ! BIN: 20: 06 f8 7f ff    brlz %g1, 65535
+        ! BIN: 24: 0a f8 7f ff    brnz %g1, 65535
+        ! BIN: 28: 0c f8 7f ff    brgz %g1, 65535
+        ! BIN: 2c: 0e f8 7f ff    brgez %g1, 65535
+        brz   %g1, .-4
+        brlez %g1, .-4
+        brlz  %g1, .-4
+        brnz  %g1, .-4
+        brgz  %g1, .-4
+        brgez %g1, .-4

llvm/test/MC/Sparc/sparc64-ctrl-instructions.s

         ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
         fbue,pn %fcc3, .BB0
 
         ! CHECK:             fbne,a,pn %fcc3, .BB0           ! encoding: [0x23,0b01110AAA,A,A]
         ! CHECK-NEXT:                                        !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19
         fbne,a,pn %fcc3, .BB0
 
 
-        ! CHECK:                brz %g1, .BB0                   ! encoding: [0x02,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
-        ! CHECK:                brlez %g1, .BB0                 ! encoding: [0x04,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
-        ! CHECK:                brlz %g1, .BB0                  ! encoding: [0x06,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
-        ! CHECK:                brnz %g1, .BB0                  ! encoding: [0x0a,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !  fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
-        ! CHECK:                brgz %g1, .BB0                  ! encoding: [0x0c,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
-        ! CHECK:                brgez %g1, .BB0                 ! encoding: [0x0e,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                                           !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK:                brz %g1, .BB0                   ! encoding: [0x02'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
+        ! CHECK:                brlez %g1, .BB0                 ! encoding: [0x04'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
+        ! CHECK:                brlz %g1, .BB0                  ! encoding: [0x06'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
+        ! CHECK:                brnz %g1, .BB0                  ! encoding: [0x0a'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
+        ! CHECK:                brgz %g1, .BB0                  ! encoding: [0x0c'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
+        ! CHECK:                brgez %g1, .BB0                 ! encoding: [0x0e'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                                           !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
 
         brz   %g1, .BB0
         brlez %g1, .BB0
         brlz  %g1, .BB0
         brnz  %g1, .BB0
         brgz  %g1, .BB0
         brgez %g1, .BB0
 
-        ! CHECK: brz %g1, .BB0                   ! encoding: [0x02,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                            !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK: brz %g1, .BB0                   ! encoding: [0x02'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
         brz,pt   %g1, .BB0
 
-        ! CHECK: brz,a %g1, .BB0                 ! encoding: [0x22,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                            !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK: brz,a %g1, .BB0                 ! encoding: [0x22'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
         brz,a   %g1, .BB0
 
-        ! CHECK: brz,a %g1, .BB0                 ! encoding: [0x22,0b11AA1000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                            !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK: brz,a %g1, .BB0                 ! encoding: [0x22'A',0xc8'A',0x40'A',A]
+        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
         brz,a,pt   %g1, .BB0
 
-        ! CHECK:  brz,pn %g1, .BB0               ! encoding: [0x02,0b11AA0000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                            !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK:  brz,pn %g1, .BB0               ! encoding: [0x02'A',0xc0'A',0x40'A',A]
+        ! CHECK-NEXT:                            !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
         brz,pn   %g1, .BB0
 
-        ! CHECK:  brz,a,pn %g1, .BB0              ! encoding: [0x22,0b11AA0000,0b01BBBBBB,B]
-        ! CHECK-NEXT:                             !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16_2
-        ! CHECK-NEXT:                             !   fixup B - offset: 0, value: .BB0, kind: fixup_sparc_br16_14
+        ! CHECK:  brz,a,pn %g1, .BB0              ! encoding: [0x22'A',0xc0'A',0x40'A',A]
+        ! CHECK-NEXT:                             !   fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br16
         brz,a,pn   %g1, .BB0
 
         ! CHECK: movrz   %g1, %g2, %g3 ! encoding: [0x87,0x78,0x44,0x02]
         ! CHECK: movrlez %g1, %g2, %g3 ! encoding: [0x87,0x78,0x48,0x02]
         ! CHECK: movrlz  %g1, %g2, %g3 ! encoding: [0x87,0x78,0x4c,0x02]
         ! CHECK: movrnz  %g1, %g2, %g3 ! encoding: [0x87,0x78,0x54,0x02]
         ! CHECK: movrgz  %g1, %g2, %g3 ! encoding: [0x87,0x78,0x58,0x02]
         ! CHECK: movrgez %g1, %g2, %g3 ! encoding: [0x87,0x78,0x5c,0x02]