[SPARC] Implement hooks for conditional branch relaxation

[koakuma]

Summary

Integrate the BranchRelaxation pass to help with relaxing out-of-range conditional branches.

This is mostly of concern for SPARCv9, which uses conditional branches with much smaller range than its v8 counterparts.
(Some large autogenerated code, such as the ones generated by TableGen, already hits this limitation when building in Release)

[koakuma]

Ping?

[arsenm]

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

600

MI.isInlineAsm()

[koakuma]

• Use MI.isInlineAsm() as suggested
• Clean up unnecessary changes

[jrtc27]

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

321

These are all double what I'd expect?

[koakuma]

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

321

Yes, I'm also including the delay slots here, like in getInstSizeInBytes.

[brad]

@jrtc27 ?

[koakuma]

Ping?

[arsenm]

llvm/lib/Target/Sparc/SparcTargetMachine.cpp

193

Don't check the global subtarget, just unconditionally enable the pass

[koakuma]

Update as suggested, remove the conditional on target.

[koakuma]

Update update_llc_test_checks testcases.

[koakuma]

Ping?

[brad]

@arsenm Ping?

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
   int CC = (int)MI->getOperand(opNum).getImm();
   switch (MI->getOpcode()) {
   default: break;
   case SP::FBCOND:
   case SP::FBCONDA:
+  case SP::FBCOND_V9:
+  case SP::FBCONDA_V9:
   case SP::BPFCC:
   case SP::BPFCCA:
   case SP::BPFCCNT:
   case SP::BPFCCANT:
   case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
   case SP::MOVFCCri:  case SP::V9MOVFCCri:
   case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
   case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:

llvm/lib/Target/Sparc/SparcInstrInfo.h

public:
   /// isStoreToStackSlot - If the specified machine instruction is a direct
   /// store to a stack slot, return the virtual or physical register number of
   /// the source reg along with the FrameIndex of the loaded stack slot.  If
   /// not, return 0.  This predicate must return 0 if the instruction has
   /// any side effects other than storing to the stack slot.
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
+  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
+
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
                      bool AllowModify = false) const override;
 
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
+  /// Determine if the branch target is in range.
+  bool isBranchOffsetInRange(unsigned BranchOpc, int64_t Offset) const override;
+
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
                    bool KillSrc) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI,
                            Register VReg) const override;
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI, Register DestReg,
                             int FrameIndex, const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI,
                             Register VReg) const override;
 
   Register getGlobalBaseReg(MachineFunction *MF) const;
 
+  /// GetInstSize - Return the number of bytes of code the specified
+  /// instruction may be.  This returns the maximum number of bytes.
+  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
+
   // Lower pseudo instructions after register allocation.
   bool expandPostRAPseudo(MachineInstr &MI) const override;
 };
 
 }
 
 #endif

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "SparcGenInstrInfo.inc"
 
+static cl::opt<unsigned> BPccDisplacementBits(
+    "sparc-bpcc-offset-bits", cl::Hidden, cl::init(19),
+    cl::desc("Restrict range of BPcc/FBPfcc instructions (DEBUG)"));
+
 // Pin the vtable to this file.
 void SparcInstrInfo::anchor() {}
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
     : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
       Subtarget(ST) {}
 
 /// isLoadFromStackSlot - If the specified machine instruction is a direct
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
         MI.getOperand(1).getImm() == 0) {
       FrameIndex = MI.getOperand(0).getIndex();
       return MI.getOperand(2).getReg();
     }
   }
   return 0;
 }
 
-static bool IsIntegerCC(unsigned CC)
-{
-  return  (CC <= SPCC::ICC_VC);
-}
-
 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
 {
   switch(CC) {
   case SPCC::ICC_A:    return SPCC::ICC_N;
   case SPCC::ICC_N:    return SPCC::ICC_A;
   case SPCC::ICC_NE:   return SPCC::ICC_E;
   case SPCC::ICC_E:    return SPCC::ICC_NE;
   case SPCC::ICC_G:    return SPCC::ICC_LE;
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
   case SPCC::REG_GZ:
       return SPCC::REG_LEZ;
   case SPCC::REG_GEZ:
       return SPCC::REG_LZ;
   }
   llvm_unreachable("Invalid cond code");
 }
 
-static bool isUncondBranchOpcode(int Opc) {
-  return Opc == SP::BA || Opc == SP::BPA;
-}
+static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
 
 static bool isI32CondBranchOpcode(int Opc) {
   return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA ||
          Opc == SP::BPICCNT || Opc == SP::BPICCANT;
 }
 
 static bool isI64CondBranchOpcode(int Opc) {
   return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT ||
          Opc == SP::BPXCCANT;
 }
 
-static bool isFCondBranchOpcode(int Opc) { return Opc == SP::FBCOND; }
+static bool isFCondBranchOpcode(int Opc) {
+  return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 ||
+         Opc == SP::FBCONDA_V9;
+}
 
 static bool isCondBranchOpcode(int Opc) {
   return isI32CondBranchOpcode(Opc) || isI64CondBranchOpcode(Opc) ||
          isFCondBranchOpcode(Opc);
 }
 
 static bool isIndirectBranchOpcode(int Opc) {
   return Opc == SP::BINDrr || Opc == SP::BINDri;
 }
 
 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
                             SmallVectorImpl<MachineOperand> &Cond) {
   unsigned Opc = LastInst->getOpcode();
   int64_t CC = LastInst->getOperand(1).getImm();
 
   // Push the branch opcode into Cond too so later in insertBranch
   // it can use the information to emit the correct SPARC branch opcode.
   Cond.push_back(MachineOperand::CreateImm(Opc));
   Cond.push_back(MachineOperand::CreateImm(CC));
 
   Target = LastInst->getOperand(0).getMBB();
 }
 
+MachineBasicBlock *
+SparcInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  default:
+      llvm_unreachable("unexpected opcode!");
+  case SP::BA:
+  case SP::BCOND:
+  case SP::BCONDA:
+  case SP::FBCOND:
+  case SP::FBCONDA:
+  case SP::BPICC:
+  case SP::BPICCA:
+  case SP::BPICCNT:
+  case SP::BPICCANT:
+  case SP::BPXCC:
+  case SP::BPXCCA:
+  case SP::BPXCCNT:
+  case SP::BPXCCANT:
+  case SP::BPFCC:
+  case SP::BPFCCA:
+  case SP::BPFCCNT:
+  case SP::BPFCCANT:
+  case SP::FBCOND_V9:
+  case SP::FBCONDA_V9:
+      return MI.getOperand(0).getMBB();
+  }
+}
+
 bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                    MachineBasicBlock *&TBB,
                                    MachineBasicBlock *&FBB,
                                    SmallVectorImpl<MachineOperand> &Cond,
                                    bool AllowModify) const {
   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
   if (I == MBB.end())
     return false;
unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
                                       MachineBasicBlock *TBB,
                                       MachineBasicBlock *FBB,
                                       ArrayRef<MachineOperand> Cond,
                                       const DebugLoc &DL,
                                       int *BytesAdded) const {
   assert(TBB && "insertBranch must not be told to insert a fallthrough");
   assert((Cond.size() <= 2) &&
          "Sparc branch conditions should have at most two components!");
-  assert(!BytesAdded && "code size not handled");
 
   if (Cond.empty()) {
     assert(!FBB && "Unconditional branch with multiple successors!");
-    BuildMI(&MBB, DL, get(Subtarget.isV9() ? SP::BPA : SP::BA)).addMBB(TBB);
+    BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
+    if (BytesAdded)
+      *BytesAdded = 8;
     return 1;
   }
 
   // Conditional branch
   unsigned Opc = Cond[0].getImm();
   unsigned CC = Cond[1].getImm();
-
-  if (IsIntegerCC(CC)) {
-    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
-  } else {
-    BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
-  }
-  if (!FBB)
+
+  if (!FBB) {
+    if (BytesAdded)
+      *BytesAdded = 8;
     return 1;
+  }
 
-  BuildMI(&MBB, DL, get(Subtarget.isV9() ? SP::BPA : SP::BA)).addMBB(FBB);
+  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
+  if (BytesAdded)
+    *BytesAdded = 16;
   return 2;
 }
 
 unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                       int *BytesRemoved) const {
-  assert(!BytesRemoved && "code size not handled");
-
   MachineBasicBlock::iterator I = MBB.end();
   unsigned Count = 0;
+  int Removed = 0;
   while (I != MBB.begin()) {
     --I;
 
     if (I->isDebugInstr())
       continue;
 
     if (!isCondBranchOpcode(I->getOpcode()) &&
         !isUncondBranchOpcode(I->getOpcode()))
       break; // Not a branch
 
     I->eraseFromParent();
+    Removed += getInstSizeInBytes(*I);
     I = MBB.end();
     ++Count;
   }
+
+  if (BytesRemoved)
+    *BytesRemoved = Removed;
   return Count;
 }
 
 bool SparcInstrInfo::reverseBranchCondition(
     SmallVectorImpl<MachineOperand> &Cond) const {
   assert(Cond.size() <= 2);
   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
   Cond[1].setImm(GetOppositeBranchCondition(CC));
   return false;
 }
 
+bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
+                                           int64_t Offset) const {
+  assert((Offset & 0b11) == 0 && "Malformed branch offset");
+  switch (BranchOpc) {
+  case SP::BA:
+  case SP::BCOND:
+  case SP::BCONDA:
+  case SP::FBCOND:
+  case SP::FBCONDA:
+    return isIntN(22, Offset >> 2);
+
+  case SP::BPICC:
+  case SP::BPICCA:
+  case SP::BPICCNT:
+  case SP::BPICCANT:
+  case SP::BPXCC:
+  case SP::BPXCCA:
+  case SP::BPXCCNT:
+  case SP::BPXCCANT:
+  case SP::BPFCC:
+  case SP::BPFCCA:
+  case SP::BPFCCNT:
+  case SP::BPFCCANT:
+  case SP::FBCOND_V9:
+  case SP::FBCONDA_V9:
+    return isIntN(BPccDisplacementBits, Offset >> 2);
+  }
+
+  llvm_unreachable("Unknown branch instruction!");
+}
+
 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,
                                  MCRegister SrcReg, bool KillSrc) const {
   unsigned numSubRegs = 0;
   unsigned movOpc     = 0;
   const unsigned *subRegIdx = nullptr;
   bool ExtraG0 = false;
Register SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
 
   DebugLoc dl;
 
   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
   SparcFI->setGlobalBaseReg(GlobalBaseReg);
   return GlobalBaseReg;
 }
 
+unsigned SparcInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
+  unsigned Opcode = MI.getOpcode();
+
+  if (MI.isInlineAsm()) {
+    const MachineFunction *MF = MI.getParent()->getParent();
+    const char *AsmStr = MI.getOperand(0).getSymbolName();
+    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
+  }
+
+  // If the instruction has a delay slot, be conservative and also include
+  // it for sizing purposes. This is done so that the BranchRelaxation pass
+  // will not mistakenly mark out-of-range branches as in-range.
+  if (MI.hasDelaySlot())
+    return get(Opcode).getSize() * 2;
+  return get(Opcode).getSize();
+}
+
 bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case TargetOpcode::LOAD_STACK_GUARD: {
     assert(Subtarget.isTargetLinux() &&
            "Only Linux target is expected to contain LOAD_STACK_GUARD");
     // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
     const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
     MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addReg(SP::G7)
         .addImm(Offset);
     return true;
   }
   }
   return false;
 }

llvm/lib/Target/Sparc/SparcInstrInfo.td

 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
   : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
 
 // Same as BranchAlways but uses the new v9 encoding
 class BranchPredictAlways<dag ins, string asmstr, list<dag> pattern>
   : F2_3<0b001, 0, 1, (outs), ins, asmstr, pattern>;
 }
 
-let cond = 8 in {
-  // If we're compiling for v9, prefer BPA rather than BA
-  // TODO: Disallow BA emission when FeatureV8Deprecated isn't enabled
-  let Predicates = [HasV9], cc = 0b00 in
-    def BPA : BranchPredictAlways<(ins bprtarget:$imm19),
-      "ba %icc, $imm19", [(br bb:$imm19)]>;
-
+let cond = 8 in
   def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
-}
 
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
 
 // conditional branch class:
 class BranchSP<dag ins, string asmstr, list<dag> pattern>
  : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
 
 // conditional branch with annul class:

llvm/lib/Target/Sparc/SparcTargetMachine.cpp

extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializeSparcDAGToDAGISelPass(PR);
 }
 
+static cl::opt<bool>
+    BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
+                     cl::desc("Relax out of range conditional branches"));
+
 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
   // Sparc is typically big endian, but some are little.
   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
   Ret += "-m:e";
 
   // Some ABIs have 32bit pointers.
   if (!is64Bit)
     Ret += "-p:32:32";

 }
 
 bool SparcPassConfig::addInstSelector() {
   addPass(createSparcISelDag(getSparcTargetMachine()));
   return false;
 }
 
 void SparcPassConfig::addPreEmitPass(){
+  if (BranchRelaxation)
+    addPass(&BranchRelaxationPassID);
+
   addPass(createSparcDelaySlotFillerPass());
 
   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
   {
     addPass(new InsertNOPLoad());
   }
   if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
     addPass(new DetectRoundChange());
   }
   if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
   {

llvm/test/CodeGen/SPARC/branches-relax.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=sparc64 -sparc-bpcc-offset-bits=4 | FileCheck --check-prefix=SPARC64 %s
+
+define i32 @branch_relax_int(i32 %in) {
+; SPARC64-LABEL: branch_relax_int:
+; SPARC64:         .cfi_startproc
+; SPARC64-NEXT:  ! %bb.0:
+; SPARC64-NEXT:    save %sp, -128, %sp
+; SPARC64-NEXT:    .cfi_def_cfa_register %fp
+; SPARC64-NEXT:    .cfi_window_save
+; SPARC64-NEXT:    .cfi_register %o7, %i7
+; SPARC64-NEXT:    cmp %i0, 0
+; SPARC64-NEXT:    bne %icc, .LBB0_1
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    ba .LBB0_2
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  .LBB0_1: ! %false
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore %g0, %g0, %o0
+; SPARC64-NEXT:  .LBB0_2: ! %true
+; SPARC64-NEXT:    mov 4, %i0
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore
+  %tst = icmp eq i32 %in, 0
+  br i1 %tst, label %true, label %false
+
+true:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret i32 4
+
+false:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret i32 0
+}
+
+define float @branch_relax_float(float %in) {
+; SPARC64-LABEL: branch_relax_float:
+; SPARC64:         .cfi_startproc
+; SPARC64-NEXT:  ! %bb.0:
+; SPARC64-NEXT:    save %sp, -128, %sp
+; SPARC64-NEXT:    .cfi_def_cfa_register %fp
+; SPARC64-NEXT:    .cfi_window_save
+; SPARC64-NEXT:    .cfi_register %o7, %i7
+; SPARC64-NEXT:    sethi %h44(.LCPI1_0), %i0
+; SPARC64-NEXT:    add %i0, %m44(.LCPI1_0), %i0
+; SPARC64-NEXT:    sllx %i0, 12, %i0
+; SPARC64-NEXT:    ld [%i0+%l44(.LCPI1_0)], %f0
+; SPARC64-NEXT:    fcmps %fcc0, %f1, %f0
+; SPARC64-NEXT:    fbe %fcc0, .LBB1_1
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    ba .LBB1_2
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  .LBB1_1: ! %true
+; SPARC64-NEXT:    sethi %h44(.LCPI1_1), %i0
+; SPARC64-NEXT:    add %i0, %m44(.LCPI1_1), %i0
+; SPARC64-NEXT:    sllx %i0, 12, %i0
+; SPARC64-NEXT:    ld [%i0+%l44(.LCPI1_1)], %f0
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore
+; SPARC64-NEXT:  .LBB1_2: ! %false
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore
+  %tst = fcmp oeq float %in, 0.0
+  br i1 %tst, label %true, label %false
+
+true:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret float 4.0
+
+false:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret float 0.0
+}

llvm/test/CodeGen/SPARC/branches-v9.ll

 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    cmp %i0, 0
 ; CHECK-NEXT:    be %icc, .LBB0_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.1: ! %fbb
 ; CHECK-NEXT:    call f2
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    ba %icc, .LBB0_3
+; CHECK-NEXT:    ba .LBB0_3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB0_2: ! %tbb
 ; CHECK-NEXT:    call f1
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB0_3: ! %end
 ; CHECK-NEXT:    call f3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    cmp %i0, 0
 ; CHECK-NEXT:    be %xcc, .LBB1_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.1: ! %fbb
 ; CHECK-NEXT:    call f2
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    ba %icc, .LBB1_3
+; CHECK-NEXT:    ba .LBB1_3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB1_2: ! %tbb
 ; CHECK-NEXT:    call f1
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB1_3: ! %end
 ; CHECK-NEXT:    call f3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ret

llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll

 ; SPARC-NEXT:    xor %i5, %g2, %i5
 ; SPARC-NEXT:    xor %i3, %g2, %i3
 ; SPARC-NEXT:    or %i3, %i5, %i3
 ; SPARC-NEXT:    xor %i4, %g2, %i4
 ; SPARC-NEXT:    xor %i2, %g2, %i2
 ; SPARC-NEXT:    or %i2, %i4, %i2
 ; SPARC-NEXT:    or %i2, %i3, %i2
 ; SPARC-NEXT:    cmp %i2, 0
-; SPARC-NEXT:    bne .LBB0_1
+; SPARC-NEXT:    bne .LBB0_2
 ; SPARC-NEXT:    nop
-; SPARC-NEXT:  ! %bb.2: ! %start
+; SPARC-NEXT:  ! %bb.1: ! %start
 ; SPARC-NEXT:    ba .LBB0_3
 ; SPARC-NEXT:    mov %g0, %i4
-; SPARC-NEXT:  .LBB0_1:
+; SPARC-NEXT:  .LBB0_2:
 ; SPARC-NEXT:    mov 1, %i4
 ; SPARC-NEXT:  .LBB0_3: ! %start
 ; SPARC-NEXT:    ld [%fp+-4], %i2 ! 4-byte Folded Reload
 ; SPARC-NEXT:    ld [%fp+-8], %i3 ! 4-byte Folded Reload
 ; SPARC-NEXT:    ret
 ; SPARC-NEXT:    restore
 ;
 ; SPARC64-LABEL: muloti_test:

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.generated.expected

 ; CHECK-NEXT:  ! %bb.0:
 ; CHECK-NEXT:    save %sp, -112, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    st %g0, [%fp+-4]
 ; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    st %g0, [%fp+-8]
-; CHECK-NEXT:    be .LBB0_1
+; CHECK-NEXT:    be .LBB0_2
 ; CHECK-NEXT:    mov 1, %i0
-; CHECK-NEXT:  ! %bb.2:
+; CHECK-NEXT:  ! %bb.1:
 ; CHECK-NEXT:    ba .LBB0_3
 ; CHECK-NEXT:    st %i0, [%fp+-16]
-; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    st %i0, [%fp+-8]
 ; CHECK-NEXT:    mov 2, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-12]
 ; CHECK-NEXT:    mov 3, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:    mov 4, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-20]
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    ld [%fp+-8], %i0
 ; CHECK-NEXT:    cmp %i0, 0
-; CHECK-NEXT:    be .LBB0_4
+; CHECK-NEXT:    be .LBB0_5
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:  ! %bb.5:
+; CHECK-NEXT:  ! %bb.4:
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:    ba .LBB0_6
 ; CHECK-NEXT:    st %i0, [%fp+-16]
-; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:  .LBB0_5:
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-8]
 ; CHECK-NEXT:    mov 2, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-12]
 ; CHECK-NEXT:    mov 3, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:    mov 4, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-20]

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.nogenerated.expected

 ; CHECK-NEXT:  ! %bb.0:
 ; CHECK-NEXT:    save %sp, -112, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    st %g0, [%fp+-4]
 ; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    st %g0, [%fp+-8]
-; CHECK-NEXT:    be .LBB0_1
+; CHECK-NEXT:    be .LBB0_2
 ; CHECK-NEXT:    mov 1, %i0
-; CHECK-NEXT:  ! %bb.2:
+; CHECK-NEXT:  ! %bb.1:
 ; CHECK-NEXT:    ba .LBB0_3
 ; CHECK-NEXT:    st %i0, [%fp+-16]
-; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    st %i0, [%fp+-8]
 ; CHECK-NEXT:    mov 2, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-12]
 ; CHECK-NEXT:    mov 3, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:    mov 4, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-20]
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    ld [%fp+-8], %i0
 ; CHECK-NEXT:    cmp %i0, 0
-; CHECK-NEXT:    be .LBB0_4
+; CHECK-NEXT:    be .LBB0_5
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:  ! %bb.5:
+; CHECK-NEXT:  ! %bb.4:
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:    ba .LBB0_6
 ; CHECK-NEXT:    st %i0, [%fp+-16]
-; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:  .LBB0_5:
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-8]
 ; CHECK-NEXT:    mov 2, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-12]
 ; CHECK-NEXT:    mov 3, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:    mov 4, %i0
 ; CHECK-NEXT:    st %i0, [%fp+-20]