[X86] Prioritize lowering V{4|16}F32 with blend.

[goldstein.w.n]

Summary

Blend is often fastest available instruction so it should be higher
priority for v4f32 and an option for v16f32.

[RKSimon]

LGTM

[goldstein.w.n]

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[RKSimon]

@goldstein.w.n You have a lot of accepted but unmerged patches - it would be better to get them committed than just repeatedly rebasing them

[goldstein.w.n]

In D143856#4149420, @RKSimon wrote:

@goldstein.w.n You have a lot of accepted but unmerged patches - it would be better to get them committed than just repeatedly rebasing them

Ahh sure, habit is to do series all at once, but can push some first.

[goldstein.w.n]

In D143856#4149420, @RKSimon wrote:

@goldstein.w.n You have a lot of accepted but unmerged patches - it would be better to get them committed than just repeatedly rebasing them

pushed up to D143786

llvm/lib/Target/X86/X86ISelLowering.cpp

 static SDValue lowerV4F32Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
                                  const APInt &Zeroable, SDValue V1, SDValue V2,
                                  const X86Subtarget &Subtarget,
                                  SelectionDAG &DAG) {
   assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
   assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
   assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
 
+  if (Subtarget.hasSSE41())
+    if (SDValue Blend = lowerShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
+                                            Zeroable, Subtarget, DAG))
+      return Blend;
+
   int NumV2Elements = count_if(Mask, [](int M) { return M >= 4; });
 
   if (NumV2Elements == 0) {
     // Check for being able to broadcast a single element.
     if (SDValue Broadcast = lowerShuffleAsBroadcast(DL, MVT::v4f32, V1, V2,
                                                     Mask, Subtarget, DAG))
       return Broadcast;
 
static SDValue lowerV4F32Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
   // when the V2 input is targeting element 0 of the mask -- that is the fast
   // case here.
   if (NumV2Elements == 1 && Mask[0] >= 4)
     if (SDValue V = lowerShuffleAsElementInsertion(
             DL, MVT::v4f32, V1, V2, Mask, Zeroable, Subtarget, DAG))
       return V;
 
   if (Subtarget.hasSSE41()) {
-    if (SDValue Blend = lowerShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
-                                            Zeroable, Subtarget, DAG))
-      return Blend;
-
     // Use INSERTPS if we can complete the shuffle efficiently.
     if (SDValue V = lowerShuffleAsInsertPS(DL, V1, V2, Mask, Zeroable, DAG))
       return V;
 
     if (!isSingleSHUFPSMask(Mask))
       if (SDValue BlendPerm = lowerShuffleAsBlendAndPermute(DL, MVT::v4f32, V1,
                                                             V2, Mask, DAG))
         return BlendPerm;
if (is128BitLaneRepeatedShuffleMask(MVT::v16f32, Mask, RepeatedMask)) {
     if (SDValue Blend = lowerShuffleAsBlend(DL, MVT::v16f32, V1, V2, Mask,
                                             Zeroable, Subtarget, DAG))
       return Blend;
 
     // Otherwise, fall back to a SHUFPS sequence.
     return lowerShuffleWithSHUFPS(DL, MVT::v16f32, RepeatedMask, V1, V2, DAG);
   }
 
+  if (SDValue Blend = lowerShuffleAsBlend(DL, MVT::v16f32, V1, V2, Mask,
+                                          Zeroable, Subtarget, DAG))
+    return Blend;
+
   // Try to create an in-lane repeating shuffle mask and then shuffle the
   // results into the target lanes.
   if (SDValue V = lowerShuffleAsRepeatedMaskAndLanePermute(
           DL, MVT::v16f32, V1, V2, Mask, Subtarget, DAG))
     return V;
 
   // If we have a single input shuffle with different shuffle patterns in the
   // 128-bit lanes and don't lane cross, use variable mask VPERMILPS.

llvm/test/CodeGen/X86/avx512-insert-extract.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck --check-prefixes=CHECK,KNL %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck --check-prefixes=CHECK,SKX %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq,+avx512vbmi | FileCheck --check-prefixes=CHECK,SKX %s
 
 define <16 x float> @test1(<16 x float> %x, ptr %br, float %y) nounwind {
-; CHECK-LABEL: test1:
-; CHECK:       ## %bb.0:
-; CHECK-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0],mem[0],xmm0[2,3]
-; CHECK-NEXT:    vinsertf32x4 $0, %xmm2, %zmm0, %zmm2
-; CHECK-NEXT:    vbroadcastss %xmm1, %zmm1
-; CHECK-NEXT:    vmovaps {{.*#+}} zmm0 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,30,15]
-; CHECK-NEXT:    vpermi2ps %zmm1, %zmm2, %zmm0
-; CHECK-NEXT:    retq
+; KNL-LABEL: test1:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0],mem[0],xmm0[2,3]
+; KNL-NEXT:    vinsertf32x4 $0, %xmm2, %zmm0, %zmm0
+; KNL-NEXT:    movw $16384, %ax ## imm = 0x4000
+; KNL-NEXT:    kmovw %eax, %k1
+; KNL-NEXT:    vbroadcastss %xmm1, %zmm0 {%k1}
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: test1:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    vinsertps {{.*#+}} xmm2 = xmm0[0],mem[0],xmm0[2,3]
+; SKX-NEXT:    vinsertf32x4 $0, %xmm2, %zmm0, %zmm0
+; SKX-NEXT:    movw $16384, %ax ## imm = 0x4000
+; SKX-NEXT:    kmovd %eax, %k1
+; SKX-NEXT:    vbroadcastss %xmm1, %zmm0 {%k1}
+; SKX-NEXT:    retq
   %rrr = load float, ptr %br
   %rrr2 = insertelement <16 x float> %x, float %rrr, i32 1
   %rrr3 = insertelement <16 x float> %rrr2, float %y, i32 14
   ret <16 x float> %rrr3
 }
 
 define <8 x double> @test2(<8 x double> %x, ptr %br, double %y) nounwind {
 ; KNL-LABEL: test2:

llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll

; X86-AVX512F-NEXT:    retl
   %resE = insertelement <16 x float> %resC, float %valE, i32 14
   %resF = insertelement <16 x float> %resE, float %valF, i32 15
   ret <16 x float> %resF
 }
 
 define <16 x float> @merge_16f32_f32_0uu3zzuuuuuzCuEF(ptr %ptr) nounwind uwtable noinline ssp {
 ; ALL-LABEL: merge_16f32_f32_0uu3zzuuuuuzCuEF:
 ; ALL:       # %bb.0:
-; ALL-NEXT:    vmovups (%rdi), %zmm1
-; ALL-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; ALL-NEXT:    vmovaps {{.*#+}} zmm0 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
-; ALL-NEXT:    vpermi2ps %zmm2, %zmm1, %zmm0
+; ALL-NEXT:    vmovdqu64 (%rdi), %zmm0
+; ALL-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
 ; ALL-NEXT:    retq
 ;
 ; X86-AVX512F-LABEL: merge_16f32_f32_0uu3zzuuuuuzCuEF:
 ; X86-AVX512F:       # %bb.0:
 ; X86-AVX512F-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-AVX512F-NEXT:    vmovups (%eax), %zmm1
-; X86-AVX512F-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; X86-AVX512F-NEXT:    vmovaps {{.*#+}} zmm0 = <0,u,u,3,20,21,u,u,u,u,u,u,12,29,14,15>
-; X86-AVX512F-NEXT:    vpermi2ps %zmm2, %zmm1, %zmm0
+; X86-AVX512F-NEXT:    vmovdqu64 (%eax), %zmm0
+; X86-AVX512F-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
 ; X86-AVX512F-NEXT:    retl
   %ptr3 = getelementptr inbounds float, ptr %ptr, i64 3
   %ptrC = getelementptr inbounds float, ptr %ptr, i64 12
   %ptrE = getelementptr inbounds float, ptr %ptr, i64 14
   %ptrF = getelementptr inbounds float, ptr %ptr, i64 15
   %val0 = load float, ptr %ptr
   %val3 = load float, ptr %ptr3
   %valC = load float, ptr %ptrC