This patch updates the remaining SparseCompiler integration tests to
target SVE when available.
TODO: Triage sparse_matmul.mlir and sparse_tanh.mlir
Paths
| Differential D143514
[mlir][sparse] Port the remaining integration tests to use SVE ClosedPublic Authored by awarzynski on Feb 7 2023, 9:49 AM.
Details Summary This patch updates the remaining SparseCompiler integration tests to TODO: Triage sparse_matmul.mlir and sparse_tanh.mlir
Diff Detail
Event Timeline
Comment Actions
There are currently two tests that are XFAIL'ed - I will triage them shortly. Tested with:
Comment Actions Split "sparse_reduce_custom.mlir" into two tests I've split sparse_reduce_custom.mlir into:
The latter contains product reducitons that are currently supported on AArch64. We did the same for Comment Actions Note that in the long run it would perhaps be desirable to really skip the run if there is no VLA available, since we now do another similar run in most cases, which wastes testing resources. This revision is now accepted and ready to land.Feb 8 2023, 12:38 PM Closed by commit rGbfe4ce3f8339: [mlir][sparse] Port the remaining integration tests to use SVE (authored by awarzynski). · Explain WhyFeb 9 2023, 2:16 AM This revision was automatically updated to reflect the committed changes. Comment Actions Thanks for reviewing!
I have also thought about it and created https://github.com/llvm/llvm-project/issues/60628 to track this. Btw, I created https://github.com/llvm/llvm-project/issues/60626 for the outstanding issues with the generated output. frgossen added inline comments.
Peiming added inline comments.
Comment Actions @frgossen , I'm sorry that you are hitting these issues :(
No, sorry. But perhaps we should be using fpcmp for verifying FP output 🤔 . clang-aarch64-sve-vla (which runs these tests) is green, so ideally I would avoid reverting this change. Perhaps you could blacklist the failing tests and create a GitHub ticket like https://github.com/llvm/llvm-project/issues/60626? We may need to approach this on a case-by-case basis. Comment Actions Fix in https://reviews.llvm.org/D143674 (our new push_back uses size/capacity a bit different, so a vector_transfer+print may see unitialized memory, which is why the enable-buffer-initialization was introduced to make sure memory is consistent) if there are issues beyond this problem, please let me know!
Revision Contents
Diff 495580 mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_dim.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_foreach.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2dense.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2sparse.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_io.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reshape.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_push_back.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort_coo.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_c32.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_f16.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir
mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir
|
We actually always run this right? If so, we should really make this (here and everywhere)
// Do the same run, but now with direct IR generation and, if available, VLA