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bixia (Bixia Zheng)
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User Since
Nov 17 2017, 12:00 PM (96 w, 19 h)

Recent Activity

Apr 3 2019

bixia updated the diff for D60168: [test-suite,CUDA] Add #include <stdio.h> to test_round.cu to fix a build error..

Remove iostream.

Apr 3 2019, 11:51 AM · Restricted Project

Apr 2 2019

bixia added a reviewer for D60168: [test-suite,CUDA] Add #include <stdio.h> to test_round.cu to fix a build error.: tra.
Apr 2 2019, 5:53 PM · Restricted Project
bixia created D60168: [test-suite,CUDA] Add #include <stdio.h> to test_round.cu to fix a build error..
Apr 2 2019, 5:53 PM · Restricted Project

Apr 1 2019

bixia committed rG6c21ccd245bb: [NVPTX] Fix the codegen for llvm.round. (authored by bixia).
[NVPTX] Fix the codegen for llvm.round.
Apr 1 2019, 9:09 AM

Mar 29 2019

bixia updated the diff for D59947: [NVPTX] Fix the codegen for llvm.round..

Rewrite a few magic constants in a different form, hoping this can make it easier to understand what is going on.

Mar 29 2019, 4:14 PM · Restricted Project
bixia updated the diff for D59950: [test-suite,CUDA] Add a test case to test the edge cases for the implementation of llvm.round intrinsic in the PTX backend..

Modify test to also check a negative value beyond -max(float).

Mar 29 2019, 11:39 AM · Restricted Project
bixia updated the summary of D59947: [NVPTX] Fix the codegen for llvm.round..
Mar 29 2019, 11:31 AM · Restricted Project
bixia updated the diff for D59947: [NVPTX] Fix the codegen for llvm.round..

Fix commit message.

Mar 29 2019, 11:26 AM · Restricted Project
bixia updated the diff for D59947: [NVPTX] Fix the codegen for llvm.round..

Modify test cases to check for the use of some constants.

Mar 29 2019, 11:17 AM · Restricted Project

Mar 28 2019

bixia updated the diff for D59950: [test-suite,CUDA] Add a test case to test the edge cases for the implementation of llvm.round intrinsic in the PTX backend..

Fix the test to pass in a scalar value instead of a pointer.
Remove unnecessary device memory allocation and copy.
Add a call to cudaDeviceSynchronize.

Mar 28 2019, 6:45 PM · Restricted Project
bixia updated the diff for D59950: [test-suite,CUDA] Add a test case to test the edge cases for the implementation of llvm.round intrinsic in the PTX backend..

Rename round.cu to test_round.cu.
Fix the intrinsic for double.
Change the test to use assert and a variable to prevent constant folding.

Mar 28 2019, 6:17 PM · Restricted Project
bixia added a comment to D59947: [NVPTX] Fix the codegen for llvm.round..

Does XLA:GPU built with this change pass the exhaustive test you added for kRound after we revert the change that made kRound call into libdevice?

Mar 28 2019, 5:19 PM · Restricted Project
bixia added a reviewer for D59950: [test-suite,CUDA] Add a test case to test the edge cases for the implementation of llvm.round intrinsic in the PTX backend.: tra.
Mar 28 2019, 11:11 AM · Restricted Project
bixia created D59950: [test-suite,CUDA] Add a test case to test the edge cases for the implementation of llvm.round intrinsic in the PTX backend..
Mar 28 2019, 11:11 AM · Restricted Project
bixia added a reviewer for D59947: [NVPTX] Fix the codegen for llvm.round.: tra.
Mar 28 2019, 10:20 AM · Restricted Project
bixia created D59947: [NVPTX] Fix the codegen for llvm.round..
Mar 28 2019, 10:16 AM · Restricted Project

Mar 22 2019

bixia committed rGbdf0230cffd1: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow. (authored by bixia).
[ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow.
Mar 22 2019, 9:37 AM

Mar 19 2019

bixia updated the diff for D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow..

Modify test case to check the return value.

Mar 19 2019, 5:11 PM · Restricted Project
bixia added a comment to D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow..

The problem is only reported by ubsan (undefined behavior sanitizer). My test case produces a value of 1.27e+80, which is a value between max(float) and max(double). Without ubsan, llvm opt (compiled with clang for x86) produces the correct result silently. However, since (float)the-double-value has undefined behavior by c++ language, there is no guarantee that the llvm opt produced by any compiler for any platform produces the same result. Do you have suggestion on what is a better test case?

Mar 19 2019, 1:38 PM · Restricted Project
bixia updated the diff for D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow..

Update commit message.

Mar 19 2019, 9:13 AM · Restricted Project
bixia updated the diff for D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow..

Add a test case.

Mar 19 2019, 9:13 AM · Restricted Project

Mar 18 2019

bixia added a reviewer for D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow.: sanjoy.
Mar 18 2019, 11:37 AM · Restricted Project
bixia created D59500: [ConstantFolding] Fix GetConstantFoldFPValue to avoid cast overflow..
Mar 18 2019, 10:31 AM · Restricted Project

Jun 6 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

@spatel Thanks for your comment! I need to revise my example to better match the real case I am looking at-- in particular, to show that the optimization will increase the number of zext instructions. In this example, there are only two zext instructions. However, if we narrow all the arithmetic operations to i32 we will need four zext instructions. In one of your previous comment, you have suggested to extend TruncInstCombine in aggressive-instcombine. I see the following issues: (1) TruncInstCombine doesn't increase the number of zext/sext instructions. (2) TruncInstCombine currently only handles operations with this properties truncate(op(i64), i32) == op(truncate(i64, i32)), div/rem/right-shift which are needed here aren't part of such operations. We can properly add value range analysis to resolve this though. (3) TruncInstCombine is driven by the truncate instruction in the IR, and there is no such truncate instruction in the case here. To handle the case here (such as the pattern "lshr followed by shl" you mentioned) , is it acceptable to add a new optimization to aggressive-instcombine that can increase the number of zext/sext instructions?

Jun 6 2018, 4:04 PM · Restricted Project

Jun 5 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

What Sanjoy suggested doesn't (completely) solve the problem we have , where UDIV and UREM are used to calculate the dimensional indices from a linear index, and the dimensionally indices are then used to access tensors of different shapes (for example, two tensors being accessed both require broadcasting but along different dimensions).
With the current state of D47113, would it be acceptable if I revise my change here to only narrow i64 udiv/urem to i32 using the added patterns?

Jun 5 2018, 10:03 PM · Restricted Project

May 21 2018

bixia added a comment to D47113: [CVP] Teach CorrelatedValuePropagation to reduce the width of lshr instruction..

InstCombiner::visitShl performs similar narrowing without checking user count and can increase the total number to ZExt instructions.

May 21 2018, 8:42 AM · Restricted Project
bixia added a comment to D47113: [CVP] Teach CorrelatedValuePropagation to reduce the width of lshr instruction..

InstCombiner::visitLShr can perform the same transformation for the cases where correlated-value propagation is not needed to discover the range of the values.
However, unlike the transformation here, InstCombiner::visitLShr carefully makes sure that the transformation won't increase the total number of ZExt/ZExt instructions (Op1.hasOneUse check). Why the transformation here doesn't need similar check? Is it safe to remove such a check in InstCombiner::visitLShr?

May 21 2018, 12:00 AM · Restricted Project

May 18 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

Ping.

May 18 2018, 3:18 PM · Restricted Project

May 14 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

Instcombine has udiv/urem narrowing without increasing the total number of ZExt instructions. Correlated-Propagation has udiv/urem narrowing that can increasing the total number of ZExt instruction (kind of a superset of what is in instcombine). These are existing duplicated functionalities. I have considered two possible changes to this: (1) allow instcombine to increase the total number of ZExt instructions in general (by simply removing the m_oneuse related checks). (2) as shown in this change, allow instcombine to handle a special case and may increase the number of ZExt instructions by one.
I looked at other similar narrowing transformations in instcombine, and found most of them have the check to avoid increasing the total number of ZExt/SExt instructions (lshr narrowing for example), but some of them don't have such a check (shl narrowing for example). I am not sure whether these are by design or due to something else such as ignorance. Do you know about this?

May 14 2018, 8:45 AM · Restricted Project

May 13 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

Are you suggesting to teach correlated-propagation to narrow shl/and? InstCombine can perform such narrowing, I don't see why it is better to duplicate this in correlated-propagation. Can you explain? The "m_OneUse" check in the code I am changing here is a simple logic to make sure that the transformation do not increase the number of ZExt instructions. I basically add a little more logic there to say "if there are two uses, and we can guarantee that the transformation do not increase the number of ZExt instructions, we also want to perform the transformation here. " What are your concerns for such a change?

May 13 2018, 10:04 AM · Restricted Project

May 12 2018

bixia added a comment to D46760: [InstCombine] Enhance narrowUDivURem..

Yes, you are right in that correlated value propagation can handle the case. However, if the divisor is a power of 2 and instcombine is invoked before correlated value propagation (as in the opt passes), instcombine transforms the i64 udiv/urem into i64 shift/and. My original motivated test case is like below, the change here is required in order for opt transform all the i64 arithmetic operations into i32 operations.

May 12 2018, 8:36 PM · Restricted Project
bixia updated the diff for D46760: [InstCombine] Enhance narrowUDivURem..

Use early return.

May 12 2018, 8:21 PM · Restricted Project

May 11 2018

bixia added inline comments to D46760: [InstCombine] Enhance narrowUDivURem..
May 11 2018, 10:55 AM · Restricted Project
bixia updated the summary of D46760: [InstCombine] Enhance narrowUDivURem..
May 11 2018, 10:52 AM · Restricted Project
bixia updated the diff for D46760: [InstCombine] Enhance narrowUDivURem..

Add another test case.

May 11 2018, 10:46 AM · Restricted Project
bixia added a reviewer for D46760: [InstCombine] Enhance narrowUDivURem.: sanjoy.
May 11 2018, 10:17 AM · Restricted Project
bixia created D46760: [InstCombine] Enhance narrowUDivURem..
May 11 2018, 10:13 AM · Restricted Project

Apr 26 2018

bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Removed nuw nsw from the tests.
Apr 26 2018, 1:28 PM

Apr 25 2018

bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Removed nuw nsw from the tests.
Apr 25 2018, 2:49 PM
bixia added inline comments to D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 25 2018, 2:49 PM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Removed nuw nsw from the tests.
Apr 25 2018, 2:45 PM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Removed nuw nsw from the tests.
Apr 25 2018, 1:30 PM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Removed nuw nsw from the tests.
  • Removed \brief from the comment.
Apr 25 2018, 12:03 PM
bixia added inline comments to D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 25 2018, 11:23 AM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Remove nuw nsw from the tests.
Apr 25 2018, 11:21 AM

Apr 24 2018

bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Applied git clang-format.
Apr 24 2018, 4:20 PM
bixia added inline comments to D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 24 2018, 3:32 PM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Use prefix ++ instead of postfix ++.
Apr 24 2018, 3:10 PM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Use prefix ++ instead of postfix ++.
Apr 24 2018, 11:42 AM
bixia added a child revision for D46017: Add test cases to prepare for the optimization that simplifies Add with remainder expressions as operands.: D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 24 2018, 9:43 AM
bixia added a parent revision for D45976: [InstCombine] Simplify Add with remainder expressions as operands.: D46017: Add test cases to prepare for the optimization that simplifies Add with remainder expressions as operands..
Apr 24 2018, 9:43 AM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Use instnamer to fix names.
Apr 24 2018, 9:38 AM
bixia added inline comments to D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 24 2018, 9:33 AM
bixia updated the diff for D45976: [InstCombine] Simplify Add with remainder expressions as operands..
  • Use instnamer to fix names.
Apr 24 2018, 9:32 AM
bixia updated the diff for D46017: Add test cases to prepare for the optimization that simplifies Add with remainder expressions as operands..
  • Use instnamer to fix the name of the tests.
Apr 24 2018, 9:11 AM
bixia created D46017: Add test cases to prepare for the optimization that simplifies Add with remainder expressions as operands..
Apr 24 2018, 8:44 AM

Apr 23 2018

bixia updated the summary of D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 23 2018, 11:21 AM
bixia created D45976: [InstCombine] Simplify Add with remainder expressions as operands..
Apr 23 2018, 11:16 AM
bixia updated the summary of D45974: Here is the summary..
Apr 23 2018, 10:38 AM
bixia updated the diff for D45974: Here is the summary..
  • Add a blank line.
Apr 23 2018, 10:36 AM
bixia created D45974: Here is the summary..
Apr 23 2018, 10:35 AM

Apr 6 2018

bixia accepted D45391: [NVPTX] add support for initializing fp16 arrays..
Apr 6 2018, 3:20 PM
bixia accepted D45339: [NVPTX] Fixed vectorized LDG for f16..
Apr 6 2018, 2:00 PM

Apr 5 2018

bixia added inline comments to D45339: [NVPTX] Fixed vectorized LDG for f16..
Apr 5 2018, 7:18 PM
bixia added inline comments to D45339: [NVPTX] Fixed vectorized LDG for f16..
Apr 5 2018, 4:21 PM