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Differential D143367

[RISCV] Remove DecoderMethod from C_NOP_HINT. NFC
ClosedPublic

Authored by craig.topper on Feb 5 2023, 9:33 PM.

Details

Reviewers
asb
luismarques
reames
kito-cheng
jrtc27
Commits
rG2398e2057cfa: [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC
Summary

This doesn't appear to be needed.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 5 2023, 9:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 5 2023, 9:33 PM
Herald added subscribers: luke, VincentWu, vkmr and 24 others. · View Herald Transcript
craig.topper requested review of this revision.Feb 5 2023, 9:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 5 2023, 9:33 PM
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Harbormaster completed remote builds in B211999: Diff 494998.Feb 5 2023, 9:34 PM
luismarques accepted this revision.Feb 6 2023, 3:40 AM

LGTM. It might have been needed in an older version of D62592.

This revision is now accepted and ready to land.Feb 6 2023, 3:40 AM
This revision was landed with ongoing or failed builds.Feb 6 2023, 7:26 AM
Closed by commit rG2398e2057cfa: [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG2398e2057cfa: [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
Disassembler/
15 lines
1 line

Diff 495128

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Show First 20 Lines • Show All 347 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
Inst.addOperand(MCOperand::createImm(Imm)); Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder); const MCDisassembler *Decoder);
static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder);
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder); const MCDisassembler *Decoder);
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder); const MCDisassembler *Decoder);
Show All 14 Linesstatic DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
(void)Result; (void)Result;
assert(Result == MCDisassembler::Success && "Invalid register"); assert(Result == MCDisassembler::Success && "Invalid register");
Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(Inst.getOperand(0));
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, uint32_t Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
uint32_t SImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
(void)Result;
assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success;
}
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder) { const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X0)); Inst.addOperand(MCOperand::createReg(RISCV::X0));
uint32_t SImm6 = uint32_t SImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
(void)Result; (void)Result;
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Show First 20 Lines • Show All 605 Lines • ▼ Show 20 Lines
let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0, let Predicates = [HasStdExtCOrZca, HasRVCHints], hasSideEffects = 0, mayLoad = 0,
mayStore = 0 in mayStore = 0 in
{ {
let rd = 0 in let rd = 0 in
def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm), def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
"c.nop", "$imm">, Sched<[WriteNop]> { "c.nop", "$imm">, Sched<[WriteNop]> {
let Inst{6-2} = imm{4-0}; let Inst{6-2} = imm{4-0};
let DecoderMethod = "decodeRVCInstrSImm";
} }
def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb), def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, immzero:$imm), (ins GPRNoX0:$rd, immzero:$imm),
"c.addi", "$rd, $imm">, "c.addi", "$rd, $imm">,
Sched<[WriteIALU, ReadIALU]> { Sched<[WriteIALU, ReadIALU]> {
let Constraints = "$rd = $rd_wb"; let Constraints = "$rd = $rd_wb";
let Inst{12} = 0; let Inst{12} = 0;
▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines