DAG: Lower single infinity is.fpclass tests to fcmp

[arsenm]

Summary

InstCombine also should have taken care of this, but this
should be helpful when the fcmp based lowering strategy tries
to combine multiple tests.

[arsenm]

ping

[sepavloff]

What is the advantage of such lowering?

Implementation of is_fpclass as fcmp requires materialization of infinity constant. In contrast to zero constant, which often can be easily materialized, infinity usually requires loading constant from memory. So additional memory access is required as compared to the default lowering.

[arsenm]

In D143201#4174260, @sepavloff wrote:

What is the advantage of such lowering?

Implementation of is_fpclass as fcmp requires materialization of infinity constant. In contrast to zero constant, which often can be easily materialized, infinity usually requires loading constant from memory. So additional memory access is required as compared to the default lowering.

This also avoids a register bank copy if the target has separate integer and FP banks

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (Flags.hasNoFPExcept() &&
     if (TestMask == fcInf) {
       // isinf(x) --> fabs(x) == inf
       SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op);
       SDValue Inf =
           DAG.getConstantFP(APFloat::getInf(Semantics), DL, OperandVT);
       return DAG.getSetCC(DL, ResultVT, Abs, Inf,
                           IsInverted ? ISD::SETONE : ISD::SETOEQ);
     }
+
+    if (TestMask == fcPosInf || TestMask == fcNegInf) {
+      // isposinf(x) --> x == inf
+      // isneginf(x) --> x == -inf
+      SDValue Inf = DAG.getConstantFP(
+        APFloat::getInf(Semantics, TestMask == fcNegInf), DL, OperandVT);
+      return DAG.getSetCC(DL, ResultVT, Op, Inf,
+                          IsInverted ? ISD::SETONE : ISD::SETOEQ);
+    }
   }
 
   // FIXME: Placeholder until FPClassTest is marked as a BitmaskEnum.
   unsigned Test = static_cast<unsigned>(TestMask);
 
   // In the general case use integer operations.
   unsigned BitSize = OperandVT.getScalarSizeInBits();
   EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), BitSize);

llvm/test/CodeGen/X86/is_fpclass-fp80.ll

 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 516)  ; 0x204 = "inf"
   ret i1 %0
 }
 
 define i1 @is_posinf_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_posinf_f80:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    movl $-2147483648, %ecx # imm = 0x80000000
-; CHECK-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
-; CHECK-32-NEXT:    xorl $32767, %eax # imm = 0x7FFF
-; CHECK-32-NEXT:    orl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    orl %ecx, %eax
-; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    fldt {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-32-NEXT:    fxch %st(1)
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setae %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_posinf_f80:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movzwl {{[0-9]+}}(%rsp), %eax
-; CHECK-64-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
-; CHECK-64-NEXT:    xorq {{[0-9]+}}(%rsp), %rcx
-; CHECK-64-NEXT:    xorq $32767, %rax # imm = 0x7FFF
-; CHECK-64-NEXT:    orq %rcx, %rax
-; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-64-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
+; CHECK-64-NEXT:    fxch %st(1)
+; CHECK-64-NEXT:    fucompi %st(1), %st
+; CHECK-64-NEXT:    fstp %st(0)
+; CHECK-64-NEXT:    setae %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 512)  ; 0x200 = "+inf"
   ret i1 %0
 }
 
 define i1 @is_neginf_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_neginf_f80:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    xorl $65535, %eax # imm = 0xFFFF
-; CHECK-32-NEXT:    movl $-2147483648, %ecx # imm = 0x80000000
-; CHECK-32-NEXT:    xorl {{[0-9]+}}(%esp), %ecx
-; CHECK-32-NEXT:    orl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    orl %ecx, %eax
-; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    fldt {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setae %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_neginf_f80:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movl {{[0-9]+}}(%rsp), %eax
-; CHECK-64-NEXT:    notl %eax
-; CHECK-64-NEXT:    movzwl %ax, %eax
-; CHECK-64-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
-; CHECK-64-NEXT:    xorq {{[0-9]+}}(%rsp), %rcx
-; CHECK-64-NEXT:    orq %rax, %rcx
-; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    fldt {{[0-9]+}}(%rsp)
+; CHECK-64-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
+; CHECK-64-NEXT:    fucompi %st(1), %st
+; CHECK-64-NEXT:    fstp %st(0)
+; CHECK-64-NEXT:    setae %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f80(x86_fp80 %x, i32 4)  ; "-inf"
   ret i1 %0
 }
 
 define i1 @is_normal_f80(x86_fp80 %x) {
 ; CHECK-32-LABEL: is_normal_f80:

llvm/test/CodeGen/X86/is_fpclass.ll

 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507)  ; ~0x204 = "~inf"
   ret i1 %0
 }
 
 define i1 @is_plus_inf_f(float %x) {
 ; CHECK-32-LABEL: is_plus_inf_f:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    cmpl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
-; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-32-NEXT:    fxch %st(1)
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setae %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_plus_inf_f:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movd %xmm0, %eax
-; CHECK-64-NEXT:    cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-64-NEXT:    setae %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512)  ; 0x200 = "+inf"
   ret i1 %0
 }
 
 define i1 @is_minus_inf_f(float %x) {
 ; CHECK-32-LABEL: is_minus_inf_f:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000
-; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setae %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: is_minus_inf_f:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movd %xmm0, %eax
-; CHECK-64-NEXT:    cmpl $-8388608, %eax # imm = 0xFF800000
-; CHECK-64-NEXT:    sete %al
+; CHECK-64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-64-NEXT:    ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT:    setae %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4)  ; "-inf"
   ret i1 %0
 }
 
 define i1 @not_is_minus_inf_f(float %x) {
 ; CHECK-32-LABEL: not_is_minus_inf_f:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    cmpl $-8388608, {{[0-9]+}}(%esp) # imm = 0xFF800000
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    flds {{\.?LCPI[0-9]+_[0-9]+}}
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
 ; CHECK-32-NEXT:    setne %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: not_is_minus_inf_f:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movd %xmm0, %eax
-; CHECK-64-NEXT:    cmpl $-8388608, %eax # imm = 0xFF800000
+; CHECK-64-NEXT:    ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; CHECK-64-NEXT:    setne %al
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1019)  ; ~"-inf"
   ret i1 %0
 }
 
 define i1 @isfinite_f(float %x) {