[SDAG] fix miscompiles caused by using ValueTracking matchSelectPattern to create FMINIMUM/FMAXIMUM

[spatel]

Summary

ValueTracking attempts to match compare+select patterns to FP min/max operations, but it was created before the newer IEEE-754-2019 minimum/maximum ops were defined. Ie, matchSelectPattern() does not account for the -0.0/+0.0 behavior that is specified in the newer standard.

FMINIMUM/FMAXIMUM nodes were created to map to the newer standard:

/// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
/// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
/// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.

We could adjust ValueTracking to deal with signed zero, but it seems like a moot point given the divergent NaN behavior discussed in D143056, so just delete this possibility to avoid bugs when converting IR to SDAG.

[samparker]

Thanks for doing this.

It looks like it could cause some unexpected performance hiccups though... So, for the targets that would return the input NaN, do you think it would be worth implementing a target API for ValueTracking so that it could make a decision, or is this something that have to be sunk into the DAGBuilder? Are there any other uses of matchSelectPattern that could also be making a bogus decision?

[arsenm]

Can you preserve the match with nsz?

I think we need to just rename FMINNUM to FMIN, and have explicit FMINNUM_IEEE2008 (with snan handling and unspecified -0 vs. 0, or whatever version these were introduced), and FMINNUM_IEEE2019 (with specified +0 vs. 0)

[samparker]

Can you preserve the match with nsz?

I'm not sure I follow why signalling is important here? I've noticed that we'll lower FMINNUM to FMINIMUM, in TargetLowering::expandFMINNUM_FMAXNUM, in the absence of any NaNs - but that also doesn't appear to respect the +/-0 issue raised here.

[arsenm]

In D143106#4099451, @samparker wrote:

Can you preserve the match with nsz?

I'm not sure I follow why signalling is important here?

I didn’t say it was, but changing from select to a min introduces quieting which wouldn’t happen before

[spatel]

In D143106#4099017, @samparker wrote:

It looks like it could cause some unexpected performance hiccups though... So, for the targets that would return the input NaN, do you think it would be worth implementing a target API for ValueTracking so that it could make a decision, or is this something that have to be sunk into the DAGBuilder? Are there any other uses of matchSelectPattern that could also be making a bogus decision?

I agree that this seems likely to cause some perf regressions based on the test diffs. If we can find a way to avoid those, that works for me, but it's such a mess, I figured we should just remove this hunk of wrong code as a first step.

Let me try to summarize where we stand:

1. The select pattern in IR guarantees that we would return a NaN input bitwise exactly. The FMINIMUM/FMAXIMUM intrinsics/nodes don't guarantee that, and as noted in D143056, the targets that implement this operation tend to return a canonical NaN rather than propagate a NaN payload. Given that, changing semantics in IR or SDAG to accommodate this transform does not seem viable.

2. The select pattern in IR differs in its treatment of -0.0, so we have potential for real numeric miscompiles as shown in the test diffs here. It seems likely that we will add even more MIN/MAX node variations to match target behavior, but I'm not sure what that behavior is yet, so I don't know what a good solution will be. As an example of an existing codegen semantic variation of min/max, note that x86 has target-specific FMAXC/FMINC nodes.

3. We could look for 'nsz' and 'nnan' on the IR to make the transform sound, but it requires a questionable combination of FMF on the fcmp and select: https://alive2.llvm.org/ce/z/vjV9AC . This might get better with the nofpclass attribute proposed in D139902.

4. I don't think we need to worry about SNaN with this transform because we're not using strict math -- strict variants of the MIN/MAX nodes already exist -- but I'm also not sure how that path works yet. I was ignoring that complication for now. There is an attempt to clarify SNaN behavior with a LangRef edit in D143074 in case that part wasn't clear enough.

[spatel]

In D143106#4099017, @samparker wrote:

So, for the targets that would return the input NaN, do you think it would be worth implementing a target API for ValueTracking so that it could make a decision, or is this something that have to be sunk into the DAGBuilder?

Can't rule out transforms/analysis in IR...but currently, it doesn't look good. It seems more likely that we would defer to codegen (DAGCombiner or target-specific isel).

Are there any other uses of matchSelectPattern that could also be making a bogus decision?

I did an audit of trunk LLVM for SPF_MINNUM and related API, and this looks like the only potential misuse.

[uabelho]

Hi,

Would the rewrite be legal if the fcmp was "fast" or would that also lead to miscompiles?
So e.g. if we have

%cmp = fcmp fast ogt float %a, %b
%cond = select i1 %cmp, float %a, float %b

?

[spatel]

In D143106#4106570, @uabelho wrote:

Hi,

Would the rewrite be legal if the fcmp was "fast" or would that also lead to miscompiles?
So e.g. if we have

%cmp = fcmp fast ogt float %a, %b
%cond = select i1 %cmp, float %a, float %b

?

To make this transform sound, the inputs must be neither -0.0 nor NaN. But "nsz" doesn't guarantee that - it just means the sign of zero is "insignificant". That is already implied by the definition of fcmp, so "nsz" on fcmp is redundant/meaningless - "nsz" needs to be on the select. We have the opposite problem with "nnan" on the select. By definition, the select filters out a possible poison value (NaN), so a "nnan" on the select doesn't give us the required pre-condition that neither input is NaN.

That's why we have this strange proof:
https://alive2.llvm.org/ce/z/vjV9AC

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal)
       VT = TLI.getTypeToTransformTo(Ctx, VT);
 
     // If the vselect is legal, assume we want to leave this as a vector setcc +
     // vselect. Otherwise, if this is going to be scalarized, we want to see if
     // min/max is legal on the scalar type.
     bool UseScalarMinMax = VT.isVector() &&
       !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
 
+    // ValueTracking's select pattern matching does not account for -0.0,
+    // so we can't lower to FMINIMUM/FMAXIMUM because those nodes specify that
+    // -0.0 is less than +0.0.
     Value *LHS, *RHS;
     auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
     ISD::NodeType Opc = ISD::DELETED_NODE;
     switch (SPR.Flavor) {
     case SPF_UMAX:    Opc = ISD::UMAX; break;
     case SPF_UMIN:    Opc = ISD::UMIN; break;
     case SPF_SMAX:    Opc = ISD::SMAX; break;
     case SPF_SMIN:    Opc = ISD::SMIN; break;
     case SPF_FMINNUM:
       switch (SPR.NaNBehavior) {
       case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
-      case SPNB_RETURNS_NAN:   Opc = ISD::FMINIMUM; break;
+      case SPNB_RETURNS_NAN: break;
       case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
-      case SPNB_RETURNS_ANY: {
-        if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
+      case SPNB_RETURNS_ANY:
+        if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ||
+            (UseScalarMinMax &&
+             TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType())))
           Opc = ISD::FMINNUM;
-        else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
-          Opc = ISD::FMINIMUM;
-        else if (UseScalarMinMax)
-          Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
-            ISD::FMINNUM : ISD::FMINIMUM;
         break;
       }
-      }
       break;
     case SPF_FMAXNUM:
       switch (SPR.NaNBehavior) {
       case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
-      case SPNB_RETURNS_NAN:   Opc = ISD::FMAXIMUM; break;
+      case SPNB_RETURNS_NAN: break;
       case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
       case SPNB_RETURNS_ANY:
-
-        if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
+        if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ||
+            (UseScalarMinMax &&
+             TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType())))
           Opc = ISD::FMAXNUM;
-        else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
-          Opc = ISD::FMAXIMUM;
-        else if (UseScalarMinMax)
-          Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
-            ISD::FMAXNUM : ISD::FMAXIMUM;
         break;
       }
       break;
     case SPF_NABS:
       Negate = true;
       [[fallthrough]];
     case SPF_ABS:
       IsUnaryAbs = true;

llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll

 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
 
 define double @test_direct(float %in) {
 ; CHECK-LABEL: test_direct:
   %cmp = fcmp olt float %in, 0.000000e+00
   %val = select i1 %cmp, float 0.000000e+00, float %in
   %longer = fpext float %val to double
   ret double %longer
 
-; CHECK: fmax s
+; CHECK: fcmp
+; CHECK: fcsel
 }
 
 define double @test_cross(float %in) {
 ; CHECK-LABEL: test_cross:
   %cmp = fcmp ult float %in, 0.000000e+00
   %val = select i1 %cmp, float %in, float 0.000000e+00
   %longer = fpext float %val to double
   ret double %longer
 
-; CHECK: fmin s
+; CHECK: fcmp
+; CHECK: fcsel
 }
 
 ; Same as previous, but with ordered comparison;
 ; must become fminnm, not fmin.
 define double @test_cross_fail_nan(float %in) {
 ; CHECK-LABEL: test_cross_fail_nan:
   %cmp = fcmp olt float %in, 0.000000e+00
   %val = select i1 %cmp, float %in, float 0.000000e+00

llvm/test/CodeGen/AArch64/tbl-loops.ll

 ; CHECK-NEXT:    add x8, x1, x10, lsl #2
 ; CHECK-NEXT:    mov x14, x10
 ; CHECK-NEXT:    dup v0.4s, w15
 ; CHECK-NEXT:  .LBB0_4: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldp q1, q2, [x13, #-16]
 ; CHECK-NEXT:    subs x14, x14, #8
 ; CHECK-NEXT:    add x13, x13, #32
-; CHECK-NEXT:    fcmlt v3.4s, v1.4s, #0.0
-; CHECK-NEXT:    fmin v1.4s, v1.4s, v0.4s
-; CHECK-NEXT:    fcmlt v4.4s, v2.4s, #0.0
-; CHECK-NEXT:    fmin v2.4s, v2.4s, v0.4s
-; CHECK-NEXT:    bic v1.16b, v1.16b, v3.16b
+; CHECK-NEXT:    fcmgt v3.4s, v1.4s, v0.4s
+; CHECK-NEXT:    fcmlt v5.4s, v1.4s, #0.0
+; CHECK-NEXT:    fcmgt v4.4s, v2.4s, v0.4s
+; CHECK-NEXT:    fcmlt v6.4s, v2.4s, #0.0
+; CHECK-NEXT:    bit v1.16b, v0.16b, v3.16b
+; CHECK-NEXT:    bit v2.16b, v0.16b, v4.16b
+; CHECK-NEXT:    bic v1.16b, v1.16b, v5.16b
 ; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
-; CHECK-NEXT:    bic v2.16b, v2.16b, v4.16b
+; CHECK-NEXT:    bic v2.16b, v2.16b, v6.16b
 ; CHECK-NEXT:    fcvtzs v2.4s, v2.4s
 ; CHECK-NEXT:    xtn v1.4h, v1.4s
 ; CHECK-NEXT:    xtn v2.4h, v2.4s
 ; CHECK-NEXT:    xtn v1.8b, v1.8h
 ; CHECK-NEXT:    xtn v2.8b, v2.8h
 ; CHECK-NEXT:    mov v1.s[1], v2.s[0]
 ; CHECK-NEXT:    stur d1, [x12, #-4]
 ; CHECK-NEXT:    add x12, x12, #8
 ; CHECK-NEXT:    b.ne .LBB0_4
 ; CHECK-NEXT:  // %bb.5: // %middle.block
 ; CHECK-NEXT:    cmp x11, x10
 ; CHECK-NEXT:    b.eq .LBB0_8
 ; CHECK-NEXT:  .LBB0_6: // %for.body.preheader1
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    sub w10, w2, w10
 ; CHECK-NEXT:    mov w11, #1132396544
 ; CHECK-NEXT:  .LBB0_7: // %for.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldr s1, [x8], #4
 ; CHECK-NEXT:    fmov s2, w11
+; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fcsel s2, s2, s1, gt
 ; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fmin s2, s1, s2
 ; CHECK-NEXT:    fcsel s1, s0, s2, mi
 ; CHECK-NEXT:    subs w10, w10, #1
 ; CHECK-NEXT:    fcvtzs w12, s1
 ; CHECK-NEXT:    strb w12, [x9], #1
 ; CHECK-NEXT:    b.ne .LBB0_7
 ; CHECK-NEXT:  .LBB0_8: // %for.cond.cleanup
 ; CHECK-NEXT:    ret
 entry:

 ; CHECK-NEXT:  .LBB1_5: // %for.body.preheader1
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    sub w10, w2, w10
 ; CHECK-NEXT:    mov w11, #1132396544
 ; CHECK-NEXT:  .LBB1_6: // %for.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldp s2, s3, [x8], #8
 ; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fmin s4, s2, s1
+; CHECK-NEXT:    fcmp s2, s1
+; CHECK-NEXT:    fcsel s4, s1, s2, gt
 ; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fmin s1, s3, s1
 ; CHECK-NEXT:    fcsel s2, s0, s4, mi
+; CHECK-NEXT:    fcmp s3, s1
+; CHECK-NEXT:    fcsel s1, s1, s3, gt
 ; CHECK-NEXT:    fcmp s3, #0.0
+; CHECK-NEXT:    fcvtzs w12, s2
 ; CHECK-NEXT:    fcsel s1, s0, s1, mi
+; CHECK-NEXT:    strb w12, [x9]
 ; CHECK-NEXT:    subs w10, w10, #1
-; CHECK-NEXT:    fcvtzs w12, s2
 ; CHECK-NEXT:    fcvtzs w13, s1
-; CHECK-NEXT:    strb w12, [x9]
 ; CHECK-NEXT:    strb w13, [x9, #1]
 ; CHECK-NEXT:    add x9, x9, #2
 ; CHECK-NEXT:    b.ne .LBB1_6
 ; CHECK-NEXT:  .LBB1_7: // %for.cond.cleanup
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_8: // %vector.ph
 ; CHECK-NEXT:    add x11, x8, #1
 ; CHECK-NEXT:    mov w13, #1132396544
 ; CHECK-NEXT:    and x10, x11, #0x1fffffffc
 ; CHECK-NEXT:    mov x12, x10
 ; CHECK-NEXT:    add x8, x1, x10, lsl #3
 ; CHECK-NEXT:    add x9, x0, x10, lsl #1
 ; CHECK-NEXT:    dup v0.4s, w13
 ; CHECK-NEXT:  .LBB1_9: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ld2 { v1.4s, v2.4s }, [x1], #32
-; CHECK-NEXT:    fcmlt v3.4s, v1.4s, #0.0
+; CHECK-NEXT:    fcmgt v3.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    subs x12, x12, #4
-; CHECK-NEXT:    fmin v4.4s, v1.4s, v0.4s
-; CHECK-NEXT:    fcmlt v5.4s, v2.4s, #0.0
-; CHECK-NEXT:    fmin v1.4s, v2.4s, v0.4s
-; CHECK-NEXT:    bic v2.16b, v4.16b, v3.16b
+; CHECK-NEXT:    fcmgt v4.4s, v2.4s, v0.4s
+; CHECK-NEXT:    fcmlt v5.4s, v1.4s, #0.0
+; CHECK-NEXT:    bsl v3.16b, v0.16b, v1.16b
+; CHECK-NEXT:    bsl v4.16b, v0.16b, v2.16b
+; CHECK-NEXT:    fcmlt v1.4s, v2.4s, #0.0
+; CHECK-NEXT:    bic v2.16b, v3.16b, v5.16b
 ; CHECK-NEXT:    fcvtzs v2.4s, v2.4s
-; CHECK-NEXT:    bic v1.16b, v1.16b, v5.16b
+; CHECK-NEXT:    bic v1.16b, v4.16b, v1.16b
 ; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
 ; CHECK-NEXT:    xtn v2.4h, v2.4s
 ; CHECK-NEXT:    xtn v1.4h, v1.4s
 ; CHECK-NEXT:    trn1 v1.8b, v2.8b, v1.8b
 ; CHECK-NEXT:    str d1, [x0], #8
 ; CHECK-NEXT:    b.ne .LBB1_9
 ; CHECK-NEXT:  // %bb.10: // %middle.block
 ; CHECK-NEXT:    cmp x11, x10

 ; CHECK-NEXT:  .LBB2_5: // %for.body.preheader1
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    sub w10, w2, w10
 ; CHECK-NEXT:    mov w11, #1132396544
 ; CHECK-NEXT:  .LBB2_6: // %for.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldp s2, s3, [x8]
 ; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fmin s4, s2, s1
+; CHECK-NEXT:    fcmp s2, s1
+; CHECK-NEXT:    fcsel s4, s1, s2, gt
 ; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    ldr s2, [x8, #8]
-; CHECK-NEXT:    fmin s5, s3, s1
+; CHECK-NEXT:    fcsel s2, s0, s4, mi
+; CHECK-NEXT:    fcmp s3, s1
+; CHECK-NEXT:    fcsel s4, s1, s3, gt
+; CHECK-NEXT:    fcmp s3, #0.0
+; CHECK-NEXT:    ldr s3, [x8, #8]
+; CHECK-NEXT:    fcvtzs w12, s2
 ; CHECK-NEXT:    add x8, x8, #12
 ; CHECK-NEXT:    fcsel s4, s0, s4, mi
+; CHECK-NEXT:    fcmp s3, s1
+; CHECK-NEXT:    strb w12, [x9]
+; CHECK-NEXT:    fcsel s1, s1, s3, gt
 ; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    fmin s1, s2, s1
-; CHECK-NEXT:    fcsel s3, s0, s5, mi
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvtzs w12, s4
+; CHECK-NEXT:    fcvtzs w13, s4
 ; CHECK-NEXT:    fcsel s1, s0, s1, mi
+; CHECK-NEXT:    strb w13, [x9, #1]
 ; CHECK-NEXT:    subs w10, w10, #1
-; CHECK-NEXT:    fcvtzs w13, s3
-; CHECK-NEXT:    strb w12, [x9]
 ; CHECK-NEXT:    fcvtzs w14, s1
-; CHECK-NEXT:    strb w13, [x9, #1]
 ; CHECK-NEXT:    strb w14, [x9, #2]
 ; CHECK-NEXT:    add x9, x9, #3
 ; CHECK-NEXT:    b.ne .LBB2_6
 ; CHECK-NEXT:  .LBB2_7: // %for.cond.cleanup
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB2_8: // %vector.ph
 ; CHECK-NEXT:    add x11, x8, #1
 ; CHECK-NEXT:    adrp x12, .LCPI2_0
 ; CHECK-NEXT:    and x10, x11, #0x1fffffffc
 ; CHECK-NEXT:    mov w13, #1132396544
 ; CHECK-NEXT:    add x8, x10, x10, lsl #1
 ; CHECK-NEXT:    ldr q0, [x12, :lo12:.LCPI2_0]
 ; CHECK-NEXT:    add x9, x0, x8
 ; CHECK-NEXT:    mov x12, x10
 ; CHECK-NEXT:    add x8, x1, x8, lsl #2
 ; CHECK-NEXT:    dup v1.4s, w13
 ; CHECK-NEXT:  .LBB2_9: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ld3 { v2.4s, v3.4s, v4.4s }, [x1], #48
-; CHECK-NEXT:    fcmlt v5.4s, v2.4s, #0.0
+; CHECK-NEXT:    fcmgt v5.4s, v2.4s, v1.4s
 ; CHECK-NEXT:    add x13, x0, #8
-; CHECK-NEXT:    fmin v6.4s, v2.4s, v1.4s
+; CHECK-NEXT:    fcmgt v7.4s, v3.4s, v1.4s
 ; CHECK-NEXT:    subs x12, x12, #4
-; CHECK-NEXT:    fcmlt v7.4s, v3.4s, #0.0
-; CHECK-NEXT:    fmin v16.4s, v3.4s, v1.4s
-; CHECK-NEXT:    fmin v2.4s, v4.4s, v1.4s
-; CHECK-NEXT:    bic v5.16b, v6.16b, v5.16b
+; CHECK-NEXT:    fcmgt v17.4s, v4.4s, v1.4s
+; CHECK-NEXT:    fcmlt v6.4s, v2.4s, #0.0
+; CHECK-NEXT:    bsl v5.16b, v1.16b, v2.16b
+; CHECK-NEXT:    fcmlt v16.4s, v3.4s, #0.0
+; CHECK-NEXT:    bsl v7.16b, v1.16b, v3.16b
+; CHECK-NEXT:    mov v2.16b, v17.16b
+; CHECK-NEXT:    bic v5.16b, v5.16b, v6.16b
 ; CHECK-NEXT:    fcmlt v6.4s, v4.4s, #0.0
-; CHECK-NEXT:    bic v3.16b, v16.16b, v7.16b
+; CHECK-NEXT:    bsl v2.16b, v1.16b, v4.16b
+; CHECK-NEXT:    bic v3.16b, v7.16b, v16.16b
 ; CHECK-NEXT:    fcvtzs v4.4s, v5.4s
 ; CHECK-NEXT:    fcvtzs v3.4s, v3.4s
 ; CHECK-NEXT:    bic v2.16b, v2.16b, v6.16b
 ; CHECK-NEXT:    fcvtzs v2.4s, v2.4s
 ; CHECK-NEXT:    xtn v4.4h, v4.4s
 ; CHECK-NEXT:    xtn v5.4h, v3.4s
 ; CHECK-NEXT:    xtn v6.4h, v2.4s
 ; CHECK-NEXT:    tbl v2.16b, { v4.16b, v5.16b, v6.16b }, v0.16b

 ; CHECK-NEXT:  .LBB3_5: // %for.body.preheader1
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    sub w10, w2, w10
 ; CHECK-NEXT:    mov w11, #1132396544
 ; CHECK-NEXT:  .LBB3_6: // %for.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldp s2, s3, [x8]
 ; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fmin s4, s2, s1
+; CHECK-NEXT:    fcmp s2, s1
+; CHECK-NEXT:    fcsel s4, s1, s2, gt
 ; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fmin s2, s3, s1
-; CHECK-NEXT:    fcsel s4, s0, s4, mi
+; CHECK-NEXT:    fcsel s2, s0, s4, mi
+; CHECK-NEXT:    fcmp s3, s1
+; CHECK-NEXT:    fcsel s4, s1, s3, gt
 ; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    ldp s5, s3, [x8, #8]
+; CHECK-NEXT:    ldp s3, s5, [x8, #8]
+; CHECK-NEXT:    fcvtzs w12, s2
 ; CHECK-NEXT:    add x8, x8, #16
-; CHECK-NEXT:    fcsel s2, s0, s2, mi
-; CHECK-NEXT:    fcvtzs w12, s4
-; CHECK-NEXT:    fmin s6, s5, s1
-; CHECK-NEXT:    fcmp s5, #0.0
-; CHECK-NEXT:    fmin s1, s3, s1
-; CHECK-NEXT:    fcvtzs w13, s2
+; CHECK-NEXT:    fcsel s4, s0, s4, mi
+; CHECK-NEXT:    fcmp s3, s1
 ; CHECK-NEXT:    strb w12, [x9]
-; CHECK-NEXT:    fcsel s5, s0, s6, mi
+; CHECK-NEXT:    fcsel s6, s1, s3, gt
 ; CHECK-NEXT:    fcmp s3, #0.0
+; CHECK-NEXT:    fcvtzs w13, s4
+; CHECK-NEXT:    fcsel s3, s0, s6, mi
+; CHECK-NEXT:    fcmp s5, s1
 ; CHECK-NEXT:    strb w13, [x9, #1]
+; CHECK-NEXT:    fcsel s1, s1, s5, gt
+; CHECK-NEXT:    fcmp s5, #0.0
+; CHECK-NEXT:    fcvtzs w14, s3
 ; CHECK-NEXT:    fcsel s1, s0, s1, mi
+; CHECK-NEXT:    strb w14, [x9, #2]
 ; CHECK-NEXT:    subs w10, w10, #1
-; CHECK-NEXT:    fcvtzs w14, s5
 ; CHECK-NEXT:    fcvtzs w12, s1
-; CHECK-NEXT:    strb w14, [x9, #2]
 ; CHECK-NEXT:    strb w12, [x9, #3]
 ; CHECK-NEXT:    add x9, x9, #4
 ; CHECK-NEXT:    b.ne .LBB3_6
 ; CHECK-NEXT:  .LBB3_7: // %for.cond.cleanup
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB3_8: // %vector.ph
 ; CHECK-NEXT:    add x11, x8, #1
 ; CHECK-NEXT:    adrp x12, .LCPI3_0
 ; CHECK-NEXT:    and x10, x11, #0x1fffffffc
 ; CHECK-NEXT:    mov w13, #1132396544
 ; CHECK-NEXT:    add x8, x1, x10, lsl #4
 ; CHECK-NEXT:    add x9, x0, x10, lsl #2
 ; CHECK-NEXT:    ldr q0, [x12, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    mov x12, x10
 ; CHECK-NEXT:    dup v1.4s, w13
 ; CHECK-NEXT:  .LBB3_9: // %vector.body
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x1], #64
-; CHECK-NEXT:    fcmlt v6.4s, v2.4s, #0.0
+; CHECK-NEXT:    fcmgt v6.4s, v2.4s, v1.4s
 ; CHECK-NEXT:    subs x12, x12, #4
-; CHECK-NEXT:    fmin v7.4s, v2.4s, v1.4s
-; CHECK-NEXT:    fcmlt v16.4s, v3.4s, #0.0
-; CHECK-NEXT:    fmin v17.4s, v3.4s, v1.4s
-; CHECK-NEXT:    fmin v18.4s, v4.4s, v1.4s
-; CHECK-NEXT:    bic v6.16b, v7.16b, v6.16b
-; CHECK-NEXT:    fcmlt v7.4s, v4.4s, #0.0
-; CHECK-NEXT:    bic v16.16b, v17.16b, v16.16b
+; CHECK-NEXT:    fcmlt v7.4s, v2.4s, #0.0
+; CHECK-NEXT:    fcmgt v16.4s, v3.4s, v1.4s
+; CHECK-NEXT:    fcmgt v19.4s, v4.4s, v1.4s
+; CHECK-NEXT:    bsl v6.16b, v1.16b, v2.16b
+; CHECK-NEXT:    fcmlt v17.4s, v3.4s, #0.0
+; CHECK-NEXT:    bsl v16.16b, v1.16b, v3.16b
+; CHECK-NEXT:    fcmlt v18.4s, v4.4s, #0.0
+; CHECK-NEXT:    bic v6.16b, v6.16b, v7.16b
+; CHECK-NEXT:    fcmgt v7.4s, v5.4s, v1.4s
+; CHECK-NEXT:    bsl v19.16b, v1.16b, v4.16b
+; CHECK-NEXT:    bic v16.16b, v16.16b, v17.16b
 ; CHECK-NEXT:    fcmlt v17.4s, v5.4s, #0.0
-; CHECK-NEXT:    fmin v2.4s, v5.4s, v1.4s
+; CHECK-NEXT:    mov v2.16b, v7.16b
+; CHECK-NEXT:    bsl v2.16b, v1.16b, v5.16b
 ; CHECK-NEXT:    fcvtzs v4.4s, v6.4s
-; CHECK-NEXT:    bic v3.16b, v18.16b, v7.16b
+; CHECK-NEXT:    bic v3.16b, v19.16b, v18.16b
 ; CHECK-NEXT:    fcvtzs v5.4s, v16.4s
 ; CHECK-NEXT:    fcvtzs v3.4s, v3.4s
 ; CHECK-NEXT:    bic v2.16b, v2.16b, v17.16b
 ; CHECK-NEXT:    fcvtzs v2.4s, v2.4s
 ; CHECK-NEXT:    xtn v16.4h, v4.4s
 ; CHECK-NEXT:    xtn v17.4h, v5.4s
 ; CHECK-NEXT:    xtn v18.4h, v3.4s
 ; CHECK-NEXT:    xtn v19.4h, v2.4s

llvm/test/CodeGen/ARM/neon_minmax.ll

 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=-neon %s -o -
 
 define float @fmin_ole(float %x) nounwind {
 ;CHECK-LABEL: fmin_ole:
-;CHECK: vmin.f32
+;CHECK-NOT: vmin.f32
   %cond = fcmp ole float 1.0, %x
   %min1 = select i1 %cond, float 1.0, float %x
   ret float %min1
 }
 
 define float @fmin_ole_zero(float %x) nounwind {
 ;CHECK-LABEL: fmin_ole_zero:
 ;CHECK-NOT: vmin.f32
   %cond = fcmp ole float 0.0, %x
   %min1 = select i1 %cond, float 0.0, float %x
   ret float %min1
 }
 
 define float @fmin_ult(float %x) nounwind {
 ;CHECK-LABEL: fmin_ult:
-;CHECK: vmin.f32
+;CHECK-NOT: vmin.f32
   %cond = fcmp ult float %x, 1.0
   %min1 = select i1 %cond, float %x, float 1.0
   ret float %min1
 }
 
 define float @fmax_ogt(float %x) nounwind {
 ;CHECK-LABEL: fmax_ogt:
-;CHECK: vmax.f32
+;CHECK-NOT: vmax.f32
   %cond = fcmp ogt float 1.0, %x
   %max1 = select i1 %cond, float 1.0, float %x
   ret float %max1
 }
 
 define float @fmax_uge(float %x) nounwind {
 ;CHECK-LABEL: fmax_uge:
-;CHECK: vmax.f32
+;CHECK-NOT: vmax.f32
   %cond = fcmp uge float %x, 1.0
   %max1 = select i1 %cond, float %x, float 1.0
   ret float %max1
 }
 
 define float @fmax_uge_zero(float %x) nounwind {
 ;CHECK-LABEL: fmax_uge_zero:
 ;CHECK-NOT: vmax.f32
   %cond = fcmp uge float %x, 0.0
   %max1 = select i1 %cond, float %x, float 0.0
   ret float %max1
 }
 
 define float @fmax_olt_reverse(float %x) nounwind {
 ;CHECK-LABEL: fmax_olt_reverse:
-;CHECK: vmax.f32
+;CHECK-NOT: vmax.f32
   %cond = fcmp olt float %x, 1.0
   %max1 = select i1 %cond, float 1.0, float %x
   ret float %max1
 }
 
 define float @fmax_ule_reverse(float %x) nounwind {
 ;CHECK-LABEL: fmax_ule_reverse:
-;CHECK: vmax.f32
+;CHECK-NOT: vmax.f32
   %cond = fcmp ult float 1.0, %x
   %max1 = select i1 %cond, float %x, float 1.0
   ret float %max1
 }
 
 define float @fmin_oge_reverse(float %x) nounwind {
 ;CHECK-LABEL: fmin_oge_reverse:
-;CHECK: vmin.f32
+;CHECK-NOT: vmin.f32
   %cond = fcmp oge float %x, 1.0
   %min1 = select i1 %cond, float 1.0, float %x
   ret float %min1
 }
 
 define float @fmin_ugt_reverse(float %x) nounwind {
 ;CHECK-LABEL: fmin_ugt_reverse:
-;CHECK: vmin.f32
+;CHECK-NOT: vmin.f32
   %cond = fcmp ugt float 1.0, %x
   %min1 = select i1 %cond, float %x, float 1.0
   ret float %min1
 }

llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll

-; RUN: llc < %s -march=nvptx | FileCheck %s --check-prefixes=CHECK,CHECK-NONAN
-; RUN: llc < %s -march=nvptx -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK,CHECK-NAN
+; RUN: llc < %s -march=nvptx | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -march=nvptx -mcpu=sm_80 | FileCheck %s --check-prefixes=CHECK
 ; RUN: %if ptxas %{ llc < %s -march=nvptx | %ptxas-verify %}
 ; RUN: %if ptxas-11.0 %{ llc < %s -march=nvptx -mcpu=sm_80 | %ptxas-verify -arch=sm_80 %}
 
 ; ---- minimum ----
 
 ; CHECK-LABEL: minimum_half
 define half @minimum_half(half %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.b16
-  ; CHECK-NAN: min.NaN.f16
+  ; CHECK: setp
+  ; CHECK: selp.b16
   %p = fcmp ult half %a, 0.0
   %x = select i1 %p, half %a, half 0.0
   ret half %x
 }
 
 ; CHECK-LABEL: minimum_float
 define float @minimum_float(float %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.f32
-  ; CHECK-NAN: min.NaN.f32
+  ; CHECK: setp
+  ; CHECK: selp.f32
   %p = fcmp ult float %a, 0.0
   %x = select i1 %p, float %a, float 0.0
   ret float %x
 }
 
 ; CHECK-LABEL: minimum_double
 define double @minimum_double(double %a) #0 {
   ; CHECK: setp
   ; CHECK: selp.f64
   %p = fcmp ult double %a, 0.0
   %x = select i1 %p, double %a, double 0.0
   ret double %x
 }
 
 ; CHECK-LABEL: minimum_v2half
 define <2 x half> @minimum_v2half(<2 x half> %a) #0 {
-  ; CHECK-NONAN-DAG: setp
-  ; CHECK-NONAN-DAG: setp
-  ; CHECK-NONAN-DAG: selp.b16
-  ; CHECK-NONAN-DAG: selp.b16
-  ; CHECK-NAN: min.NaN.f16x2
+  ; CHECK-DAG: setp
+  ; CHECK-DAG: selp.b16
+  ; CHECK-DAG: selp.b16
   %p = fcmp ult <2 x half> %a, zeroinitializer
   %x = select <2 x i1> %p, <2 x half> %a, <2 x half> zeroinitializer
   ret <2 x half> %x
 }
 
 ; ---- maximum ----
 
 ; CHECK-LABEL: maximum_half
 define half @maximum_half(half %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.b16
-  ; CHECK-NAN: max.NaN.f16
+  ; CHECK: setp
+  ; CHECK: selp.b16
   %p = fcmp ugt half %a, 0.0
   %x = select i1 %p, half %a, half 0.0
   ret half %x
 }
 
 ; CHECK-LABEL: maximum_float
 define float @maximum_float(float %a) #0 {
-  ; CHECK-NONAN: setp
-  ; CHECK-NONAN: selp.f32
-  ; CHECK-NAN: max.NaN.f32
+  ; CHECK: setp
+  ; CHECK: selp.f32
   %p = fcmp ugt float %a, 0.0
   %x = select i1 %p, float %a, float 0.0
   ret float %x
 }
 
 ; CHECK-LABEL: maximum_double
 define double @maximum_double(double %a) #0 {
   ; CHECK: setp
   ; CHECK: selp.f64
   %p = fcmp ugt double %a, 0.0
   %x = select i1 %p, double %a, double 0.0
   ret double %x
 }
 
 ; CHECK-LABEL: maximum_v2half
 define <2 x half> @maximum_v2half(<2 x half> %a) #0 {
-  ; CHECK-NONAN-DAG: setp
-  ; CHECK-NONAN-DAG: setp
-  ; CHECK-NONAN-DAG: selp.b16
-  ; CHECK-NONAN-DAG: selp.b16
-  ; CHECK-NAN: max.NaN.f16x2
+  ; CHECK-DAG: setp
+  ; CHECK-DAG: selp.b16
+  ; CHECK-DAG: selp.b16
   %p = fcmp ugt <2 x half> %a, zeroinitializer
   %x = select <2 x i1> %p, <2 x half> %a, <2 x half> zeroinitializer
   ret <2 x half> %x
 }

llvm/test/CodeGen/SystemZ/vec-max-05.ll

; CHECK: br %r14
   %cmp = fcmp ogt double %val, 0.0
   %ret = select i1 %cmp, double %val, double 0.0
   ret double %ret
 }
 
 ; Test a f64 constant compare/select resulting in maximum.
 define double @f5(double %dummy, double %val) {
 ; CHECK-LABEL: f5:
-; CHECK: lzdr [[REG:%f[0-9]+]]
-; CHECK: wfmaxdb %f0, %f2, [[REG]], 1
+; CHECK: ltdbr  %f0, %f2
 ; CHECK: br %r14
   %cmp = fcmp ugt double %val, 0.0
   %ret = select i1 %cmp, double %val, double 0.0
   ret double %ret
 }
 
 ; Test the v2f64 maxnum intrinsic.
 define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
; CHECK: br %r14
   %cmp = fcmp ogt float %val, 0.0
   %ret = select i1 %cmp, float %val, float 0.0
   ret float %ret
 }
 
 ; Test a f32 constant compare/select resulting in maximum.
 define float @f15(float %dummy, float %val) {
 ; CHECK-LABEL: f15:
-; CHECK: lzer [[REG:%f[0-9]+]]
-; CHECK: wfmaxsb %f0, %f2, [[REG]], 1
+; CHECK: ltebr  %f1, %f2
+; CHECK: ldr  %f0, %f2
 ; CHECK: br %r14
   %cmp = fcmp ugt float %val, 0.0
   %ret = select i1 %cmp, float %val, float 0.0
   ret float %ret
 }
 
 ; Test the v4f32 maxnum intrinsic.
 define <4 x float> @f16(<4 x float> %dummy, <4 x float> %val1,
; CHECK: br %r14
   ret void
 }
 
 ; Test a f128 constant compare/select resulting in maximum.
 define void @f25(ptr %ptr, ptr %dst) {
 ; CHECK-LABEL: f25:
 ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
 ; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
+; CHECK: wfcxb [[REG1]], [[REG2]]
 ; CHECK: vst [[RES]], 0(%r3)
 ; CHECK: br %r14
   %val = load fp128, ptr %ptr
   %cmp = fcmp ugt fp128 %val, 0xL00000000000000000000000000000000
   %res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
   store fp128 %res, ptr %dst
   ret void
 }
 

llvm/test/CodeGen/SystemZ/vec-max-min-zerosplat.ll

; CHECK-NEXT: br %r14
   %cmp = fcmp olt <4 x float> %val,  zeroinitializer
   %ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
   ret <4 x float> %ret
 }
 
 define <2 x double> @f5(<2 x double> %val) {
 ; CHECK-LABEL: f5:
 ; CHECK: vgbm %v0, 0
-; CHECK-NEXT: vfmaxdb %v24, %v24, %v0, 1
+; CHECK-NEXT: vfchedb %v1, %v0, %v24
+; CHECK-NEXT: vsel  %v24, %v0, %v24, %v1
 ; CHECK-NEXT: br %r14
   %cmp = fcmp ugt <2 x double> %val,  zeroinitializer
   %ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
   ret <2 x double> %ret
 }
 
 define <2 x double> @f6(<2 x double> %val) {
 ; CHECK-LABEL: f6:
 ; CHECK: vgbm %v0, 0
-; CHECK-NEXT: vfmindb %v24, %v24, %v0, 1
+; CHECK-NEXT: vfchedb %v1, %v24, %v0
+; CHECK-NEXT: vsel  %v24, %v0, %v24, %v1
 ; CHECK-NEXT: br %r14
   %cmp = fcmp ult <2 x double> %val,  zeroinitializer
   %ret = select <2 x i1> %cmp, <2 x double> %val, <2 x double> zeroinitializer
   ret <2 x double> %ret
 }
 
 define <4 x float> @f7(<4 x float> %val) {
 ; CHECK-LABEL: f7:
 ; CHECK: vgbm %v0, 0
-; CHECK-NEXT: vfmaxsb %v24, %v24, %v0, 1
+; CHECK-NEXT: vfchesb %v1, %v0, %v24
+; CHECK-NEXT: vsel  %v24, %v0, %v24, %v1
 ; CHECK-NEXT: br %r14
   %cmp = fcmp ugt <4 x float> %val,  zeroinitializer
   %ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
   ret <4 x float> %ret
 }
 
 define <4 x float> @f8(<4 x float> %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: vgbm %v0, 0
-; CHECK-NEXT: vfminsb %v24, %v24, %v0, 1
+; CHECK-NEXT: vfchesb %v1, %v24, %v0
+; CHECK-NEXT: vsel  %v24, %v0, %v24, %v1
 ; CHECK-NEXT: br %r14
   %cmp = fcmp ult <4 x float> %val,  zeroinitializer
   %ret = select <4 x i1> %cmp, <4 x float> %val, <4 x float> zeroinitializer
   ret <4 x float> %ret
 }

llvm/test/CodeGen/SystemZ/vec-min-05.ll

; CHECK: br %r14
   %cmp = fcmp olt double %val, 0.0
   %ret = select i1 %cmp, double %val, double 0.0
   ret double %ret
 }
 
 ; Test a f64 constant compare/select resulting in minimum.
 define double @f5(double %dummy, double %val) {
 ; CHECK-LABEL: f5:
-; CHECK: lzdr [[REG:%f[0-9]+]]
-; CHECK: wfmindb %f0, %f2, [[REG]], 1
-; CHECK: br %r14
+; CHECK: ltdbr  %f0, %f2
+; CHECK: bnher  %r14
   %cmp = fcmp ult double %val, 0.0
   %ret = select i1 %cmp, double %val, double 0.0
   ret double %ret
 }
 
 ; Test the v2f64 minnum intrinsic.
 define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
                         <2 x double> %val2) {
; CHECK: br %r14
   %cmp = fcmp olt float %val, 0.0
   %ret = select i1 %cmp, float %val, float 0.0
   ret float %ret
 }
 
 ; Test a f32 constant compare/select resulting in minimum.
 define float @f15(float %dummy, float %val) {
 ; CHECK-LABEL: f15:
-; CHECK: lzer [[REG:%f[0-9]+]]
-; CHECK: wfminsb %f0, %f2, [[REG]], 1
-; CHECK: br %r14
+; CHECK: ltebr  %f1, %f2
+; CHECK: ldr  %f0, %f2
+; CHECK: bnher  %r14
   %cmp = fcmp ult float %val, 0.0
   %ret = select i1 %cmp, float %val, float 0.0
   ret float %ret
 }
 
 ; Test the v4f32 minnum intrinsic.
 define <4 x float> @f16(<4 x float> %dummy, <4 x float> %val1,
                         <4 x float> %val2) {
; CHECK: br %r14
   ret void
 }
 
 ; Test a f128 constant compare/select resulting in minimum.
 define void @f25(ptr %ptr, ptr %dst) {
 ; CHECK-LABEL: f25:
 ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
 ; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
-; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
+; CHECK: wfcxb [[REG1]], [[REG2]]
 ; CHECK: vst [[RES]], 0(%r3)
 ; CHECK: br %r14
   %val = load fp128, ptr %ptr
   %cmp = fcmp ult fp128 %val, 0xL00000000000000000000000000000000
   %res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
   store fp128 %res, ptr %dst
   ret void
 }
 

llvm/test/CodeGen/WebAssembly/f32.ll

 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get $push1=, 0
 ; CHECK-NEXT:    f32.nearest $push0=, $pop1
 ; CHECK-NEXT:    return $pop0
   %a = call float @llvm.rint.f32(float %x)
   ret float %a
 }
 
+; This is not "minimum" because a -0.0 input returns +0.0.
+
 define float @fmin32(float %x) {
 ; CHECK-LABEL: fmin32:
 ; CHECK:         .functype fmin32 (f32) -> (f32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    local.get $push2=, 0
 ; CHECK-NEXT:    f32.const $push0=, 0x0p0
-; CHECK-NEXT:    f32.min $push1=, $pop2, $pop0
-; CHECK-NEXT:    return $pop1
+; CHECK-NEXT:    local.get $push5=, 0
+; CHECK-NEXT:    local.get $push4=, 0
+; CHECK-NEXT:    f32.const $push3=, 0x0p0
+; CHECK-NEXT:    f32.ge $push1=, $pop4, $pop3
+; CHECK-NEXT:    f32.select $push2=, $pop0, $pop5, $pop1
+; CHECK-NEXT:    return $pop2
   %a = fcmp ult float %x, 0.0
   %b = select i1 %a, float %x, float 0.0
   ret float %b
 }
 
+; This is not "maximum" because a -0.0 input returns +0.0.
+
 define float @fmax32(float %x) {
 ; CHECK-LABEL: fmax32:
 ; CHECK:         .functype fmax32 (f32) -> (f32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    local.get $push2=, 0
 ; CHECK-NEXT:    f32.const $push0=, 0x0p0
-; CHECK-NEXT:    f32.max $push1=, $pop2, $pop0
-; CHECK-NEXT:    return $pop1
+; CHECK-NEXT:    local.get $push5=, 0
+; CHECK-NEXT:    local.get $push4=, 0
+; CHECK-NEXT:    f32.const $push3=, 0x0p0
+; CHECK-NEXT:    f32.le $push1=, $pop4, $pop3
+; CHECK-NEXT:    f32.select $push2=, $pop0, $pop5, $pop1
+; CHECK-NEXT:    return $pop2
   %a = fcmp ugt float %x, 0.0
   %b = select i1 %a, float %x, float 0.0
   ret float %b
 }
 
 declare float @llvm.minimum.f32(float, float)
 define float @fmin32_intrinsic(float %x, float %y) {
 ; CHECK-LABEL: fmin32_intrinsic:

llvm/test/CodeGen/WebAssembly/f64.ll

 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get $push1=, 0
 ; CHECK-NEXT:    f64.nearest $push0=, $pop1
 ; CHECK-NEXT:    return $pop0
   %a = call double @llvm.rint.f64(double %x)
   ret double %a
 }
 
+; This is not "minimum" because a -0.0 input returns +0.0.
+
 define double @fmin64(double %x) {
 ; CHECK-LABEL: fmin64:
 ; CHECK:         .functype fmin64 (f64) -> (f64)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    local.get $push2=, 0
 ; CHECK-NEXT:    f64.const $push0=, 0x0p0
-; CHECK-NEXT:    f64.min $push1=, $pop2, $pop0
-; CHECK-NEXT:    return $pop1
+; CHECK-NEXT:    local.get $push5=, 0
+; CHECK-NEXT:    local.get $push4=, 0
+; CHECK-NEXT:    f64.const $push3=, 0x0p0
+; CHECK-NEXT:    f64.ge $push1=, $pop4, $pop3
+; CHECK-NEXT:    f64.select $push2=, $pop0, $pop5, $pop1
+; CHECK-NEXT:    return $pop2
   %a = fcmp ult double %x, 0.0
   %b = select i1 %a, double %x, double 0.0
   ret double %b
 }
 
+; This is not "maximum" because a -0.0 input returns +0.0.
+
 define double @fmax64(double %x) {
 ; CHECK-LABEL: fmax64:
 ; CHECK:         .functype fmax64 (f64) -> (f64)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    local.get $push2=, 0
 ; CHECK-NEXT:    f64.const $push0=, 0x0p0
-; CHECK-NEXT:    f64.max $push1=, $pop2, $pop0
-; CHECK-NEXT:    return $pop1
+; CHECK-NEXT:    local.get $push5=, 0
+; CHECK-NEXT:    local.get $push4=, 0
+; CHECK-NEXT:    f64.const $push3=, 0x0p0
+; CHECK-NEXT:    f64.le $push1=, $pop4, $pop3
+; CHECK-NEXT:    f64.select $push2=, $pop0, $pop5, $pop1
+; CHECK-NEXT:    return $pop2
   %a = fcmp ugt double %x, 0.0
   %b = select i1 %a, double %x, double 0.0
   ret double %b
 }
 
 declare double @llvm.minimum.f64(double, double)
 define double @fmin64_intrinsic(double %x, double %y) {
 ; CHECK-LABEL: fmin64_intrinsic:

llvm/test/CodeGen/WebAssembly/simd-arith.ll

; NO-SIMD128-FAST-NEXT:    return
   %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
   ret <4 x float> %a
 }
 
 define <4 x float> @min_unordered_v4f32(<4 x float> %x) {
 ; SIMD128-LABEL: min_unordered_v4f32:
 ; SIMD128:         .functype min_unordered_v4f32 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f32x4.min $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f32x4.gt $push0=, $0, $1
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: min_unordered_v4f32:
 ; SIMD128-FAST:         .functype min_unordered_v4f32 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f32x4.min $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f32x4.gt $push1=, $0, $1
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: min_unordered_v4f32:
 ; NO-SIMD128:         .functype min_unordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push1=, $3, $pop0
-; NO-SIMD128-NEXT:    f32.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push2=, $2, $pop9
-; NO-SIMD128-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push3=, $1, $pop8
-; NO-SIMD128-NEXT:    f32.store 0($0), $pop3
-; NO-SIMD128-NEXT:    i32.const $push5=, 12
-; NO-SIMD128-NEXT:    i32.add $push6=, $0, $pop5
-; NO-SIMD128-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push4=, $4, $pop7
-; NO-SIMD128-NEXT:    f32.store 0($pop6), $pop4
+; NO-SIMD128-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.gt $push1=, $3, $pop17
+; NO-SIMD128-NEXT:    f32.select $push2=, $pop0, $3, $pop1
+; NO-SIMD128-NEXT:    f32.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.gt $push3=, $2, $pop15
+; NO-SIMD128-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.gt $push5=, $1, $pop13
+; NO-SIMD128-NEXT:    f32.select $push6=, $pop14, $1, $pop5
+; NO-SIMD128-NEXT:    f32.store 0($0), $pop6
+; NO-SIMD128-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.gt $push7=, $4, $pop11
+; NO-SIMD128-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: min_unordered_v4f32:
 ; NO-SIMD128-FAST:         .functype min_unordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push2=, $2, $pop9
-; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-FAST-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push3=, $3, $pop8
-; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop3
-; NO-SIMD128-FAST-NEXT:    i32.const $push4=, 12
-; NO-SIMD128-FAST-NEXT:    i32.add $push5=, $0, $pop4
-; NO-SIMD128-FAST-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT:    f32.store 0($pop5), $pop6
+; NO-SIMD128-FAST-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.gt $push1=, $1, $pop17
+; NO-SIMD128-FAST-NEXT:    f32.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.gt $push3=, $2, $pop15
+; NO-SIMD128-FAST-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-FAST-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.gt $push5=, $3, $pop13
+; NO-SIMD128-FAST-NEXT:    f32.select $push6=, $pop14, $3, $pop5
+; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop6
+; NO-SIMD128-FAST-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-FAST-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-FAST-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.gt $push7=, $4, $pop11
+; NO-SIMD128-FAST-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-FAST-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp ule <4 x float> %x, <float 5., float 5., float 5., float 5.>
   %a = select <4 x i1> %cmps, <4 x float> %x,
     <4 x float> <float 5., float 5., float 5., float 5.>
   ret <4 x float> %a
 }
 
 define <4 x float> @max_unordered_v4f32(<4 x float> %x) {
 ; SIMD128-LABEL: max_unordered_v4f32:
 ; SIMD128:         .functype max_unordered_v4f32 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
 ; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f32x4.max $push1=, $0, $pop0
+; SIMD128-NEXT:    f32x4.pmax $push1=, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: max_unordered_v4f32:
 ; SIMD128-FAST:         .functype max_unordered_v4f32 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
 ; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f32x4.max $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    f32x4.pmax $push0=, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: max_unordered_v4f32:
 ; NO-SIMD128:         .functype max_unordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push1=, $3, $pop0
-; NO-SIMD128-NEXT:    f32.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push2=, $2, $pop9
-; NO-SIMD128-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push3=, $1, $pop8
-; NO-SIMD128-NEXT:    f32.store 0($0), $pop3
-; NO-SIMD128-NEXT:    i32.const $push5=, 12
-; NO-SIMD128-NEXT:    i32.add $push6=, $0, $pop5
-; NO-SIMD128-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push4=, $4, $pop7
-; NO-SIMD128-NEXT:    f32.store 0($pop6), $pop4
+; NO-SIMD128-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.lt $push1=, $3, $pop17
+; NO-SIMD128-NEXT:    f32.select $push2=, $pop0, $3, $pop1
+; NO-SIMD128-NEXT:    f32.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.lt $push3=, $2, $pop15
+; NO-SIMD128-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.lt $push5=, $1, $pop13
+; NO-SIMD128-NEXT:    f32.select $push6=, $pop14, $1, $pop5
+; NO-SIMD128-NEXT:    f32.store 0($0), $pop6
+; NO-SIMD128-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.lt $push7=, $4, $pop11
+; NO-SIMD128-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: max_unordered_v4f32:
 ; NO-SIMD128-FAST:         .functype max_unordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push2=, $2, $pop9
-; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-FAST-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push3=, $3, $pop8
-; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop3
-; NO-SIMD128-FAST-NEXT:    i32.const $push4=, 12
-; NO-SIMD128-FAST-NEXT:    i32.add $push5=, $0, $pop4
-; NO-SIMD128-FAST-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT:    f32.store 0($pop5), $pop6
+; NO-SIMD128-FAST-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.lt $push1=, $1, $pop17
+; NO-SIMD128-FAST-NEXT:    f32.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.lt $push3=, $2, $pop15
+; NO-SIMD128-FAST-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-FAST-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.lt $push5=, $3, $pop13
+; NO-SIMD128-FAST-NEXT:    f32.select $push6=, $pop14, $3, $pop5
+; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop6
+; NO-SIMD128-FAST-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-FAST-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-FAST-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.lt $push7=, $4, $pop11
+; NO-SIMD128-FAST-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-FAST-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp uge <4 x float> %x, <float 5., float 5., float 5., float 5.>
   %a = select <4 x i1> %cmps, <4 x float> %x,
     <4 x float> <float 5., float 5., float 5., float 5.>
   ret <4 x float> %a
 }
 
 define <4 x float> @min_ordered_v4f32(<4 x float> %x) {
 ; SIMD128-LABEL: min_ordered_v4f32:
 ; SIMD128:         .functype min_ordered_v4f32 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f32x4.min $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f32x4.le $push0=, $1, $0
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: min_ordered_v4f32:
 ; SIMD128-FAST:         .functype min_ordered_v4f32 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f32x4.min $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f32x4.le $push1=, $1, $0
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: min_ordered_v4f32:
 ; NO-SIMD128:         .functype min_ordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push1=, $3, $pop0
-; NO-SIMD128-NEXT:    f32.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push2=, $2, $pop9
-; NO-SIMD128-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push3=, $1, $pop8
-; NO-SIMD128-NEXT:    f32.store 0($0), $pop3
-; NO-SIMD128-NEXT:    i32.const $push5=, 12
-; NO-SIMD128-NEXT:    i32.add $push6=, $0, $pop5
-; NO-SIMD128-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.min $push4=, $4, $pop7
-; NO-SIMD128-NEXT:    f32.store 0($pop6), $pop4
+; NO-SIMD128-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.ge $push1=, $3, $pop17
+; NO-SIMD128-NEXT:    f32.select $push2=, $pop0, $3, $pop1
+; NO-SIMD128-NEXT:    f32.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.ge $push3=, $2, $pop15
+; NO-SIMD128-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.ge $push5=, $1, $pop13
+; NO-SIMD128-NEXT:    f32.select $push6=, $pop14, $1, $pop5
+; NO-SIMD128-NEXT:    f32.store 0($0), $pop6
+; NO-SIMD128-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.ge $push7=, $4, $pop11
+; NO-SIMD128-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: min_ordered_v4f32:
 ; NO-SIMD128-FAST:         .functype min_ordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push2=, $2, $pop9
-; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-FAST-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push3=, $3, $pop8
-; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop3
-; NO-SIMD128-FAST-NEXT:    i32.const $push4=, 12
-; NO-SIMD128-FAST-NEXT:    i32.add $push5=, $0, $pop4
-; NO-SIMD128-FAST-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.min $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT:    f32.store 0($pop5), $pop6
+; NO-SIMD128-FAST-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.ge $push1=, $1, $pop17
+; NO-SIMD128-FAST-NEXT:    f32.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.ge $push3=, $2, $pop15
+; NO-SIMD128-FAST-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-FAST-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.ge $push5=, $3, $pop13
+; NO-SIMD128-FAST-NEXT:    f32.select $push6=, $pop14, $3, $pop5
+; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop6
+; NO-SIMD128-FAST-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-FAST-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-FAST-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.ge $push7=, $4, $pop11
+; NO-SIMD128-FAST-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-FAST-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp ole <4 x float> <float 5., float 5., float 5., float 5.>, %x
   %a = select <4 x i1> %cmps,
     <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x
   ret <4 x float> %a
 }
 
 define <4 x float> @max_ordered_v4f32(<4 x float> %x) {
 ; SIMD128-LABEL: max_ordered_v4f32:
 ; SIMD128:         .functype max_ordered_v4f32 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f32x4.max $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f32x4.ge $push0=, $1, $0
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: max_ordered_v4f32:
 ; SIMD128-FAST:         .functype max_ordered_v4f32 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f32x4.max $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f32x4.ge $push1=, $1, $0
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: max_ordered_v4f32:
 ; NO-SIMD128:         .functype max_ordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push1=, $3, $pop0
-; NO-SIMD128-NEXT:    f32.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push2=, $2, $pop9
-; NO-SIMD128-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push3=, $1, $pop8
-; NO-SIMD128-NEXT:    f32.store 0($0), $pop3
-; NO-SIMD128-NEXT:    i32.const $push5=, 12
-; NO-SIMD128-NEXT:    i32.add $push6=, $0, $pop5
-; NO-SIMD128-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-NEXT:    f32.max $push4=, $4, $pop7
-; NO-SIMD128-NEXT:    f32.store 0($pop6), $pop4
+; NO-SIMD128-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.le $push1=, $3, $pop17
+; NO-SIMD128-NEXT:    f32.select $push2=, $pop0, $3, $pop1
+; NO-SIMD128-NEXT:    f32.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.le $push3=, $2, $pop15
+; NO-SIMD128-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.le $push5=, $1, $pop13
+; NO-SIMD128-NEXT:    f32.select $push6=, $pop14, $1, $pop5
+; NO-SIMD128-NEXT:    f32.store 0($0), $pop6
+; NO-SIMD128-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-NEXT:    f32.le $push7=, $4, $pop11
+; NO-SIMD128-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: max_ordered_v4f32:
 ; NO-SIMD128-FAST:         .functype max_ordered_v4f32 (i32, f32, f32, f32, f32) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f32.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f32.const $push9=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push2=, $2, $pop9
-; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop2
-; NO-SIMD128-FAST-NEXT:    f32.const $push8=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push3=, $3, $pop8
-; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop3
-; NO-SIMD128-FAST-NEXT:    i32.const $push4=, 12
-; NO-SIMD128-FAST-NEXT:    i32.add $push5=, $0, $pop4
-; NO-SIMD128-FAST-NEXT:    f32.const $push7=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f32.max $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT:    f32.store 0($pop5), $pop6
+; NO-SIMD128-FAST-NEXT:    f32.const $push17=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.le $push1=, $1, $pop17
+; NO-SIMD128-FAST-NEXT:    f32.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f32.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f32.const $push16=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push15=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.le $push3=, $2, $pop15
+; NO-SIMD128-FAST-NEXT:    f32.select $push4=, $pop16, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f32.store 4($0), $pop4
+; NO-SIMD128-FAST-NEXT:    f32.const $push14=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push13=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.le $push5=, $3, $pop13
+; NO-SIMD128-FAST-NEXT:    f32.select $push6=, $pop14, $3, $pop5
+; NO-SIMD128-FAST-NEXT:    f32.store 8($0), $pop6
+; NO-SIMD128-FAST-NEXT:    i32.const $push9=, 12
+; NO-SIMD128-FAST-NEXT:    i32.add $push10=, $0, $pop9
+; NO-SIMD128-FAST-NEXT:    f32.const $push12=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.const $push11=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f32.le $push7=, $4, $pop11
+; NO-SIMD128-FAST-NEXT:    f32.select $push8=, $pop12, $4, $pop7
+; NO-SIMD128-FAST-NEXT:    f32.store 0($pop10), $pop8
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp oge <4 x float> <float 5., float 5., float 5., float 5.>, %x
   %a = select <4 x i1> %cmps,
     <4 x float> <float 5., float 5., float 5., float 5.>, <4 x float> %x
   ret <4 x float> %a
 }
 
 declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
; NO-SIMD128-FAST-NEXT:    return
   %a = call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
   ret <2 x double> %a
 }
 
 define <2 x double> @min_unordered_v2f64(<2 x double> %x) {
 ; SIMD128-LABEL: min_unordered_v2f64:
 ; SIMD128:         .functype min_unordered_v2f64 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f64x2.min $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f64x2.gt $push0=, $0, $1
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: min_unordered_v2f64:
 ; SIMD128-FAST:         .functype min_unordered_v2f64 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f64x2.min $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f64x2.gt $push1=, $0, $1
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: min_unordered_v2f64:
 ; NO-SIMD128:         .functype min_unordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.min $push1=, $2, $pop0
-; NO-SIMD128-NEXT:    f64.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.min $push2=, $1, $pop3
-; NO-SIMD128-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.gt $push1=, $2, $pop7
+; NO-SIMD128-NEXT:    f64.select $push2=, $pop0, $2, $pop1
+; NO-SIMD128-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.gt $push3=, $1, $pop5
+; NO-SIMD128-NEXT:    f64.select $push4=, $pop6, $1, $pop3
+; NO-SIMD128-NEXT:    f64.store 0($0), $pop4
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: min_unordered_v2f64:
 ; NO-SIMD128-FAST:         .functype min_unordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.min $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.min $push2=, $2, $pop3
-; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.gt $push1=, $1, $pop7
+; NO-SIMD128-FAST-NEXT:    f64.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.gt $push3=, $2, $pop5
+; NO-SIMD128-FAST-NEXT:    f64.select $push4=, $pop6, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop4
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp ule <2 x double> %x, <double 5., double 5.>
   %a = select <2 x i1> %cmps, <2 x double> %x,
     <2 x double> <double 5., double 5.>
   ret <2 x double> %a
 }
 
 define <2 x double> @max_unordered_v2f64(<2 x double> %x) {
 ; SIMD128-LABEL: max_unordered_v2f64:
 ; SIMD128:         .functype max_unordered_v2f64 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
 ; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f64x2.max $push1=, $0, $pop0
+; SIMD128-NEXT:    f64x2.pmax $push1=, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: max_unordered_v2f64:
 ; SIMD128-FAST:         .functype max_unordered_v2f64 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
 ; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f64x2.max $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    f64x2.pmax $push0=, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: max_unordered_v2f64:
 ; NO-SIMD128:         .functype max_unordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.max $push1=, $2, $pop0
-; NO-SIMD128-NEXT:    f64.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.max $push2=, $1, $pop3
-; NO-SIMD128-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.lt $push1=, $2, $pop7
+; NO-SIMD128-NEXT:    f64.select $push2=, $pop0, $2, $pop1
+; NO-SIMD128-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.lt $push3=, $1, $pop5
+; NO-SIMD128-NEXT:    f64.select $push4=, $pop6, $1, $pop3
+; NO-SIMD128-NEXT:    f64.store 0($0), $pop4
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: max_unordered_v2f64:
 ; NO-SIMD128-FAST:         .functype max_unordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.max $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.max $push2=, $2, $pop3
-; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.lt $push1=, $1, $pop7
+; NO-SIMD128-FAST-NEXT:    f64.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.lt $push3=, $2, $pop5
+; NO-SIMD128-FAST-NEXT:    f64.select $push4=, $pop6, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop4
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp uge <2 x double> %x, <double 5., double 5.>
   %a = select <2 x i1> %cmps, <2 x double> %x,
     <2 x double> <double 5., double 5.>
   ret <2 x double> %a
 }
 
 define <2 x double> @min_ordered_v2f64(<2 x double> %x) {
 ; SIMD128-LABEL: min_ordered_v2f64:
 ; SIMD128:         .functype min_ordered_v2f64 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f64x2.min $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f64x2.le $push0=, $1, $0
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: min_ordered_v2f64:
 ; SIMD128-FAST:         .functype min_ordered_v2f64 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f64x2.min $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f64x2.le $push1=, $1, $0
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: min_ordered_v2f64:
 ; NO-SIMD128:         .functype min_ordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.min $push1=, $2, $pop0
-; NO-SIMD128-NEXT:    f64.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.min $push2=, $1, $pop3
-; NO-SIMD128-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.ge $push1=, $2, $pop7
+; NO-SIMD128-NEXT:    f64.select $push2=, $pop0, $2, $pop1
+; NO-SIMD128-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.ge $push3=, $1, $pop5
+; NO-SIMD128-NEXT:    f64.select $push4=, $pop6, $1, $pop3
+; NO-SIMD128-NEXT:    f64.store 0($0), $pop4
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: min_ordered_v2f64:
 ; NO-SIMD128-FAST:         .functype min_ordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.min $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.min $push2=, $2, $pop3
-; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.ge $push1=, $1, $pop7
+; NO-SIMD128-FAST-NEXT:    f64.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.ge $push3=, $2, $pop5
+; NO-SIMD128-FAST-NEXT:    f64.select $push4=, $pop6, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop4
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp ole <2 x double> <double 5., double 5.>, %x
   %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>,
     <2 x double> %x
   ret <2 x double> %a
 }
 
 define <2 x double> @max_ordered_v2f64(<2 x double> %x) {
 ; SIMD128-LABEL: max_ordered_v2f64:
 ; SIMD128:         .functype max_ordered_v2f64 (v128) -> (v128)
 ; SIMD128-NEXT:  # %bb.0:
-; SIMD128-NEXT:    v128.const $push0=, 0x1.4p2, 0x1.4p2
-; SIMD128-NEXT:    f64x2.max $push1=, $0, $pop0
+; SIMD128-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-NEXT:    f64x2.ge $push0=, $1, $0
+; SIMD128-NEXT:    v128.bitselect $push1=, $pop2, $0, $pop0
 ; SIMD128-NEXT:    return $pop1
 ;
 ; SIMD128-FAST-LABEL: max_ordered_v2f64:
 ; SIMD128-FAST:         .functype max_ordered_v2f64 (v128) -> (v128)
 ; SIMD128-FAST-NEXT:  # %bb.0:
-; SIMD128-FAST-NEXT:    v128.const $push1=, 0x1.4p2, 0x1.4p2
-; SIMD128-FAST-NEXT:    f64x2.max $push0=, $0, $pop1
+; SIMD128-FAST-NEXT:    v128.const $push3=, 0x1.4p2, 0x1.4p2
+; SIMD128-FAST-NEXT:    local.tee $push2=, $1=, $pop3
+; SIMD128-FAST-NEXT:    f64x2.ge $push1=, $1, $0
+; SIMD128-FAST-NEXT:    v128.bitselect $push0=, $pop2, $0, $pop1
 ; SIMD128-FAST-NEXT:    return $pop0
 ;
 ; NO-SIMD128-LABEL: max_ordered_v2f64:
 ; NO-SIMD128:         .functype max_ordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-NEXT:  # %bb.0:
 ; NO-SIMD128-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.max $push1=, $2, $pop0
-; NO-SIMD128-NEXT:    f64.store 8($0), $pop1
-; NO-SIMD128-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-NEXT:    f64.max $push2=, $1, $pop3
-; NO-SIMD128-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.le $push1=, $2, $pop7
+; NO-SIMD128-NEXT:    f64.select $push2=, $pop0, $2, $pop1
+; NO-SIMD128-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-NEXT:    f64.le $push3=, $1, $pop5
+; NO-SIMD128-NEXT:    f64.select $push4=, $pop6, $1, $pop3
+; NO-SIMD128-NEXT:    f64.store 0($0), $pop4
 ; NO-SIMD128-NEXT:    return
 ;
 ; NO-SIMD128-FAST-LABEL: max_ordered_v2f64:
 ; NO-SIMD128-FAST:         .functype max_ordered_v2f64 (i32, f64, f64) -> ()
 ; NO-SIMD128-FAST-NEXT:  # %bb.0:
 ; NO-SIMD128-FAST-NEXT:    f64.const $push0=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.max $push1=, $1, $pop0
-; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT:    f64.const $push3=, 0x1.4p2
-; NO-SIMD128-FAST-NEXT:    f64.max $push2=, $2, $pop3
-; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push7=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.le $push1=, $1, $pop7
+; NO-SIMD128-FAST-NEXT:    f64.select $push2=, $pop0, $1, $pop1
+; NO-SIMD128-FAST-NEXT:    f64.store 0($0), $pop2
+; NO-SIMD128-FAST-NEXT:    f64.const $push6=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.const $push5=, 0x1.4p2
+; NO-SIMD128-FAST-NEXT:    f64.le $push3=, $2, $pop5
+; NO-SIMD128-FAST-NEXT:    f64.select $push4=, $pop6, $2, $pop3
+; NO-SIMD128-FAST-NEXT:    f64.store 8($0), $pop4
 ; NO-SIMD128-FAST-NEXT:    return
   %cmps = fcmp oge <2 x double> <double 5., double 5.>, %x
   %a = select <2 x i1> %cmps, <2 x double> <double 5., double 5.>,
     <2 x double> %x
   ret <2 x double> %a
 }
 
 declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)