Use ArrayRef instead of raw pointers. NFC

[sepavloff]

Summary

Change signature of TargetLowering::getRoundingControlRegisters so that
it returns ArrayRef, not plain pointer.

[pengfei]

LG.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

14950–14951

Maybe return {AArch64::FPCR};?

llvm/lib/Target/X86/X86ISelLowering.cpp

3103

ditto.

[efriedma]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

14950–14951

I'm pretty sure return {AArch64::FPCR}; would be a use-after-free. (It allocates an std::initializer_list on the stack, then returns a reference to it.)

[pengfei]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

14950–14951

Thanke @efriedma! You are right https://godbolt.org/z/ar7rd7v8M
Sorry for misleading.

[sepavloff]

Thanks!

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   /// Returns a 0 terminated array of registers that can be safely used as
   /// scratch registers.
   virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
     return nullptr;
   }
 
   /// Returns a 0 terminated array of rounding control registers that can be
   /// attached into strict FP call.
-  virtual const MCPhysReg *getRoundingControlRegisters() const {
-    return nullptr;
+  virtual ArrayRef<MCPhysReg> getRoundingControlRegisters() const {
+    return ArrayRef<MCPhysReg>();
   }
 
   /// This callback is used to prepare for a volatile or atomic load.
   /// It takes a chain node as input and returns the chain for the load itself.
   ///
   /// Having a callback like this is necessary for targets like SystemZ,
   /// which allows a CPU to reuse the result of a previous load indefinitely,
   /// even if a cache-coherent store is performed by another CPU.  The default

llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
           if (Reg.isPhysical())
             UsedRegs.push_back(Reg);
         }
     }
   }
 
   // Add rounding control registers as implicit def for function call.
   if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
-    const MCPhysReg *RCRegs = TLI->getRoundingControlRegisters();
-    if (RCRegs)
-      for (; *RCRegs; ++RCRegs)
-        UsedRegs.push_back(*RCRegs);
+    ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
+    for (MCPhysReg Reg : RCRegs)
+      UsedRegs.push_back(Reg);
   }
 
   // Finally mark unused registers as dead.
   if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef())
     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
 
   // STATEPOINT is too 'dynamic' to have meaningful machine description.
   // We have to manually tie operands.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

public:
   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                   EVT VT) const override;
   bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
 
   bool generateFMAsInMachineCombiner(EVT VT,
                                      CodeGenOpt::Level OptLevel) const override;
 
   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
-  const MCPhysReg *getRoundingControlRegisters() const override;
+  ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
 
   /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
   bool isDesirableToCommuteWithShift(const SDNode *N,
                                      CombineLevel Level) const override;
 
   /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
   bool isDesirableToCommuteXorWithShift(const SDNode *N) const override;
 

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
   // site. Hence we include LR in the scratch registers, which are in turn added
   // as implicit-defs for stackmaps and patchpoints.
   static const MCPhysReg ScratchRegs[] = {
     AArch64::X16, AArch64::X17, AArch64::LR, 0
   };
   return ScratchRegs;
 }
 
-const MCPhysReg *AArch64TargetLowering::getRoundingControlRegisters() const {
-  static const MCPhysReg RCRegs[] = {AArch64::FPCR, 0};
+ArrayRef<MCPhysReg> AArch64TargetLowering::getRoundingControlRegisters() const {
+  static const MCPhysReg RCRegs[] = {AArch64::FPCR};
   return RCRegs;
 }
 
 bool
 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
                                                      CombineLevel Level) const {
   assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA ||
           N->getOpcode() == ISD::SRL) &&
          "Expected shift op");

llvm/lib/Target/X86/X86ISelLowering.h

EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
                             ISD::NodeType ExtendKind) const override;
 
     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                         bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         LLVMContext &Context) const override;
 
     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
-    const MCPhysReg *getRoundingControlRegisters() const override;
+    ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
 
     TargetLoweringBase::AtomicExpansionKind
     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
     TargetLoweringBase::AtomicExpansionKind
     shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
     TargetLoweringBase::AtomicExpansionKind
     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
     TargetLoweringBase::AtomicExpansionKind

llvm/lib/Target/X86/X86ISelLowering.cpp

bool X86TargetLowering::CanLowerReturn(
   return CCInfo.CheckReturn(Outs, RetCC_X86);
 }
 
 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
   static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
   return ScratchRegs;
 }
 
-const MCPhysReg *X86TargetLowering::getRoundingControlRegisters() const {
+ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
   // FIXME: We should def X86::FPCW for x87 as well. But it affects a lot of lit
   // tests at the moment, which is not what we expected.
-  static const MCPhysReg RCRegs[] = { X86::MXCSR, 0 };
+  static const MCPhysReg RCRegs[] = {X86::MXCSR};
   return RCRegs;
 }
 
 /// Lowers masks values (v*i1) to the local register values
 /// \returns DAG node after lowering to register type
 static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
                                const SDLoc &Dl, SelectionDAG &DAG) {
   EVT ValVT = ValArg.getValueType();