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Differential D143044

[InstCombine][NFC] Add tests pre-implementation of issue #54856
ClosedPublic

Authored by jmciver on Jan 31 2023, 9:11 PM.

Details

Reviewers
RKSimon
fhahn
spatel
hjyamauchi
nikic
goldstein.w.n
Commits
rGea868d5748ce: [InstCombine][NFC] Add tests pre-implementation of issue #54856
Summary

Provide both positive and negative testing using scalar and vector values for
issue #54856.

Diff Detail

Event Timeline

jmciver created this revision.Jan 31 2023, 9:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 31 2023, 9:11 PM
Herald added a subscriber: StephenFan. · View Herald Transcript
jmciver added a parent revision: D143032: [InstCombine] Allow splats with poison/undef in llvm::decomposeBitTestICmp.Jan 31 2023, 9:11 PM
Harbormaster completed remote builds in B211137: Diff 493817.Jan 31 2023, 10:15 PM
jmciver added a child revision: D125717: [InstCombine] Optimize and of icmps with power-of-2 and contiguous masks.Feb 1 2023, 3:02 PM
jmciver published this revision for review.Feb 1 2023, 3:10 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 1 2023, 3:10 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
jmciver updated this revision to Diff 494097.Feb 1 2023, 3:57 PM

Fix vector of two elements test case

jmciver mentioned this in D125717: [InstCombine] Optimize and of icmps with power-of-2 and contiguous masks.Feb 1 2023, 3:59 PM
Harbormaster completed remote builds in B211335: Diff 494097.Feb 1 2023, 4:44 PM
RKSimon added inline comments.Feb 16 2023, 6:52 AM
llvm/test/Transforms/InstCombine/icmp-logical.ll
1775

Sequentially numbering test names for a fold isn't great - it'd be better to use the name to describe the specific pattern in more detail

jmciver updated this revision to Diff 499008.Feb 20 2023, 6:41 PM

Remove sequential test names in favor of pattern details

jmciver added inline comments.Feb 20 2023, 6:45 PM
llvm/test/Transforms/InstCombine/icmp-logical.ll
1775

Thanks for the input! I have attempted to improve the test names with pattern details.

Harbormaster completed remote builds in B214900: Diff 499008.Feb 20 2023, 10:01 PM
jmciver marked an inline comment as done.Feb 21 2023, 3:01 PM
jmciver updated this revision to Diff 508456.Mar 26 2023, 7:01 PM

Rebase to latest main.

Harbormaster completed remote builds in B221865: Diff 508456.Mar 26 2023, 7:02 PM
jmciver updated this revision to Diff 508469.Mar 26 2023, 8:47 PM

Rebase to latest main.

Harbormaster completed remote builds in B221873: Diff 508469.Mar 26 2023, 8:48 PM
jmciver updated this revision to Diff 508480.Mar 26 2023, 10:18 PM

Rebase onto latest main.

Harbormaster completed remote builds in B221882: Diff 508480.Mar 26 2023, 10:19 PM
jmciver updated this revision to Diff 522024.May 14 2023, 2:28 PM

Add undef based splat vector tests

Harbormaster completed remote builds in B231882: Diff 522024.May 14 2023, 3:20 PM
jmciver updated this revision to Diff 523250.May 17 2023, 8:45 PM

Add postfix of "fail" to the names of tests that intentionally do not change

Herald added a subscriber: hiraditya. · View Herald TranscriptMay 17 2023, 8:45 PM
Harbormaster completed remote builds in B232766: Diff 523250.May 17 2023, 8:46 PM
jmciver updated this revision to Diff 523251.May 17 2023, 8:47 PM

Add postfix of "fail" to the names of tests that intentionally do not change

Harbormaster completed remote builds in B232767: Diff 523251.May 17 2023, 9:24 PM
jmciver updated this revision to Diff 523888.May 19 2023, 12:12 PM

Move tests from icmp-logical.ll to icmp-power2-and-icmp-shifted-mask.ll

Harbormaster completed remote builds in B233266: Diff 523888.May 19 2023, 2:59 PM
goldstein.w.n accepted this revision.Jun 1 2023, 9:20 PM
goldstein.w.n added a subscriber: goldstein.w.n.

LGTM.

Probably slightly more tests than needed but more is always better than less :)

This revision is now accepted and ready to land.Jun 1 2023, 9:20 PM
jmciver added a comment.Jun 2 2023, 6:54 PM

@goldstein.w.n thanks for taking the time to review.

Closed by commit rGea868d5748ce: [InstCombine][NFC] Add tests pre-implementation of issue #54856 (authored by jmciver). · Explain WhyJun 9 2023, 3:10 PM
This revision was automatically updated to reflect the committed changes.
jmciver added a commit: rGea868d5748ce: [InstCombine][NFC] Add tests pre-implementation of issue #54856.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
670 lines

Diff 508469

llvm/test/Transforms/InstCombine/icmp-logical.ll

Show First 20 Lines • Show All 1,763 Lines • ▼ Show 20 Lines;
%t1 = and i32 %x, 6 %t1 = and i32 %x, 6
%t2 = icmp eq i32 %t1, 0 %t2 = icmp eq i32 %t1, 0
%t3 = and i32 %x, 15 %t3 = and i32 %x, 15
%t4 = icmp ne i32 %t3, 8 %t4 = icmp ne i32 %t3, 8
%t5 = select i1 %t4, i1 true, i1 %t2 %t5 = select i1 %t4, i1 true, i1 %t2
ret i1 %t5 ret i1 %t5
} }
define i1 @masked_icmps_bmask_notmixed_or(i32 %A) { define i1 @masked_icmps_bmask_notmixed_or(i32 %A) {
; CHECK-LABEL: @masked_icmps_bmask_notmixed_or( ; CHECK-LABEL: @masked_icmps_bmask_notmixed_or(
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[TMP1]], 3 ; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[TMP1]], 3
RKSimonUnsubmitted
Done
ReplyInline Actions

Sequentially numbering test names for a fold isn't great - it'd be better to use the name to describe the specific pattern in more detail

RKSimon: Sequentially numbering test names for a fold isn't great - it'd be better to use the name to…
jmciverAuthorUnsubmitted
Done
ReplyInline Actions

Thanks for the input! I have attempted to improve the test names with pattern details.

jmciver: Thanks for the input! I have attempted to improve the test names with pattern details.
; CHECK-NEXT: ret i1 [[RES]] ; CHECK-NEXT: ret i1 [[RES]]
; ;
%mask1 = and i32 %A, 15 ; 0x0f %mask1 = and i32 %A, 15 ; 0x0f
%tst1 = icmp eq i32 %mask1, 3 ; 0x03 %tst1 = icmp eq i32 %mask1, 3 ; 0x03
%mask2 = and i32 %A, 255 ; 0xff %mask2 = and i32 %A, 255 ; 0xff
%tst2 = icmp eq i32 %mask2, 243; 0xf3 %tst2 = icmp eq i32 %mask2, 243; 0xf3
%res = or i1 %tst1, %tst2 %res = or i1 %tst1, %tst2
ret i1 %res ret i1 %res
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; ;
%mask1 = and i32 %A, 254 ; 0xfe %mask1 = and i32 %A, 254 ; 0xfe
%tst1 = icmp ne i32 %mask1, 252 ; 0xfc %tst1 = icmp ne i32 %mask1, 252 ; 0xfc
%mask2 = and i32 %A, 253 ; 0xfd %mask2 = and i32 %A, 253 ; 0xfd
%tst2 = icmp ne i32 %mask2, 252 ; 0xfc %tst2 = icmp ne i32 %mask2, 252 ; 0xfc
%res = and i1 %tst1, %tst2 %res = and i1 %tst1, %tst2
ret i1 %res ret i1 %res
} }
; Issue #54856
; ((X u< 0x8000000) & ((X & 0x60000000) != 0x60000000)) -> X u< 0x60000000
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_1610612736(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_1610612736(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 2147483648
%t2 = and i32 %x, 1610612736
%t3 = icmp ne i32 %t2, 1610612736
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_1610612736(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_1610612736(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1610612736
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1610612736
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 2147483648
%t2 = and i32 %x, 1610612736
%t3 = icmp ne i32 %t2, 1610612736
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x8000000) & ((X & 0x7FFFFFFF) != 0x7FFFFFFF)) -> X u< 0x7FFFFFFF
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_2147483647(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 2147483648
%t2 = and i32 %x, 2147483647
%t3 = icmp ne i32 %t2, 2147483647
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_2147483647(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[X:%.*]], -1
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 2147483647
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 2147483647
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 2147483648
%t2 = and i32 %x, 2147483647
%t3 = icmp ne i32 %t2, 2147483647
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x4000000) & ((X & 0x30000000) != 0x30000000)) -> X u< 0x30000000
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_805306368(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_2147483648_805306368(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 1073741824
%t2 = and i32 %x, 805306368
%t3 = icmp ne i32 %t2, 805306368
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_805306368(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_2147483648_805306368(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 805306368
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 805306368
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 1073741824
%t2 = and i32 %x, 805306368
%t3 = icmp ne i32 %t2, 805306368
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x40000000) & ((X & 0x3FFFFFFF) != 0x3FFFFFFF)) -> X u< 0x3FFFFFFF
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1073741824_1073741823(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_1073741824_1073741823(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 1073741824
%t2 = and i32 %x, 1073741823
%t3 = icmp ne i32 %t2, 1073741823
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1073741824_1073741823(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_1073741824_1073741823(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 1073741824
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 1073741823
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 1073741823
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 1073741824
%t2 = and i32 %x, 1073741823
%t3 = icmp ne i32 %t2, 1073741823
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 8) & ((X & 7) != 7)) -> X u< 7
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_7(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 7
%t3 = icmp ne i32 %t2, 7
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_7(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 7
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 7
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 7
%t3 = icmp ne i32 %t2, 7
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 8) & ((X & 6) != 6)) -> X u< 6
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_6(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 6
%t3 = icmp ne i32 %t2, 6
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_6(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 6
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 6
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 6
%t3 = icmp ne i32 %t2, 6
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 8) & ((X & 5) != 5)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_5_nc_gap_in_mask(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_5_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 5
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 5
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 5
%t3 = icmp ne i32 %t2, 5
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_5_nc_gap_in_mask(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_5_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 5
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 5
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 5
%t3 = icmp ne i32 %t2, 5
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 8) & ((X & 3) != 3)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_3_nc_gap_between_masks(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_3_nc_gap_between_masks(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 3
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 3
%t3 = icmp ne i32 %t2, 3
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_3_nc_gap_between_masks(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_3_nc_gap_between_masks(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 3
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 3
%t3 = icmp ne i32 %t2, 3
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x100) & ((X & 0x0EF) != 0x0EF)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_256_239_nc_gap_in_mask(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_256_239_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 256
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 239
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 239
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 256
%t2 = and i32 %x, 239
%t3 = icmp ne i32 %t2, 239
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_256_239_nc_gap_in_mask(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_256_239_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 256
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 239
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 239
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 256
%t2 = and i32 %x, 239
%t3 = icmp ne i32 %t2, 239
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x08) & ((X & 0x70) != 0x70)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_112_nc_mask_to_left(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_112_nc_mask_to_left(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 112
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 112
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 112
%t3 = icmp ne i32 %t2, 112
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_112_nc_mask_to_left(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_112_nc_mask_to_left(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 112
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 112
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 112
%t3 = icmp ne i32 %t2, 112
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x08) & ((X & 0x38) != 0x38))) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_56_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_56_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 56
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 56
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 56
%t3 = icmp ne i32 %t2, 56
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_56_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_56_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 56
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 56
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 56
%t3 = icmp ne i32 %t2, 56
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x08) & ((X & 0x18) != 0x18)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_24_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_24_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 24
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 24
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 24
%t3 = icmp ne i32 %t2, 24
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_24_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_24_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 24
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 24
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 24
%t3 = icmp ne i32 %t2, 24
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; ((X u< 0x8) & ((X & 0xC) != 0xC)) -> no change
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_12_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_8_12_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 12
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 12
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 12
%t3 = icmp ne i32 %t2, 12
%t4 = and i1 %t1, %t3
ret i1 %t4
}
define i1 @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_12_nc_mask_overlap(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_swapped_8_12_nc_mask_overlap(
; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8
; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 12
; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 12
; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]
; CHECK-NEXT: ret i1 [[T4]]
;
%t1 = icmp ult i32 %x, 8
%t2 = and i32 %x, 12
%t3 = icmp ne i32 %t2, 12
%t4 = and i1 %t3, %t1
ret i1 %t4
}
; Vector of 1 reduction
define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147483647(<1 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147483647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147483647>
; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <1 x i1> [[T4]]
;
%t1 = icmp ult <1 x i32> %x, <i32 2147483648>
%t2 = and <1 x i32> %x, <i32 2147483647>
%t3 = icmp ne <1 x i32> %t2, <i32 2147483647>
%t4 = and <1 x i1> %t1, %t3
ret <1 x i1> %t4
}
define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147483647(<1 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147483647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147483647>
; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <1 x i1> [[T4]]
;
%t1 = icmp ult <1 x i32> %x, <i32 2147483648>
%t2 = and <1 x i32> %x, <i32 2147483647>
%t3 = icmp ne <1 x i32> %t2, <i32 2147483647>
%t4 = and <1 x i1> %t3, %t1
ret <1 x i1> %t4
}
; Vector of 2 reduction
define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1610612736_2147483647(<2 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1610612736_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <2 x i1> [[T4]]
;
%t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
%t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
%t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
%t4 = and <2 x i1> %t1, %t3
ret <2 x i1> %t4
}
define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1610612736_2147483647(<2 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1610612736_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <2 x i1> [[T4]]
;
%t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
%t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
%t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
%t4 = and <2 x i1> %t3, %t1
ret <2 x i1> %t4
}
; Vector of 2 reduction with splat containing poison
define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_2147483648_1610612736_2147483647(<2 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_splat_2147483648_1610612736_2147483647(
; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 poison>
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <2 x i1> [[T4]]
;
%t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 poison>
%t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>
%t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>
%t4 = and <2 x i1> %t1, %t3
ret <2 x i1> %t4
}
; Vector of 7 reduction
define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_others(<7 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_others(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <7 x i1> [[T4]]
;
%t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
%t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
%t4 = and <7 x i1> %t1, %t3
ret <7 x i1> %t4
}
define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_others(<7 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_others(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <7 x i1> [[T4]]
;
%t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
%t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>
%t4 = and <7 x i1> %t3, %t1
ret <7 x i1> %t4
}
; Vector of 6 reduction
define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_64_others(<6 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_64_others(
; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <6 x i1> [[T4]]
;
%t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
%t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
%t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
%t4 = and <6 x i1> %t1, %t3
ret <6 x i1> %t4
}
define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_64_others(<6 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_64_others(
; CHECK-NEXT: [[T1:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <6 x i1> [[T4]]
;
%t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
%t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
%t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>
%t4 = and <6 x i1> %t1, %t3
ret <6 x i1> %t4
}
; Vector of 0 of 1 compatible, no change
define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147482647_nc_gap_in_mask(<1 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_2147482647_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147482647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147482647>
; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <1 x i1> [[T4]]
;
%t1 = icmp ult <1 x i32> %x, <i32 2147483648>
%t2 = and <1 x i32> %x, <i32 2147482647>
%t3 = icmp ne <1 x i32> %t2, <i32 2147482647>
%t4 = and <1 x i1> %t1, %t3
ret <1 x i1> %t4
}
define <1 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147482647_nc_gap_in_mask(<1 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_2147482647_nc_gap_in_mask(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], <i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], <i32 2147482647>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], <i32 2147482647>
; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <1 x i1> [[T4]]
;
%t1 = icmp ult <1 x i32> %x, <i32 2147483648>
%t2 = and <1 x i32> %x, <i32 2147482647>
%t3 = icmp ne <1 x i32> %t2, <i32 2147482647>
%t4 = and <1 x i1> %t3, %t1
ret <1 x i1> %t4
}
; Vector 1 of 2 compatible, no change
define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1073741823_nc_gap_between_masks(<2 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_2147483648_1073741823_nc_gap_between_masks(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 1073741823>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 1073741823>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <2 x i1> [[T4]]
;
%t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
%t2 = and <2 x i32> %x, <i32 1610612736, i32 1073741823>
%t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 1073741823>
%t4 = and <2 x i1> %t1, %t3
ret <2 x i1> %t4
}
define <2 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1073741823_nc_gap_between_masks(<2 x i32> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_2147483648_1073741823_nc_gap_between_masks(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 1073741823>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 1073741823>
; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <2 x i1> [[T4]]
;
%t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>
%t2 = and <2 x i32> %x, <i32 1610612736, i32 1073741823>
%t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 1073741823>
%t4 = and <2 x i1> %t3, %t1
ret <2 x i1> %t4
}
; Vector 1 of 7 compatible, no change
define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_nc_1_of_7(<7 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_nc_1_of_7(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <7 x i1> [[T4]]
;
%t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <7 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
%t3 = icmp ne <7 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
%t4 = and <7 x i1> %t1, %t3
ret <7 x i1> %t4
}
define <7 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_nc_1_of_7(<7 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_nc_1_of_7(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <7 x i1> [[T4]]
;
%t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <7 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
%t3 = icmp ne <7 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>
%t4 = and <7 x i1> %t3, %t1
ret <7 x i1> %t4
}
; Vector 0 of 6 compatible, no change
define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_0_of_6(<6 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_128_0_of_6(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <6 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]
; CHECK-NEXT: ret <6 x i1> [[T4]]
;
%t1 = icmp ult <6 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <6 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
%t3 = icmp ne <6 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
%t4 = and <6 x i1> %t1, %t3
ret <6 x i1> %t4
}
define <6 x i1> @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_0_of_6(<6 x i8> %x) {
; CHECK-LABEL: @masked_icmps_mask_allzeros_bmask_notmixed_and_notallones_vector_swapped_128_0_of_6(
; CHECK-NEXT: [[T1:%.*]] = icmp sgt <6 x i8> [[X:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T3]], [[T1]]
; CHECK-NEXT: ret <6 x i1> [[T4]]
;
%t1 = icmp ult <6 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
%t2 = and <6 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
%t3 = icmp ne <6 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>
%t4 = and <6 x i1> %t3, %t1
ret <6 x i1> %t4
}