AMDGPU/GlobalISel: Partially fix getGenericInstructionUniformity

[arsenm]

Summary

This was broken for the common case of instructions which are uniform
if their inputs are uniform. This is broken for control flow intrinsics
since the API currently does not express which result operand is in question.

This generates failures in just about every intrinsic test when uniformity
analysis is performed without this.

[Petar.Avramovic]

This might not be related but what happens with control flow intrinsics that get preselected in legalizer?

[arsenm]

In D142220#4068991, @Petar.Avramovic wrote:

This might not be related but what happens with control flow intrinsics that get preselected in legalizer?

They get preselected so they don't reach regbankselect in the usual compile flow. We should be able to compute correct uniformity information at any point, so it's not critical that the control flow intrinsics be correct to get something minimally functional

[Pierre-vh]

LGTM but I will leave it up to someone with experience with uniformity analysis to approve

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

8388

nit: If I understand correctly we would need an extra parameter to getGenericInstructionUniformity in order to handle this case, right?
Perhaps add that to the comment to make it clear that the API as-is doesn't give us enough information to tell?

[arsenm]

This was 40025761564bae5b62c38745ed6edc2667419591

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
   return SchedModel.computeInstrLatency(&MI);
 }
 
 InstructionUniformity
 SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
   unsigned opcode = MI.getOpcode();
   if (opcode == AMDGPU::G_INTRINSIC ||
       opcode == AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS) {
-    return AMDGPU::isIntrinsicSourceOfDivergence(MI.getIntrinsicID())
-               ? InstructionUniformity::NeverUniform
-               : InstructionUniformity::AlwaysUniform;
+    auto IID = static_cast<Intrinsic::ID>(MI.getIntrinsicID());
+    if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
+      return InstructionUniformity::NeverUniform;
+
+    // FIXME: Get a tablegen table for this.
+    switch (IID) {
+    case Intrinsic::amdgcn_readfirstlane:
+    case Intrinsic::amdgcn_readlane:
+    case Intrinsic::amdgcn_icmp:
+    case Intrinsic::amdgcn_fcmp:
+    case Intrinsic::amdgcn_ballot:
+    case Intrinsic::amdgcn_if_break:
+      return InstructionUniformity::AlwaysUniform;
+    case Intrinsic::amdgcn_if:
+    case Intrinsic::amdgcn_else:
+      // FIXME: Uniform if second result
+      break;
+    }
+
+    return InstructionUniformity::Default;
   }
 
   // Loads from the private and flat address spaces are divergent, because
   // threads can execute the load instruction with the same inputs and get
   // different results.
   //
   // All other loads are not divergent, because if threads issue loads with the
   // same arguments, they will always get the same result.