[MC] Store implicit ops immediately after the TargetInsts table. NFC.

[foad]

Summary

This shrinks MCInstrDesc (and hence the whole TargetInsts table) because
we can store a 16-bit offset value to access the implicit operands,
instead of a pointer. This also reduces the number of relocs that need
to be applied when LLVM is compiled as position-independent code.

[arsenm]

llvm/include/llvm/MC/MCInstrDesc.h

579–580

This looks a bit undefined to me. Is ubsan and asan happy with this?

[foad]

llvm/include/llvm/MC/MCInstrDesc.h

579–580

Yes. I ran check-llvm with LLVM_USE_SANITIZER='Address;Undefined' and it is clean.

[foad]

Rebase

[barannikov88]

LGTM with a couple of nits.
This change is significant, I think you need more votes to proceed.

llvm/utils/TableGen/InstrInfoEmitter.cpp

910

Could Descs be a better name? So that you don't access it as Insts.Insts below.

949

Please make sure auto is qualified correctly if you prefer using it.
This auto & is really Record *&, while it should be const Record * (const non-reference).
Or just don't use it at all :) (as the coding style suggests).

[foad]

Rebase.

[foad]

llvm/utils/TableGen/InstrInfoEmitter.cpp

910

Maybe. It's actually e.g. AMDGPUInsts.Insts, but I guess your point still applies.

[foad]

Rebase. Rename TargetInsts.Insts to TargetDescs.Insts.

[martien-de-jong]

llvm/include/llvm/MC/MCInstrDesc.h

214

Could we give OpInfo the same treatment?

llvm/utils/TableGen/InstrInfoEmitter.cpp

1070

I'm dreaming of getting rid of these extern auxiliary tables. Perhaps we can start by packing all of these addresses in a struct that can serve as an interface class? We can then make them static and only export that struct. In the future, that structure will then be the only thing that needs to be relocated.
Hiding the current names would expose the current users.

[martien-de-jong]

llvm/utils/TableGen/InstrInfoEmitter.cpp

922

In some private table gen backend that also used these offset tables, we went away from the one raw out stream. Instead, there's an array abstraction that builds the body of the array in a stringstream and methods to generate the reference string (pointer to some element, or its index or offset) for e.g. the last added entry, or a given offset from a local base. It allows you to build all tables in one intuitive sweep, and then emit the accumulated bodies in some order to the output stream. If there's interest, I could probably share that table abstraction to add as common facility to tablegen.

[foad]

llvm/include/llvm/MC/MCInstrDesc.h

214

Yes! D142219!

llvm/utils/TableGen/InstrInfoEmitter.cpp

922

Sounds nice!

1070

Sounds reasonable. The only rogue user of TargetInsts/TargetDescs that I'm aware of is the ARM AsmParser that I had to update in this patch. There was some discussion about how to fix that in D142217 but I didn't have the ARM expertise to do it myself.

[martien-de-jong]

llvm/include/llvm/MC/MCInstrDesc.h

214

Ah, many small steps make a great leap.

llvm/utils/TableGen/InstrInfoEmitter.cpp

922

I'll start digging and removing the rust.

1070

Right. I don't grasp the details right away, but I think it is a perfect example of methods that could be added to the interface class, or in a local class derived from it.

[RKSimon]

@foad MSVC builds seem to be breaking due to this:
https://lab.llvm.org/buildbot/#/builders/86/builds/53509

LLVMARMAsmParser.lib(ARMAsmParser.cpp.obj) : error LNK2001: unresolved external symbol "class llvm::MCInstrDesc const * const llvm::ARMDescs" (?ARMDescs@llvm@@3QBVMCInstrDesc@1@B)
bin\llc.exe : fatal error LNK1120: 1 unresolved externals
ninja: build stopped: subcommand failed.

[foad]

In D142218#4223664, @RKSimon wrote:

@foad MSVC builds seem to be breaking due to this:
https://lab.llvm.org/buildbot/#/builders/86/builds/53509

LLVMARMAsmParser.lib(ARMAsmParser.cpp.obj) : error LNK2001: unresolved external symbol "class llvm::MCInstrDesc const * const llvm::ARMDescs" (?ARMDescs@llvm@@3QBVMCInstrDesc@1@B)
bin\llc.exe : fatal error LNK1120: 1 unresolved externals
ninja: build stopped: subcommand failed.

Thanks - I just noticed that too. I have a quick fix but can't push it now due to some partial github outage.

[foad]

In D142218#4223825, @foad wrote:

In D142218#4223664, @RKSimon wrote:

@foad MSVC builds seem to be breaking due to this:
https://lab.llvm.org/buildbot/#/builders/86/builds/53509

LLVMARMAsmParser.lib(ARMAsmParser.cpp.obj) : error LNK2001: unresolved external symbol "class llvm::MCInstrDesc const * const llvm::ARMDescs" (?ARMDescs@llvm@@3QBVMCInstrDesc@1@B)
bin\llc.exe : fatal error LNK1120: 1 unresolved externals
ninja: build stopped: subcommand failed.

Thanks - I just noticed that too. I have a quick fix but can't push it now due to some partial github outage.

Pushed ffab44bd960c6392a0ed1f945cc145a2a2643c8c

llvm/include/llvm/MC/MCInstrDesc.h

public:
 
   unsigned short Opcode;         // The opcode number
   unsigned short NumOperands;    // Num of args (may be more if variable_ops)
   unsigned char NumDefs;         // Num of args that are definitions
   unsigned char Size;            // Number of bytes in encoding.
   unsigned short SchedClass;     // enum identifying instr sched class
   unsigned char NumImplicitUses; // Num of regs implicitly used
   unsigned char NumImplicitDefs; // Num of regs implicitly defined
+  unsigned short ImplicitOffset; // Offset to start of implicit op list
   uint64_t Flags;                // Flags identifying machine instr class
   uint64_t TSFlags;              // Target Specific Flag values
-  const MCPhysReg *ImplicitOps;  // List of implicit uses followed by defs
   const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
 
   /// Returns the value of the specified operand constraint if
   /// it is present. Returns -1 if it is not present.
   int getOperandConstraint(unsigned OpNum,
                            MCOI::OperandConstraint Constraint) const {
     if (OpNum < NumOperands &&
         (operands()[OpNum].Constraints & (1 << Constraint))) {
public:
 
   /// Return a list of registers that are potentially read by any
   /// instance of this machine instruction.  For example, on X86, the "adc"
   /// instruction adds two register operands and adds the carry bit in from the
   /// flags register.  In this case, the instruction is marked as implicitly
   /// reading the flags.  Likewise, the variable shift instruction on X86 is
   /// marked as implicitly reading the 'CL' register, which it always does.
   ArrayRef<MCPhysReg> implicit_uses() const {
-    return {ImplicitOps, NumImplicitUses};
+    auto ImplicitOps = reinterpret_cast<const MCPhysReg *>(this + Opcode + 1);
+    return {ImplicitOps + ImplicitOffset, NumImplicitUses};
   }
 
   /// Return a list of registers that are potentially written by any
   /// instance of this machine instruction.  For example, on X86, many
   /// instructions implicitly set the flags register.  In this case, they are
   /// marked as setting the FLAGS.  Likewise, many instructions always deposit
   /// their result in a physical register.  For example, the X86 divide
   /// instruction always deposits the quotient and remainder in the EAX/EDX
   /// registers.  For that instruction, this will return a list containing the
   /// EAX/EDX/EFLAGS registers.
   ArrayRef<MCPhysReg> implicit_defs() const {
-    return {ImplicitOps + NumImplicitUses, NumImplicitDefs};
+    auto ImplicitOps = reinterpret_cast<const MCPhysReg *>(this + Opcode + 1);
+    return {ImplicitOps + ImplicitOffset + NumImplicitUses, NumImplicitDefs};
   }
 
   /// Return true if this instruction implicitly
   /// uses the specified physical register.
   bool hasImplicitUseOfPhysReg(unsigned Reg) const {
     return is_contained(implicit_uses(), Reg);
   }
 

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 #include <utility>
 #include <vector>
 
 #define DEBUG_TYPE "asm-parser"
 
 using namespace llvm;
 
 namespace llvm {
-extern const MCInstrDesc ARMInsts[];
+extern const MCInstrDesc ARMDescs[];
 } // end namespace llvm
 
 namespace {
 
 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
 
 static cl::opt<ImplicitItModeTy> ImplicitItMode(
     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
void addVPTPredROperands(MCInst &Inst, unsigned N) const {
     assert(N == 4 && "Invalid number of operands!");
     addVPTPredNOperands(Inst, N-1);
     unsigned RegNum;
     if (getVPTPred() == ARMVCC::None) {
       RegNum = 0;
     } else {
       unsigned NextOpIndex = Inst.getNumOperands();
       const MCInstrDesc &MCID =
-          ARMInsts[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()];
+          ARMDescs[ARM::INSTRUCTION_LIST_END - 1 - Inst.getOpcode()];
       int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
       assert(TiedOp >= 0 &&
              "Inactive register in vpred_r is not tied to an output!");
       RegNum = Inst.getOperand(TiedOp).getReg();
     }
     Inst.addOperand(MCOperand::createReg(RegNum));
   }
 

llvm/unittests/CodeGen/MachineInstrTest.cpp

TEST(IsIdenticalToTest, DifferentDefs) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   unsigned short NumOps = 2;
   unsigned char NumDefs = 1;
   MCOperandInfo OpInfo[] = {
       {0, 0, MCOI::OPERAND_REGISTER, 0},
       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
-  MCInstrDesc MCID = {0, NumOps,  NumDefs, 0,
-                      0, 0,       0,       1ULL << MCID::HasOptionalDef,
-                      0, nullptr, OpInfo};
+  MCInstrDesc MCID = {
+      0, NumOps, NumDefs, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef,
+      0, OpInfo};
 
   // Create two MIs with different virtual reg defs and the same uses.
   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
   unsigned VirtualDef2 = -43;
   unsigned VirtualUse = -44;
 
   auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   unsigned short NumOps = 2;
   unsigned char NumDefs = 1;
   MCOperandInfo OpInfo[] = {
       {0, 0, MCOI::OPERAND_REGISTER, 0},
       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
-  MCInstrDesc MCID = {0, NumOps,  NumDefs, 0,
-                      0, 0,       0,       1ULL << MCID::HasOptionalDef,
-                      0, nullptr, OpInfo};
+  MCInstrDesc MCID = {
+      0, NumOps, NumDefs, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef,
+      0, OpInfo};
 
   // Define a series of instructions with different kinds of operands and make
   // sure that the hash function is consistent with isEqual for various
   // combinations of them.
   unsigned VirtualDef1 = -42;
   unsigned VirtualDef2 = -43;
   unsigned VirtualReg = -44;
   unsigned SentinelReg = 0;

 }
 
 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
-  MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, 0, 0, nullptr, &OpInfo};
+  MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, &OpInfo};
 
   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
   DISubprogram *DIS = DISubprogram::getDistinct(
       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
       DISubprogram::SPFlagZero, nullptr);
   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
   DebugLoc DL(DIL);
   MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);

 }
 
 TEST(MachineInstrSpan, DistanceBegin) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
 
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
 
   auto MII = MBB->begin();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrSpan, DistanceEnd) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
 
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
 
   auto MII = MBB->end();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrExtraInfo, AddExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrExtraInfo, AddExtraInfo) {
   ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
   ASSERT_TRUE(MI->getPCSections() == PCS);
 }
 
 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
   ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
   ASSERT_TRUE(MI->getPCSections() == PCS);
 }
 
 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrDebugValue, AddDebugValueOperand) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   for (const unsigned short Opcode :
        {TargetOpcode::DBG_VALUE, TargetOpcode::DBG_VALUE_LIST,
         TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI,
         TargetOpcode::DBG_LABEL}) {
     const MCInstrDesc MCID = {
-        Opcode, 0,
-        0,      0,
-        0,      0,
-        0,      (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
-        0,      nullptr,
-        nullptr};
+        Opcode, 0,      0,
+        0,      0,      0,
+        0,      0,      (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
+        0,      nullptr};
 
     auto *MI = MF->CreateMachineInstr(MCID, DebugLoc());
     MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false));
 
     MI->addOperand(*MF, MachineOperand::CreateImm(0));
     MI->getOperand(1).ChangeToRegister(0, false);
 
     ASSERT_TRUE(MI->getOperand(0).isDebug());
TEST(MachineInstrBuilder, BuildMI) {
   DebugLoc DL(DI);
   MIMetadata MIMD(DL, PCS);
   EXPECT_EQ(MIMD.getDL(), DL);
   EXPECT_EQ(MIMD.getPCSections(), PCS);
   // Check common BuildMI() overloads propagate MIMetadata.
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
   EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->instr_end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, *MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, &*MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(MBB, MIMD, MCID), HasMIMetadata(MIMD));
 }
 
 static_assert(std::is_trivially_copyable_v<MCOperand>, "trivially copyable");
 
 } // end namespace

llvm/unittests/CodeGen/RegAllocScoreTest.cpp

 #define MOCK_INSTR_ID(ID, IGNORE, IGNORE2) ID,
   MOCK_INSTR(MOCK_INSTR_ID)
 #undef MOCK_INSTR_ID
       TotalMockInstrs
 };
 
 const std::array<MCInstrDesc, MockInstrId::TotalMockInstrs> MockInstrDescs{{
 #define MOCK_SPEC(IGNORE, OPCODE, FLAGS)                                       \
-  {OPCODE, 0, 0, 0, 0, 0, 0, FLAGS, 0, nullptr, nullptr},
+  {OPCODE, 0, 0, 0, 0, 0, 0, 0, FLAGS, 0, nullptr},
     MOCK_INSTR(MOCK_SPEC)
 #undef MOCK_SPEC
 }};
 
 MachineInstr *createMockCopy(MachineFunction &MF) {
   return MF.CreateMachineInstr(MockInstrDescs[MockInstrId::Copy], DebugLoc());
 }
 

llvm/utils/TableGen/InstrInfoEmitter.cpp

private:
 
   // Operand information.
   void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
   std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
 };
 
 } // end anonymous namespace
 
-static void PrintDefList(const std::vector<Record *> &Uses, unsigned Num,
-                         raw_ostream &OS) {
-  OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
-  for (auto [Idx, U] : enumerate(Uses))
-    OS << (Idx ? ", " : "") << getQualifiedName(U);
-  OS << " };\n";
-}
-
 //===----------------------------------------------------------------------===//
 // Operand Info Emission.
 //===----------------------------------------------------------------------===//
 
 std::vector<std::string>
 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
   std::vector<std::string> Result;
 

 }
 
 void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
                                        OperandInfoMapTy &OperandInfoIDs) {
   // ID #0 is for no operand info.
   unsigned OperandListNum = 0;
   OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
 
-  OS << "\n";
   const CodeGenTarget &Target = CDP.getTargetInfo();
   for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
     std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
     unsigned &N = OperandInfoIDs[OperandInfo];
     if (N != 0) continue;
 
     N = ++OperandListNum;
     OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";

 // Main Output.
 //===----------------------------------------------------------------------===//
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(raw_ostream &OS) {
   emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
   emitEnums(OS);
 
-  OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
-  OS << "#undef GET_INSTRINFO_MC_DESC\n";
-
-  OS << "namespace llvm {\n\n";
-
   CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = std::string(Target.getName());
   Record *InstrInfo = Target.getInstructionSet();
 
-  // Keep track of all of the def lists we have emitted already.
+  // Collect all of the instruction's implicit uses and defs.
+  Records.startTimer("Collect uses/defs");
   std::map<std::vector<Record*>, unsigned> EmittedLists;
-  unsigned ListNumber = 0;
-
-  // Emit all of the instruction's implicit uses and defs.
-  Records.startTimer("Emit uses/defs");
+  std::vector<std::vector<Record *>> ImplicitLists;
+  unsigned ImplicitListSize = 0;
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
     std::vector<Record *> ImplicitOps = II->ImplicitUses;
     llvm::append_range(ImplicitOps, II->ImplicitDefs);
-    if (!ImplicitOps.empty()) {
-      unsigned &IL = EmittedLists[ImplicitOps];
-      if (!IL) {
-        IL = ++ListNumber;
-        PrintDefList(ImplicitOps, IL, OS);
-      }
+    if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
+      ImplicitLists.push_back(ImplicitOps);
+      ImplicitListSize += ImplicitOps.size();
     }
   }
 
-  OperandInfoMapTy OperandInfoIDs;
+  ArrayRef<const CodeGenInstruction *> NumberedInstructions =
+      Target.getInstructionsByEnumValue();
+  OS << "#if defined(GET_INSTRINFO_MC_DESC) || "
+        "defined(GET_INSTRINFO_CTOR_DTOR)\n";
+  OS << "namespace llvm {\n\n";
+
+  OS << "struct " << TargetName << "InstrTable {\n";
+  OS << "  MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
+  OS << "  static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "
+        "\"Unwanted padding between Insts and ImplicitOps\");\n";
+  OS << "  MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U) << "];\n";
+  OS << "};\n\n";
+
+  OS << "} // end namespace llvm\n";
+  OS << "#endif // defined(GET_INSTRINFO_MC_DESC) || "
+        "defined(GET_INSTRINFO_CTOR_DTOR)\n\n";
+
+  OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
+  OS << "#undef GET_INSTRINFO_MC_DESC\n";
+  OS << "namespace llvm {\n\n";
 
   // Emit all of the operand info records.
   Records.startTimer("Emit operand info");
+  OperandInfoMapTy OperandInfoIDs;
   EmitOperandInfo(OS, OperandInfoIDs);
+  OS << "\n";
 
   // Emit all of the MCInstrDesc records in reverse ENUM ordering.
   Records.startTimer("Emit InstrDesc records");
-  OS << "\nextern const MCInstrDesc " << TargetName << "Insts[] = {\n";
-  ArrayRef<const CodeGenInstruction*> NumberedInstructions =
-    Target.getInstructionsByEnumValue();
-
+  OS << "extern const " << TargetName << "InstrTable " << TargetName
+     << "Descs = {\n  {\n";
   SequenceToOffsetTable<std::string> InstrNames;
   unsigned Num = NumberedInstructions.size();
   for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
     // Keep a list of the instruction names.
     InstrNames.add(std::string(Inst->TheDef->getName()));
     // Emit the record into the table.
     emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoIDs, OS);
   }
-  OS << "};\n\n";
+
+  OS << "  }, {\n";
+
+  // Emit all of the instruction's implicit uses and defs.
+  Records.startTimer("Emit uses/defs");
+  for (auto &List : ImplicitLists) {
+    OS << "    /* " << EmittedLists[List] << " */";
+    for (auto &Reg : List)
+      OS << ' ' << getQualifiedName(Reg) << ',';
+    OS << '\n';
+  }
+
+  OS << "  }\n};\n\n";
 
   // Emit the array of instruction names.
   Records.startTimer("Emit instruction names");
   InstrNames.layout();
   InstrNames.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
                                           "InstrNameData[]");
 
   OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
if (HasComplexDeprecationInfos) {
     }
     OS << "\n};\n\n";
   }
 
   // MCInstrInfo initialization routine.
   Records.startTimer("Emit initialization routine");
   OS << "static inline void Init" << TargetName
      << "MCInstrInfo(MCInstrInfo *II) {\n";
-  OS << "  II->InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
+  OS << "  II->InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
      << "InstrNameIndices, " << TargetName << "InstrNameData, ";
   if (HasDeprecationFeatures)
     OS << TargetName << "InstrDeprecationFeatures, ";
   else
     OS << "nullptr, ";
   if (HasComplexDeprecationInfos)
     OS << TargetName << "InstrComplexDeprecationInfos, ";
   else
void InstrInfoEmitter::run(raw_ostream &OS) {
   OS << "#undef GET_INSTRINFO_HELPERS\n\n";
   emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ true);
   OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
 
   OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
   OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
 
   OS << "namespace llvm {\n";
-  OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n";
+  OS << "extern const " << TargetName << "InstrTable " << TargetName
+     << "Descs;\n";
   OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
   OS << "extern const char " << TargetName << "InstrNameData[];\n";
   if (HasDeprecationFeatures)
     OS << "extern const uint8_t " << TargetName
        << "InstrDeprecationFeatures[];\n";
   if (HasComplexDeprecationInfos)
     OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
        << "InstrComplexDeprecationInfos[];\n";
   OS << ClassName << "::" << ClassName
      << "(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned "
         "CatchRetOpcode, unsigned ReturnOpcode)\n"
      << "  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, "
         "ReturnOpcode) {\n"
-     << "  InitMCInstrInfo(" << TargetName << "Insts, " << TargetName
+     << "  InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
      << "InstrNameIndices, " << TargetName << "InstrNameData, ";
   if (HasDeprecationFeatures)
     OS << TargetName << "InstrDeprecationFeatures, ";
   else
     OS << "nullptr, ";
   if (HasComplexDeprecationInfos)
     OS << TargetName << "InstrComplexDeprecationInfos, ";
   else
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   const OperandInfoMapTy &OpInfo,
                                   raw_ostream &OS) {
   int MinOperands = 0;
   if (!Inst.Operands.empty())
     // Each logical operand can be multiple MI operands.
     MinOperands = Inst.Operands.back().MIOperandNo +
                   Inst.Operands.back().MINumOperands;
 
-  OS << "  { ";
-  OS << Num << ",\t" << MinOperands << ",\t"
-     << Inst.Operands.NumDefs << ",\t"
+  OS << "    { ";
+  OS << Num << ",\t" << MinOperands << ",\t" << Inst.Operands.NumDefs << ",\t"
      << Inst.TheDef->getValueAsInt("Size") << ",\t"
-     << SchedModels.getSchedClassIdx(Inst) << ",\t"
-     << Inst.ImplicitUses.size() << ",\t"
-     << Inst.ImplicitDefs.size() << ",\t0";
+     << SchedModels.getSchedClassIdx(Inst) << ",\t";
+
+  // Emit the implicit use/def list...
+  OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
+  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
+  llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
+  OS << EmittedLists[ImplicitOps] << ",\t0";
 
   CodeGenTarget &Target = CDP.getTargetInfo();
 
   // Emit all of the target independent flags...
   if (Inst.isPreISelOpcode)    OS << "|(1ULL<<MCID::PreISelOpcode)";
   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
   if (Inst.isMeta)             OS << "|(1ULL<<MCID::Meta)";
   if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
     else
       PrintFatalError(Inst.TheDef->getLoc(),
                       "Invalid TSFlags bit in " + Inst.TheDef->getName());
   }
   OS << ", 0x";
   OS.write_hex(Value);
   OS << "ULL, ";
 
-  // Emit the implicit use/def list...
-  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
-  llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
-  if (ImplicitOps.empty())
-    OS << "nullptr, ";
-  else
-    OS << "ImplicitList" << EmittedLists[ImplicitOps] << ", ";
-
   // Emit the operand info.
   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
     OS << "nullptr";
   else
     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
 
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";