[MC] Store number of implicit operands in MCInstrDesc. NFC.

[foad]

Summary

Combine the implicit uses and defs lists into a single list of uses
followed by defs. Instead of 0-terminating the list, store the number
of uses and defs. This avoids having to scan the whole list to find the
length and removes one pointer from MCInstrDesc (although it does not
get any smaller due to alignment issues).

Remove the old accessor methods getImplicitUses, getNumImplicitUses,
getImplicitDefs and getNumImplicitDefs as all clients are using the new
implicit_uses and implicit_defs.

[arsenm]

llvm/include/llvm/MC/MCInstrDesc.h

212

Could these be reordered to avoid the alignment padding?

[foad]

llvm/include/llvm/MC/MCInstrDesc.h

212

You could avoid some internal padding but I don't think you could make the struct any smaller overall.

I didn't worry too much about the exact layout of this struct until the end of the whole stack of patches.

[arsenm]

llvm/include/llvm/MC/MCInstrDesc.h

212

Probably could force the 64-bit fields to 4-byte alignment and see how compile time benchmarks look

[foad]

llvm/include/llvm/MC/MCInstrDesc.h

212

The final layout is 24 bytes of which 22 are used, so it didn't seem worth playing that kind of trick.

[arsenm]

llvm/utils/TableGen/InstrInfoEmitter.cpp

909–910

Does this really need to generate a copy of vector for every instruction/

[barannikov88]

llvm/utils/TableGen/InstrInfoEmitter.cpp

1187

I understand that the intent is to reduce code duplication, but appending Defs to Uses looks awkward.
Can it use llvm::concat_range?

[foad]

llvm/utils/TableGen/InstrInfoEmitter.cpp

909–910

Did you have an alternative in mind? Change getValueAsListOfDefs to append to an existing vector?

Or the EmittedLists map key could be a pair of vectors instead of a vector - but I have no idea what that would do to the overall efficiency of this code.

Would it help to move from Defs instead of copy from it?

[barannikov88]

llvm/utils/TableGen/InstrInfoEmitter.cpp

909–910

ArrayRef Uses = II->ImplicitUses; should work.

[barannikov88]

llvm/utils/TableGen/InstrInfoEmitter.cpp

909–910

PrintDefList accepts const std::vector<Record*> &; that should be changed to ArrayRef too (otherwise the vector will be implicitly constructed).
Unfortunately, ArrayRef::operator std::vector<T>() is not marked as explicit to catch this.

[foad]

Rebase

[foad]

llvm/utils/TableGen/InstrInfoEmitter.cpp

909–910

I've changed this code to use II->ImplicitUses and II->ImplicitDefs (thanks!) in rG2eef8759152c7aba837addd8e90fda73c9c1f63e and rebased.

[barannikov88]

llvm/utils/TableGen/InstrInfoEmitter.cpp

117

This is confusing.
The name suggests it prints defs, the parameter name is Uses, but it really prints both.

1187

Never mind, the suggestion won't work since EmittedLists is keyed by std::vector, i.e. it has to be constructed anyway.

[barannikov88]

llvm/utils/TableGen/InstrInfoEmitter.cpp

120–122

(Nit) could also use structured bindings: for (auto [Idx, Op] : enumerate(Ops))

[foad]

llvm/utils/TableGen/InstrInfoEmitter.cpp

117

Yes, but it goes away in D142218 :)

[barannikov88]

LGTM

[gulfem]

BOLT seems like using the removed getImplicitUses method(). That's why we started seeing the following failure:

[3786/4445](41) Building CXX object tools/bolt/lib/Passes/CMakeFiles/LLVMBOLTPasses.dir/LivenessAnalysis.cpp.o
In file included from /opt/s/w/ir/x/w/llvm-llvm-project/bolt/lib/Passes/LivenessAnalysis.cpp:9:
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:145:30: error: no member named 'getImplicitUses' in 'llvm::MCInstrDesc'
      for (auto I = InstInfo.getImplicitUses(),
                    ~~~~~~~~ ^
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:146:30: error: no member named 'getImplicitUses' in 'llvm::MCInstrDesc'
                E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses();
                    ~~~~~~~~ ^
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:146:59: error: no member named 'getNumImplicitUses' in 'llvm::MCInstrDesc'
                E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses();

https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8791052753995739793/+/u/clang/build/stdout

[foad]

In D142216#4078359, @gulfem wrote:

BOLT seems like using the removed getImplicitUses method(). That's why we started seeing the following failure:

[3786/4445](41) Building CXX object tools/bolt/lib/Passes/CMakeFiles/LLVMBOLTPasses.dir/LivenessAnalysis.cpp.o
In file included from /opt/s/w/ir/x/w/llvm-llvm-project/bolt/lib/Passes/LivenessAnalysis.cpp:9:
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:145:30: error: no member named 'getImplicitUses' in 'llvm::MCInstrDesc'
      for (auto I = InstInfo.getImplicitUses(),
                    ~~~~~~~~ ^
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:146:30: error: no member named 'getImplicitUses' in 'llvm::MCInstrDesc'
                E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses();
                    ~~~~~~~~ ^
/opt/s/w/ir/x/w/llvm-llvm-project/bolt/include/bolt/Passes/LivenessAnalysis.h:146:59: error: no member named 'getNumImplicitUses' in 'llvm::MCInstrDesc'
                E = InstInfo.getImplicitUses() + InstInfo.getNumImplicitUses();

https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8791052753995739793/+/u/clang/build/stdout

Sorry. Can you please try converting this code to the for (I : implicit_uses()) style? If not I will do it tomorrow.

[Amir]

@foad: the build error was flagged by pre-merge checks:
https://buildkite.com/llvm-project/premerge-checks/builds/132223#0185e040-b660-4955-8454-915e5c5800fa/6-10847

I'll fix it up but please don't ignore the signal as it breaks BOLT in upstream.

[Amir]

Was fixed in 7557b83aa543e1e3f0c820ecbb14721d4e80a809

[gulfem]

In D142216#4078574, @Amir wrote:

Was fixed in 7557b83aa543e1e3f0c820ecbb14721d4e80a809

Thanks for the update @Amir!

[foad]

In D142216#4078569, @Amir wrote:

@foad: the build error was flagged by pre-merge checks:
https://buildkite.com/llvm-project/premerge-checks/builds/132223#0185e040-b660-4955-8454-915e5c5800fa/6-10847

I'll fix it up but please don't ignore the signal as it breaks BOLT in upstream.

Thanks and sorry, will try to pay more attention to the pre-merge checks.

llvm/include/llvm/MC/MCInstrDesc.h

public:
   // the <Target>Insts table because they rely on knowing their own address to
   // find other information elsewhere in the same table.
 
   unsigned short Opcode;         // The opcode number
   unsigned short NumOperands;    // Num of args (may be more if variable_ops)
   unsigned char NumDefs;         // Num of args that are definitions
   unsigned char Size;            // Number of bytes in encoding.
   unsigned short SchedClass;     // enum identifying instr sched class
+  unsigned char NumImplicitUses; // Num of regs implicitly used
+  unsigned char NumImplicitDefs; // Num of regs implicitly defined
   uint64_t Flags;                // Flags identifying machine instr class
   uint64_t TSFlags;              // Target Specific Flag values
-  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
-  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
+  const MCPhysReg *ImplicitOps;  // List of implicit uses followed by defs
   const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
 
   /// Returns the value of the specified operand constraint if
   /// it is present. Returns -1 if it is not present.
   int getOperandConstraint(unsigned OpNum,
                            MCOI::OperandConstraint Constraint) const {
     if (OpNum < NumOperands &&
         (operands()[OpNum].Constraints & (1 << Constraint))) {
public:
   }
 
   /// Return a list of registers that are potentially read by any
   /// instance of this machine instruction.  For example, on X86, the "adc"
   /// instruction adds two register operands and adds the carry bit in from the
   /// flags register.  In this case, the instruction is marked as implicitly
   /// reading the flags.  Likewise, the variable shift instruction on X86 is
   /// marked as implicitly reading the 'CL' register, which it always does.
-  ///
-  /// This method returns null if the instruction has no implicit uses.
-  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
   ArrayRef<MCPhysReg> implicit_uses() const {
-    return {ImplicitUses, getNumImplicitUses()};
-  }
-
-  /// Return the number of implicit uses this instruction has.
-  unsigned getNumImplicitUses() const {
-    if (!ImplicitUses)
-      return 0;
-    unsigned i = 0;
-    for (; ImplicitUses[i]; ++i) /*empty*/
-      ;
-    return i;
+    return {ImplicitOps, NumImplicitUses};
   }
 
   /// Return a list of registers that are potentially written by any
   /// instance of this machine instruction.  For example, on X86, many
   /// instructions implicitly set the flags register.  In this case, they are
   /// marked as setting the FLAGS.  Likewise, many instructions always deposit
   /// their result in a physical register.  For example, the X86 divide
   /// instruction always deposits the quotient and remainder in the EAX/EDX
   /// registers.  For that instruction, this will return a list containing the
   /// EAX/EDX/EFLAGS registers.
-  ///
-  /// This method returns null if the instruction has no implicit defs.
-  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
   ArrayRef<MCPhysReg> implicit_defs() const {
-    return {ImplicitDefs, getNumImplicitDefs()};
-  }
-
-  /// Return the number of implicit defs this instruct has.
-  unsigned getNumImplicitDefs() const {
-    if (!ImplicitDefs)
-      return 0;
-    unsigned i = 0;
-    for (; ImplicitDefs[i]; ++i) /*empty*/
-      ;
-    return i;
+    return {ImplicitOps + NumImplicitUses, NumImplicitDefs};
   }
 
   /// Return true if this instruction implicitly
   /// uses the specified physical register.
   bool hasImplicitUseOfPhysReg(unsigned Reg) const {
     return is_contained(implicit_uses(), Reg);
   }
 

llvm/unittests/CodeGen/MachineInstrTest.cpp

TEST(IsIdenticalToTest, DifferentDefs) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   unsigned short NumOps = 2;
   unsigned char NumDefs = 1;
   MCOperandInfo OpInfo[] = {
       {0, 0, MCOI::OPERAND_REGISTER, 0},
       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
-  MCInstrDesc MCID = {
-      0, NumOps,  NumDefs, 0,     0, 1ULL << MCID::HasOptionalDef,
-      0, nullptr, nullptr, OpInfo};
+  MCInstrDesc MCID = {0, NumOps,  NumDefs, 0,
+                      0, 0,       0,       1ULL << MCID::HasOptionalDef,
+                      0, nullptr, OpInfo};
 
   // Create two MIs with different virtual reg defs and the same uses.
   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
   unsigned VirtualDef2 = -43;
   unsigned VirtualUse = -44;
 
   auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   unsigned short NumOps = 2;
   unsigned char NumDefs = 1;
   MCOperandInfo OpInfo[] = {
       {0, 0, MCOI::OPERAND_REGISTER, 0},
       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
-  MCInstrDesc MCID = {
-      0, NumOps,  NumDefs, 0,     0, 1ULL << MCID::HasOptionalDef,
-      0, nullptr, nullptr, OpInfo};
+  MCInstrDesc MCID = {0, NumOps,  NumDefs, 0,
+                      0, 0,       0,       1ULL << MCID::HasOptionalDef,
+                      0, nullptr, OpInfo};
 
   // Define a series of instructions with different kinds of operands and make
   // sure that the hash function is consistent with isEqual for various
   // combinations of them.
   unsigned VirtualDef1 = -42;
   unsigned VirtualDef2 = -43;
   unsigned VirtualReg = -44;
   unsigned SentinelReg = 0;

 }
 
 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
-  MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo};
+  MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, 0, 0, nullptr, &OpInfo};
 
   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
   DISubprogram *DIS = DISubprogram::getDistinct(
       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
       DISubprogram::SPFlagZero, nullptr);
   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
   DebugLoc DL(DIL);
   MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);

 }
 
 TEST(MachineInstrSpan, DistanceBegin) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
 
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
 
   auto MII = MBB->begin();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrSpan, DistanceEnd) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
 
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
 
   auto MII = MBB->end();
   MachineInstrSpan MIS(MII, MBB);
   ASSERT_TRUE(MIS.empty());
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   MBB->insert(MII, MI);
   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
 }
 
 TEST(MachineInstrExtraInfo, AddExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrExtraInfo, AddExtraInfo) {
   ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
   ASSERT_TRUE(MI->getPCSections() == PCS);
 }
 
 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
   ASSERT_TRUE(MI->getHeapAllocMarker() == HAM);
   ASSERT_TRUE(MI->getPCSections() == PCS);
 }
 
 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
   LLVMContext Ctx;
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
 
   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
   auto MAI = MCAsmInfo();
   auto MC = createMCContext(&MAI);
   auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
                                       MachineMemOperand::MOLoad, 8, Align(8));
   SmallVector<MachineMemOperand *, 2> MMOs;
   MMOs.push_back(MMO);
TEST(MachineInstrDebugValue, AddDebugValueOperand) {
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
 
   for (const unsigned short Opcode :
        {TargetOpcode::DBG_VALUE, TargetOpcode::DBG_VALUE_LIST,
         TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI,
         TargetOpcode::DBG_LABEL}) {
     const MCInstrDesc MCID = {
-        Opcode, 0,       0,
-        0,      0,       (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
-        0,      nullptr, nullptr,
+        Opcode, 0,
+        0,      0,
+        0,      0,
+        0,      (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
+        0,      nullptr,
         nullptr};
 
     auto *MI = MF->CreateMachineInstr(MCID, DebugLoc());
     MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false));
 
     MI->addOperand(*MF, MachineOperand::CreateImm(0));
     MI->getOperand(1).ChangeToRegister(0, false);
 
TEST(MachineInstrBuilder, BuildMI) {
   DebugLoc DL(DI);
   MIMetadata MIMD(DL, PCS);
   EXPECT_EQ(MIMD.getDL(), DL);
   EXPECT_EQ(MIMD.getPCSections(), PCS);
   // Check common BuildMI() overloads propagate MIMetadata.
   Module Mod("Module", Ctx);
   auto MF = createMachineFunction(Ctx, Mod);
   auto MBB = MF->CreateMachineBasicBlock();
-  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
+  MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr, nullptr};
   EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, MBB->instr_end(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, *MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(*MBB, &*MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD));
   EXPECT_THAT(BuildMI(MBB, MIMD, MCID), HasMIMetadata(MIMD));
 }
 
 static_assert(std::is_trivially_copyable_v<MCOperand>, "trivially copyable");
 
 } // end namespace

llvm/unittests/CodeGen/RegAllocScoreTest.cpp

 #define MOCK_INSTR_ID(ID, IGNORE, IGNORE2) ID,
   MOCK_INSTR(MOCK_INSTR_ID)
 #undef MOCK_INSTR_ID
       TotalMockInstrs
 };
 
 const std::array<MCInstrDesc, MockInstrId::TotalMockInstrs> MockInstrDescs{{
 #define MOCK_SPEC(IGNORE, OPCODE, FLAGS)                                       \
-  {OPCODE, 0, 0, 0, 0, FLAGS, 0, nullptr, nullptr, nullptr},
+  {OPCODE, 0, 0, 0, 0, 0, 0, FLAGS, 0, nullptr, nullptr},
     MOCK_INSTR(MOCK_SPEC)
 #undef MOCK_SPEC
 }};
 
 MachineInstr *createMockCopy(MachineFunction &MF) {
   return MF.CreateMachineInstr(MockInstrDescs[MockInstrId::Copy], DebugLoc());
 }
 

llvm/utils/TableGen/InstrInfoEmitter.cpp

private:
 
   // Operand information.
   void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
   std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
 };
 
 } // end anonymous namespace
 
 static void PrintDefList(const std::vector<Record*> &Uses,
                          unsigned Num, raw_ostream &OS) {
   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
-  for (Record *U : Uses)
-    OS << getQualifiedName(U) << ", ";
-  OS << "0 };\n";
+  for (auto [Idx, U] : enumerate(Uses))
+    OS << (Idx ? ", " : "") << getQualifiedName(U);
+  OS << " };\n";
 }
 
 //===----------------------------------------------------------------------===//
 // Operand Info Emission.
 //===----------------------------------------------------------------------===//
 
 std::vector<std::string>
 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
void InstrInfoEmitter::run(raw_ostream &OS) {
   Record *InstrInfo = Target.getInstructionSet();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
 
   // Emit all of the instruction's implicit uses and defs.
   Records.startTimer("Emit uses/defs");
   for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
-    if (!II->ImplicitUses.empty()) {
-      unsigned &IL = EmittedLists[II->ImplicitUses];
-      if (!IL) {
-        IL = ++ListNumber;
-        PrintDefList(II->ImplicitUses, IL, OS);
-      }
-    }
-    if (!II->ImplicitDefs.empty()) {
-      unsigned &IL = EmittedLists[II->ImplicitDefs];
+    std::vector<Record *> ImplicitOps = II->ImplicitUses;
+    llvm::append_range(ImplicitOps, II->ImplicitDefs);
+    if (!ImplicitOps.empty()) {
+      unsigned &IL = EmittedLists[ImplicitOps];
       if (!IL) {
         IL = ++ListNumber;
-        PrintDefList(II->ImplicitDefs, IL, OS);
+        PrintDefList(ImplicitOps, IL, OS);
       }
     }
   }
 
   OperandInfoMapTy OperandInfoIDs;
 
   // Emit all of the operand info records.
   Records.startTimer("Emit operand info");
if (!Inst.Operands.empty())
     // Each logical operand can be multiple MI operands.
     MinOperands = Inst.Operands.back().MIOperandNo +
                   Inst.Operands.back().MINumOperands;
 
   OS << "  { ";
   OS << Num << ",\t" << MinOperands << ",\t"
      << Inst.Operands.NumDefs << ",\t"
      << Inst.TheDef->getValueAsInt("Size") << ",\t"
-     << SchedModels.getSchedClassIdx(Inst) << ",\t0";
+     << SchedModels.getSchedClassIdx(Inst) << ",\t"
+     << Inst.ImplicitUses.size() << ",\t"
+     << Inst.ImplicitDefs.size() << ",\t0";
 
   CodeGenTarget &Target = CDP.getTargetInfo();
 
   // Emit all of the target independent flags...
   if (Inst.isPreISelOpcode)    OS << "|(1ULL<<MCID::PreISelOpcode)";
   if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
   if (Inst.isMeta)             OS << "|(1ULL<<MCID::Meta)";
   if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
     else
       PrintFatalError(Inst.TheDef->getLoc(),
                       "Invalid TSFlags bit in " + Inst.TheDef->getName());
   }
   OS << ", 0x";
   OS.write_hex(Value);
   OS << "ULL, ";
 
-  // Emit the implicit uses and defs lists...
-  if (Inst.ImplicitUses.empty())
-    OS << "nullptr, ";
-  else
-    OS << "ImplicitList" << EmittedLists[Inst.ImplicitUses] << ", ";
-
-  if (Inst.ImplicitDefs.empty())
+  // Emit the implicit use/def list...
+  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
+  llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
+  if (ImplicitOps.empty())
     OS << "nullptr, ";
   else
-    OS << "ImplicitList" << EmittedLists[Inst.ImplicitDefs] << ", ";
+    OS << "ImplicitList" << EmittedLists[ImplicitOps] << ", ";
 
   // Emit the operand info.
   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
     OS << "nullptr";
   else
     OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;