[NFC][AArch64] Use 'i' to encode the offset form of load/store.

[HsiangKai]

Summary

STG, STZG, ST2G, STZ2G are the exceptions to append 'Offset' to name the
offset format of load/store instructions. All other load/store
instructions use 'i' as the appendix. If there is no special reason to
do so, we should make the naming consistent.

[olista01]

LGTM

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

while (LastI != Begin) {
     if (LastI->isTransient())
       continue;
     if (!LastI->getFlag(MachineInstr::FrameDestroy))
       break;
   }
   switch (LastI->getOpcode()) {
   case AArch64::STGloop:
   case AArch64::STZGloop:
-  case AArch64::STGOffset:
-  case AArch64::STZGOffset:
-  case AArch64::ST2GOffset:
-  case AArch64::STZ2GOffset:
+  case AArch64::STGi:
+  case AArch64::STZGi:
+  case AArch64::ST2Gi:
+  case AArch64::STZ2Gi:
     return false;
   default:
     return true;
   }
   llvm_unreachable("unreachable");
 }
 
 // Given a load or a store instruction, generate an appropriate unwinding SEH
if (BaseRegOffsetBytes < kMinOffset ||
     BaseRegOffsetBytes = 0;
   }
 
   MachineInstr *LastI = nullptr;
   while (Size) {
     int64_t InstrSize = (Size > 16) ? 32 : 16;
     unsigned Opcode =
         InstrSize == 16
-            ? (ZeroData ? AArch64::STZGOffset : AArch64::STGOffset)
-            : (ZeroData ? AArch64::STZ2GOffset : AArch64::ST2GOffset);
+            ? (ZeroData ? AArch64::STZGi : AArch64::STGi)
+            : (ZeroData ? AArch64::STZ2Gi : AArch64::ST2Gi);
     assert(BaseRegOffsetBytes % 16 == 0);
     MachineInstr *I = BuildMI(*MBB, InsertI, DL, TII->get(Opcode))
                           .addReg(AArch64::SP)
                           .addReg(BaseReg)
                           .addImm(BaseRegOffsetBytes / 16)
                           .setMemRefs(CombinedMemRefs);
     // A store to [BaseReg, #0] should go last for an opportunity to fold the
     // final SP adjustment in the epilogue.

 }
 
 bool isMergeableStackTaggingInstruction(MachineInstr &MI, int64_t &Offset,
                                         int64_t &Size, bool &ZeroData) {
   MachineFunction &MF = *MI.getParent()->getParent();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
   unsigned Opcode = MI.getOpcode();
-  ZeroData = (Opcode == AArch64::STZGloop || Opcode == AArch64::STZGOffset ||
-              Opcode == AArch64::STZ2GOffset);
+  ZeroData = (Opcode == AArch64::STZGloop || Opcode == AArch64::STZGi ||
+              Opcode == AArch64::STZ2Gi);
 
   if (Opcode == AArch64::STGloop || Opcode == AArch64::STZGloop) {
     if (!MI.getOperand(0).isDead() || !MI.getOperand(1).isDead())
       return false;
     if (!MI.getOperand(2).isImm() || !MI.getOperand(3).isFI())
       return false;
     Offset = MFI.getObjectOffset(MI.getOperand(3).getIndex());
     Size = MI.getOperand(2).getImm();
     return true;
   }
 
-  if (Opcode == AArch64::STGOffset || Opcode == AArch64::STZGOffset)
+  if (Opcode == AArch64::STGi || Opcode == AArch64::STZGi)
     Size = 16;
-  else if (Opcode == AArch64::ST2GOffset || Opcode == AArch64::STZ2GOffset)
+  else if (Opcode == AArch64::ST2Gi || Opcode == AArch64::STZ2Gi)
     Size = 32;
   else
     return false;
 
   if (MI.getOperand(0).getReg() != AArch64::SP || !MI.getOperand(1).isFI())
     return false;
 
   Offset = MFI.getObjectOffset(MI.getOperand(1).getIndex()) +
for (auto &MI : MBB) {
       if (MI.isDebugInstr())
         continue;
       int OpIndex;
       switch (MI.getOpcode()) {
       case AArch64::STGloop:
       case AArch64::STZGloop:
         OpIndex = 3;
         break;
-      case AArch64::STGOffset:
-      case AArch64::STZGOffset:
-      case AArch64::ST2GOffset:
-      case AArch64::STZ2GOffset:
+      case AArch64::STGi:
+      case AArch64::STZGi:
+      case AArch64::ST2Gi:
+      case AArch64::STZ2Gi:
         OpIndex = 1;
         break;
       default:
         OpIndex = -1;
       }
 
       int TaggedFI = -1;
       if (OpIndex >= 0) {

llvm/lib/Target/AArch64/AArch64InstrFormats.td

class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
 
   let Inst{20-12} = offset;
   let Inst{4-0}   = Rt;
 
   let mayStore = 1;
 }
 
 multiclass MemTagStore<bits<2> opc1, string insn> {
-  def Offset :
+  def i :
     BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
                     (outs), (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
   def PreIndex :
     BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
                     "$Rn = $wback",
                     (outs GPR64sp:$wback),
                     (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
   def PostIndex :
     BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
                     "$Rn = $wback",
                     (outs GPR64sp:$wback),
                     (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
 
   def : InstAlias<insn # "\t$Rt, [$Rn]",
-                  (!cast<Instruction>(NAME # "Offset") GPR64sp:$Rt, GPR64sp:$Rn, 0)>;
+                  (!cast<Instruction>(NAME # "i") GPR64sp:$Rt, GPR64sp:$Rn, 0)>;
 }
 
 //---
 // Exception generation
 //---
 
 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm,

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
   case AArch64::LDNF1SH_S_IMM:
   case AArch64::LDNF1SH_D_IMM:
   case AArch64::LDNF1W_IMM:
   case AArch64::LDNF1W_D_IMM:
   case AArch64::LDNF1SW_D_IMM:
   case AArch64::LDNF1D_IMM:
     return 3;
   case AArch64::ADDG:
-  case AArch64::STGOffset:
+  case AArch64::STGi:
   case AArch64::LDR_PXI:
   case AArch64::STR_PXI:
     return 2;
   }
 }
 
 bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
case AArch64::TAGPstack:
     Scale = TypeSize::Fixed(16);
     Width = 0;
     // TAGP with a negative offset turns into SUBP, which has a maximum offset
     // of 63 (not 64!).
     MinOffset = -63;
     MaxOffset = 63;
     break;
   case AArch64::LDG:
-  case AArch64::STGOffset:
-  case AArch64::STZGOffset:
+  case AArch64::STGi:
+  case AArch64::STZGi:
     Scale = TypeSize::Fixed(16);
     Width = 16;
     MinOffset = -256;
     MaxOffset = 255;
     break;
   case AArch64::STR_ZZZZXI:
   case AArch64::LDR_ZZZZXI:
     Scale = TypeSize::Scalable(16);
bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
   case AArch64::LDNF1SB_D_IMM:
     // A eighth vector worth of data
     // Width = mbytes * elements
     Scale = TypeSize::Scalable(2);
     Width = SVEMaxBytesPerVector / 8;
     MinOffset = -8;
     MaxOffset = 7;
     break;
-  case AArch64::ST2GOffset:
-  case AArch64::STZ2GOffset:
+  case AArch64::ST2Gi:
+  case AArch64::STZ2Gi:
     Scale = TypeSize::Fixed(16);
     Width = 32;
     MinOffset = -256;
     MaxOffset = 255;
     break;
   case AArch64::STGPi:
     Scale = TypeSize::Fixed(16);
     Width = 16;
int AArch64InstrInfo::getMemScale(unsigned Opc) {
   case AArch64::LDRQui:
   case AArch64::LDURQi:
   case AArch64::STRQui:
   case AArch64::STURQi:
   case AArch64::STRQpre:
   case AArch64::LDPQi:
   case AArch64::LDRQpre:
   case AArch64::STPQi:
-  case AArch64::STGOffset:
-  case AArch64::STZGOffset:
-  case AArch64::ST2GOffset:
-  case AArch64::STZ2GOffset:
+  case AArch64::STGi:
+  case AArch64::STZGi:
+  case AArch64::ST2Gi:
+  case AArch64::STZ2Gi:
   case AArch64::STGPi:
     return 16;
   }
 }
 
 bool AArch64InstrInfo::isPreLd(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 }
 
 defm STG   : MemTagStore<0b00, "stg">;
 defm STZG  : MemTagStore<0b01, "stzg">;
 defm ST2G  : MemTagStore<0b10, "st2g">;
 defm STZ2G : MemTagStore<0b11, "stz2g">;
 
 def : Pat<(AArch64stg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),
-          (STGOffset $Rn, $Rm, $imm)>;
+          (STGi $Rn, $Rm, $imm)>;
 def : Pat<(AArch64stzg GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),
-          (STZGOffset $Rn, $Rm, $imm)>;
+          (STZGi $Rn, $Rm, $imm)>;
 def : Pat<(AArch64st2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),
-          (ST2GOffset $Rn, $Rm, $imm)>;
+          (ST2Gi $Rn, $Rm, $imm)>;
 def : Pat<(AArch64stz2g GPR64sp:$Rn, (am_indexeds9s128 GPR64sp:$Rm, simm9s16:$imm)),
-          (STZ2GOffset $Rn, $Rm, $imm)>;
+          (STZ2Gi $Rn, $Rm, $imm)>;
 
 defm STGP     : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;
 def  STGPpre  : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;
 def  STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">;
 
 def : Pat<(int_aarch64_stg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),
-          (STGOffset GPR64:$Rt, GPR64sp:$Rn,  simm9s16:$offset)>;
+          (STGi GPR64:$Rt, GPR64sp:$Rn,  simm9s16:$offset)>;
 
 def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2),
           (STGPi $Rt, $Rt2, $Rn, $imm)>;
 
 def IRGstack
     : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rsp, GPR64:$Rm), []>,
       Sched<[]>;
 def TAGPstack

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

 }
 
 // These instruction set memory tag and either keep memory contents unchanged or
 // set it to zero, ignoring the address part of the source register.
 static bool isTagStore(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     return false;
-  case AArch64::STGOffset:
-  case AArch64::STZGOffset:
-  case AArch64::ST2GOffset:
-  case AArch64::STZ2GOffset:
+  case AArch64::STGi:
+  case AArch64::STZGi:
+  case AArch64::ST2Gi:
+  case AArch64::STZ2Gi:
     return true;
   }
 }
 
 static unsigned getMatchingNonSExtOpcode(unsigned Opc,
                                          bool *IsValidLdStrOpc = nullptr) {
   if (IsValidLdStrOpc)
     *IsValidLdStrOpc = true;
static unsigned getPreIndexedOpcode(unsigned Opc) {
   case AArch64::STPDi:
     return AArch64::STPDpre;
   case AArch64::STPQi:
     return AArch64::STPQpre;
   case AArch64::STPWi:
     return AArch64::STPWpre;
   case AArch64::STPXi:
     return AArch64::STPXpre;
-  case AArch64::STGOffset:
+  case AArch64::STGi:
     return AArch64::STGPreIndex;
-  case AArch64::STZGOffset:
+  case AArch64::STZGi:
     return AArch64::STZGPreIndex;
-  case AArch64::ST2GOffset:
+  case AArch64::ST2Gi:
     return AArch64::ST2GPreIndex;
-  case AArch64::STZ2GOffset:
+  case AArch64::STZ2Gi:
     return AArch64::STZ2GPreIndex;
   case AArch64::STGPi:
     return AArch64::STGPpre;
   }
 }
 
 static unsigned getPostIndexedOpcode(unsigned Opc) {
   switch (Opc) {
static unsigned getPostIndexedOpcode(unsigned Opc) {
   case AArch64::STPDi:
     return AArch64::STPDpost;
   case AArch64::STPQi:
     return AArch64::STPQpost;
   case AArch64::STPWi:
     return AArch64::STPWpost;
   case AArch64::STPXi:
     return AArch64::STPXpost;
-  case AArch64::STGOffset:
+  case AArch64::STGi:
     return AArch64::STGPostIndex;
-  case AArch64::STZGOffset:
+  case AArch64::STZGi:
     return AArch64::STZGPostIndex;
-  case AArch64::ST2GOffset:
+  case AArch64::ST2Gi:
     return AArch64::ST2GPostIndex;
-  case AArch64::STZ2GOffset:
+  case AArch64::STZ2Gi:
     return AArch64::STZ2GPostIndex;
   case AArch64::STGPi:
     return AArch64::STGPpost;
   }
 }
 
 static bool isPreLdStPairCandidate(MachineInstr &FirstMI, MachineInstr &MI) {
 
static bool isMergeableLdStUpdate(MachineInstr &MI) {
   case AArch64::STRBBui:
   case AArch64::LDRSui:
   case AArch64::LDRDui:
   case AArch64::LDRQui:
   case AArch64::LDRXui:
   case AArch64::LDRWui:
   case AArch64::LDRHHui:
   case AArch64::LDRBBui:
-  case AArch64::STGOffset:
-  case AArch64::STZGOffset:
-  case AArch64::ST2GOffset:
-  case AArch64::STZ2GOffset:
+  case AArch64::STGi:
+  case AArch64::STZGi:
+  case AArch64::ST2Gi:
+  case AArch64::STZ2Gi:
   case AArch64::STGPi:
   // Unscaled instructions.
   case AArch64::STURSi:
   case AArch64::STURDi:
   case AArch64::STURQi:
   case AArch64::STURWi:
   case AArch64::STURXi:
   case AArch64::LDURSi:

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

def : InstRW<[N2Write_1cyc_1L01_1D_1I], (instrs STGPreIndex, STGPostIndex,
                                                 STZGPreIndex, STZGPostIndex,
                                                 STZ2GPreIndex, STZ2GPostIndex,
                                                 STGPpre, STGPpost)>;
 
 // Store allocation tags to one or two granules, signed offset
 // Store allocation tag to two granules, zeroing, signed offset
 // Store allocation tag and reg pair to memory, signed offset
 // Store multiple allocation tags
-def : InstRW<[N2Write_1cyc_1L01_1D], (instrs STGOffset, ST2GOffset, STZGOffset,
-                                             STZ2GOffset, STGPi, STGM, STZGM)>;
+def : InstRW<[N2Write_1cyc_1L01_1D], (instrs STGi, ST2Gi, STZGi,
+                                             STZ2Gi, STGPi, STGM, STZGM)>;
 
 // FP data processing instructions
 // -----------------------------------------------------------------------------
 
 // FP absolute value
 // FP arithmetic
 // FP min/max
 // FP negate

llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp

for (auto *I : ReTags) {
     int Score = 0;
     SmallVector<Register, 8> WorkList;
     WorkList.push_back(RetagReg);
 
     while (!WorkList.empty()) {
       Register UseReg = WorkList.pop_back_val();
       for (auto &UseI : MRI->use_instructions(UseReg)) {
         unsigned Opcode = UseI.getOpcode();
-        if (Opcode == AArch64::STGOffset || Opcode == AArch64::ST2GOffset ||
-            Opcode == AArch64::STZGOffset || Opcode == AArch64::STZ2GOffset ||
+        if (Opcode == AArch64::STGi || Opcode == AArch64::ST2Gi ||
+            Opcode == AArch64::STZGi || Opcode == AArch64::STZ2Gi ||
             Opcode == AArch64::STGPi || Opcode == AArch64::STGloop ||
             Opcode == AArch64::STZGloop || Opcode == AArch64::STGloop_wback ||
             Opcode == AArch64::STZGloop_wback)
           continue;
         if (UseI.isCopy()) {
           Register DstReg = UseI.getOperand(0).getReg();
           if (DstReg.isVirtual())
             WorkList.push_back(DstReg);

llvm/test/CodeGen/AArch64/ldst-opt-mte-with-dbg.mir

 # Strip out debug info, then run ldst-opt with limit=1.
 # RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass mir-strip-debug,aarch64-ldst-opt -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
 #
 # Run ldst-opt with limit=1, then strip out debug info.
 # RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt,mir-strip-debug -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
 ---
 
 ### STG and its offset limits
 
 # CHECK-LABEL: name: test_STG_post
 # CHECK: STGPostIndex $x0, $x0, 7
 name: test_STG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_same_reg
 # CHECK: STGPostIndex $x1, $x0, 7
 name: test_STG_post_same_reg
 body: |
   bb.0.entry:
     liveins: $x0, $x1
 
-    STGOffset $x1, $x0, 0
+    STGi $x1, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_unaligned
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 8, 0
 name: test_STG_post_unaligned
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 8, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post2
 # CHECK: STGPostIndex $x0, $x0, -256
 name: test_STG_post2
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 4096, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post3
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: SUBXri $x0, 4112, 0
 name: test_STG_post3
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 4112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post4
 # CHECK: STGPostIndex $x0, $x0, 255
 name: test_STG_post4
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 4080, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post5
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 4096, 0
 name: test_STG_post5
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 4096, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### The rest of ST*G variants.
 
 # CHECK-LABEL: name: test_STZG_post
 # CHECK: STZGPostIndex $x0, $x0, 7
 name: test_STZG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STZGOffset $x0, $x0, 0
+    STZGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_ST2G_post
 # CHECK: ST2GPostIndex $x0, $x0, 7
 name: test_ST2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    ST2GOffset $x0, $x0, 0
+    ST2Gi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STZ2G_post
 # CHECK: STZ2GPostIndex $x0, $x0, 7
 name: test_STZ2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STZ2GOffset $x0, $x0, 0
+    STZ2Gi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 

 
 # CHECK-LABEL: name: test_STG_pre
 # CHECK: STGPreIndex $x0, $x0, 10
 name: test_STG_pre
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 10
+    STGi $x0, $x0, 10
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 160, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 

 name: test_STG_pre_back
 body: |
   bb.0.entry:
     liveins: $x0
 
     $x0 = ADDXri $x0, 32, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     DBG_VALUE $x0, 0
     DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre_back
 # CHECK: STGPpre $x1, $x2, $x0, -3
 name: test_STGP_pre_back

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir

 # RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
 # RUN: llc -debugify-and-strip-all-safe -mtriple=aarch64-none-linux-gnu -mattr=+mte -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
 ---
 
 ### STG and its offset limits
 
 # CHECK-LABEL: name: test_STG_post
 # CHECK: STGPostIndex $x0, $x0, 7
 name: test_STG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = ADDXri $x0, 112, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_same_reg
 # CHECK: STGPostIndex $x1, $x0, 7
 name: test_STG_post_same_reg
 body: |
   bb.0.entry:
     liveins: $x0, $x1
 
-    STGOffset $x1, $x0, 0
+    STGi $x1, $x0, 0
     $x0 = ADDXri $x0, 112, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_unaligned
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 8, 0
 name: test_STG_post_unaligned
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = ADDXri $x0, 8, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post2
 # CHECK: STGPostIndex $x0, $x0, -256
 name: test_STG_post2
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = SUBXri $x0, 4096, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post3
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: SUBXri $x0, 4112, 0
 name: test_STG_post3
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = SUBXri $x0, 4112, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post4
 # CHECK: STGPostIndex $x0, $x0, 255
 name: test_STG_post4
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = ADDXri $x0, 4080, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post5
-# CHECK:      STGOffset $x0, $x0, 0
+# CHECK:      STGi $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 4096, 0
 name: test_STG_post5
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     $x0 = ADDXri $x0, 4096, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### The rest of ST*G variants.
 
 # CHECK-LABEL: name: test_STZG_post
 # CHECK: STZGPostIndex $x0, $x0, 7
 name: test_STZG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STZGOffset $x0, $x0, 0
+    STZGi $x0, $x0, 0
     $x0 = ADDXri $x0, 112, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_ST2G_post
 # CHECK: ST2GPostIndex $x0, $x0, 7
 name: test_ST2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    ST2GOffset $x0, $x0, 0
+    ST2Gi $x0, $x0, 0
     $x0 = ADDXri $x0, 112, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STZ2G_post
 # CHECK: STZ2GPostIndex $x0, $x0, 7
 name: test_STZ2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STZ2GOffset $x0, $x0, 0
+    STZ2Gi $x0, $x0, 0
     $x0 = ADDXri $x0, 112, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### STGP and its offset limits
 
 # CHECK-LABEL: name: test_STGP_post
 # CHECK: STGPpost $x1, $x2, $x0, 7

 
 # CHECK-LABEL: name: test_STG_pre
 # CHECK: STGPreIndex $x0, $x0, 10
 name: test_STG_pre
 body: |
   bb.0.entry:
     liveins: $x0
 
-    STGOffset $x0, $x0, 10
+    STGi $x0, $x0, 10
     $x0 = ADDXri $x0, 160, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre
 # CHECK: STGPpre $x1, $x2, $x0, 10
 name: test_STGP_pre
 body: |

 # CHECK-LABEL: name: test_STG_pre_back
 # CHECK: STGPreIndex $x0, $x0, 2
 name: test_STG_pre_back
 body: |
   bb.0.entry:
     liveins: $x0
 
     $x0 = ADDXri $x0, 32, 0
-    STGOffset $x0, $x0, 0
+    STGi $x0, $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre_back
 # CHECK: STGPpre $x1, $x2, $x0, -3
 name: test_STGP_pre_back
 body: |
   bb.0.entry:

llvm/test/CodeGen/AArch64/settag-merge.mir

entry:
     ret void
   }
 
 ...
 ---
 # A sequence of STG with a register copy in the middle.
 # Can be merged into ST2G + ST2G.
 # CHECK-LABEL: name:{{.*}}stg16_16_16_16_ret
-# CHECK-DAG: ST2GOffset $sp, $sp, 2
-# CHECK-DAG: ST2GOffset $sp, $sp, 0
+# CHECK-DAG: ST2Gi $sp, $sp, 2
+# CHECK-DAG: ST2Gi $sp, $sp, 0
 # CHECK-DAG: $w0 = COPY $wzr
 # CHECK-DAG: RET_ReallyLR implicit killed $w0
 
 name:            stg16_16_16_16_ret
 tracksRegLiveness: true
 stack:
   - { id: 0, name: a, size: 16, alignment: 16 }
   - { id: 1, name: b, size: 16, alignment: 16 }
   - { id: 2, name: c, size: 16, alignment: 16 }
   - { id: 3, name: d, size: 16, alignment: 16 }
 body:             |
   bb.0.entry:
-    STGOffset $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
-    STGOffset $sp, %stack.1.b, 0 :: (store (s128) into %ir.b)
-    STGOffset $sp, %stack.2.c, 0 :: (store (s128) into %ir.c)
+    STGi $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
+    STGi $sp, %stack.1.b, 0 :: (store (s128) into %ir.b)
+    STGi $sp, %stack.2.c, 0 :: (store (s128) into %ir.c)
     $w0 = COPY $wzr
-    STGOffset $sp, %stack.3.d, 0 :: (store (s128) into %ir.d)
+    STGi $sp, %stack.3.d, 0 :: (store (s128) into %ir.d)
     RET_ReallyLR implicit killed $w0
 
 ...
 
 ---
 # A store in the middle prevents merging.
 # CHECK-LABEL: name:{{.*}}stg16_store_128
-# CHECK: ST2GOffset $sp, $sp, 2
-# CHECK: ST2GOffset $sp, $sp, 4
-# CHECK: ST2GOffset $sp, $sp, 6
-# CHECK: STGOffset  $sp, $sp, 8
+# CHECK: ST2Gi $sp, $sp, 2
+# CHECK: ST2Gi $sp, $sp, 4
+# CHECK: ST2Gi $sp, $sp, 6
+# CHECK: STGi  $sp, $sp, 8
 # CHECK: STRBBui
-# CHECK: ST2GOffset $sp, $sp, 0
+# CHECK: ST2Gi $sp, $sp, 0
 # CHECK: RET_ReallyLR
 
 name:            stg16_store_128
 tracksRegLiveness: true
 stack:
   - { id: 0, name: a, size: 16, alignment: 16 }
   - { id: 1, name: b, size: 128, alignment: 16 }
 body:             |
   bb.0.entry:
-    STGOffset $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
+    STGi $sp, %stack.0.a, 0 :: (store (s128) into %ir.a)
     renamable $w8 = MOVi32imm 42
-    ST2GOffset $sp, %stack.1.b, 6 :: (store (s256) into %ir.b + 96, align 16)
-    ST2GOffset $sp, %stack.1.b, 4 :: (store (s256) into %ir.b + 64, align 16)
-    ST2GOffset $sp, %stack.1.b, 2 :: (store (s256) into %ir.b + 32, align 16)
+    ST2Gi $sp, %stack.1.b, 6 :: (store (s256) into %ir.b + 96, align 16)
+    ST2Gi $sp, %stack.1.b, 4 :: (store (s256) into %ir.b + 64, align 16)
+    ST2Gi $sp, %stack.1.b, 2 :: (store (s256) into %ir.b + 32, align 16)
     STRBBui killed renamable $w8, %stack.0.a, 0 :: (store (s8) into %ir.a, align 16)
-    ST2GOffset $sp, %stack.1.b, 0 :: (store (s256) into %ir.b, align 16)
+    ST2Gi $sp, %stack.1.b, 0 :: (store (s256) into %ir.b, align 16)
     RET_ReallyLR
 
 ...