[AArch64][SVE]: Optimize using ptest with whilelo

[hassnaa-arm]

Summary

Pointless AND, PTEST instructions are generated to force zeroing additional lanes after doing REINTERPRET_CAST operation.
For sve_whilelo operation, no need for that, because its inactive lanes are zeroed by construction.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

266

There are also other while intrinsics, which would benefit in a similar way?

llvm/test/CodeGen/AArch64/sve2-ptest_whilelt.ll

6

lt or lo?

32

Do you need the loop to test this? Or can you just use:

%0 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 0, i32 %width)
%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1)

?

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

266

Hi @hassnaa-arm, I think we should probably add the other while variants too here, since the same thing applies for whilelt, etc.

llvm/test/CodeGen/AArch64/sve2-ptest_whilelt.ll

1

The test file suggests this is SVE2, but in fact whilelo was introduced in SVE. Also, the file name suggests you're testing whilelt, but actually it's testing whilelo. Is it worth just renaming the file to be something like

sve-ptest-removal-while.ll

similar to the other existing sve-ptest-removal-xyz.ll tests?

[hassnaa-arm]

llvm/test/CodeGen/AArch64/sve2-ptest_whilelt.ll

6

sorry, lo.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

default:
     return false;
   case AArch64ISD::PTRUE:
   case AArch64ISD::SETCC_MERGE_ZERO:
     return true;
   case ISD::INTRINSIC_WO_CHAIN:
     switch (Op.getConstantOperandVal(0)) {
     default:
       return false;
+    case Intrinsic::aarch64_sve_whilelo:
     case Intrinsic::aarch64_sve_ptrue:
     case Intrinsic::aarch64_sve_pnext:
     case Intrinsic::aarch64_sve_cmpeq:
     case Intrinsic::aarch64_sve_cmpne:
     case Intrinsic::aarch64_sve_cmpge:
     case Intrinsic::aarch64_sve_cmpgt:
     case Intrinsic::aarch64_sve_cmphs:
     case Intrinsic::aarch64_sve_cmphi:

llvm/test/CodeGen/AArch64/sve2-ptest_whilelt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define void @test_svwhilelt_with_ptest(i32 noundef %width)  #0 {
+; CHECK-LABEL: test_svwhilelt_with_ptest:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    whilelo p0.s, wzr, w0
+; CHECK-NEXT:    b.eq .LBB0_3
+; CHECK-NEXT:  // %bb.1: // %for.body.lr.ph
+; CHECK-NEXT:    cntw x8
+; CHECK-NEXT:    mov w9, w8
+; CHECK-NEXT:  .LBB0_2: // %for.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    whilelo p0.s, w9, w0
+; CHECK-NEXT:    add w9, w9, w8
+; CHECK-NEXT:    b.ne .LBB0_2
+; CHECK-NEXT:  .LBB0_3: // %for.cond.cleanup
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 0, i32 %width)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1)
+  br i1 %2, label %for.body.lr.ph, label %for.cond.cleanup
+
+for.body.lr.ph:                                   ; preds = %entry
+  %3 = tail call i32 @llvm.vscale.i32()
+  %4 = shl nuw nsw i32 %3, 2
+  br label %for.body
+
+for.body:                                         ; preds = %for.body.lr.ph, %for.body
+  %5 = phi <vscale x 4 x i1> [ %1, %for.body.lr.ph ], [ %6, %for.body ]
+  %x.07 = phi i32 [ 0, %for.body.lr.ph ], [ %conv3, %for.body ]
+  %conv3 = add i32 %4, %x.07
+  %6 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %conv3, i32 %width)
+  %7 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %6)
+  br i1 %7, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %for.body, %entry
+  ret void
+}
+
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32)
+declare i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
+declare i32 @llvm.vscale.i32()
+
+attributes #0 = { "target-features"="+sve2" }