[Clang][RISCV] Expose vlenb to user

[eopXD]

Summary

This commit adds function vlenb into riscv_vector.h. vlenb is defined
through builtin function __builtin_rvv_vlenb, which is lowered to
llvm.read_register.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1559

Should we report errors if vwrite_csr(RVV_VLENB, some_value)?

[eopXD]

Upon a second thought, with future extensions of the intrinsics, we will add rounding mode and exception intrinsics. The exposure of vxsat, vxrm, and vcsr in vread_csr and vwrite_csr will confuse user and we should remove them. Furthermore, vstart is pretty much always kept to zero, and intrinsic users probably should not have access to them.

With the considerations above, I think vread_csr and vwrite_csr can be removed in the future when the rounding mode and exception intrinsics are added. This is why this patch is opening up a separate function to provide access to vlenb and not choose to extend another member in the enum.

[eopXD]

Update code. Add function vlenb instead of extending inside the vread_csr function.

[eopXD]

clang/include/clang/Basic/riscv_vector.td

1559

Thanks pointing this out. I think my second approach here won't create such problem.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1569

Inline assembly may not be elegant since it can't be optimized in many ways. We can eliminate some redundant reads of vlenb currently(done in D125564). So I think we may add a builtin function and lower it to llvm.read_register?

[eopXD]

Update code. Apply suggestion from @pcwang-thead.

[eopXD]

clang/include/clang/Basic/riscv_vector.td

1569

Thank you for the tip. Please review.

[• pcwang-thead]

The code is OK to me, except a few small comments.

clang/include/clang/Basic/riscv_vector.td

1583

The value type of read_register is i32 in llvm/test/CodeGen/RISCV/vlenb.ll, but I don't insist on it.

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

1 ↗

(On Diff #487206)

Add --check-globals or --global-value-regex to check if the metadata is vlenb exactly?

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

1583

Doesn't this need to match the size of long?

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

1 ↗

(On Diff #487206)

Please test riscv32 as well

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1583

So what about i32 for rv32 and i64 for rv64?

[eopXD]

Address comments from Craig.

[• pcwang-thead]

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

33 ↗

(On Diff #487293)

Hmm, why would we emit version info here? I think we should avoid this.
I find a clang option -Qn that can disable emitting this by setting EmitVersionIdentMetadata to false.

[eopXD]

Update code: Avoid emit clang version in test case.
@pcwang-thead Thank you for checking and providing the corresponding resolution. :)

clang/include/clang/Basic/riscv_vector.td

 // Define vread_csr&vwrite_csr described in RVV intrinsics doc.
 let HeaderCode =
 [{
 enum RVV_CSR {
   RVV_VSTART = 0,
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
 unsigned long vread_csr(enum RVV_CSR __csr) {
   unsigned long __rv = 0;
   switch (__csr) {
     case RVV_VSTART:
       __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
       break;
     case RVV_VXSAT:
       __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
       break;
     case RVV_VXRM:
       __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
       break;
     case RVV_VCSR:
       __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
       break;
+    case RVV_VLENB:
+      __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+      break;
   }
   return __rv;
 }
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
 void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
   switch (__csr) {
     case RVV_VSTART:
       __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VXSAT:
       __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VXRM:
       __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VCSR:
       __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
       break;
   }
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
 
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
 // and LMUL.
 let HeaderCode =
 [{
 #define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
 #define vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
 #define vsetvl_e8m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 0)
 #define vsetvl_e8m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 1)
 #define vsetvl_e8m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 2)
 #define vsetvl_e8m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 3)
 
 #define vsetvl_e16mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 7)
 #define vsetvl_e16m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 0)
 #define vsetvl_e16m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 1)
 #define vsetvl_e16m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 2)
 #define vsetvl_e16m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 1, 3)
 
 #define vsetvl_e32m1(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 0)
 #define vsetvl_e32m2(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 1)
 #define vsetvl_e32m4(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 2)
 #define vsetvl_e32m8(avl) __builtin_rvv_vsetvli((size_t)(avl), 2, 3)
 
 #if __riscv_v_elen >= 64
 #define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)

clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c

 // CHECK-LABEL: @vread_csr_vcsr(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
 // CHECK-NEXT:    ret i64 [[TMP0]]
 //
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}