[Clang][RISCV] Expose vlenb to user

[eopXD]

Summary

This commit adds function vlenb into riscv_vector.h. vlenb is defined
through builtin function __builtin_rvv_vlenb, which is lowered to
llvm.read_register.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1555

Should we report errors if vwrite_csr(RVV_VLENB, some_value)?

[eopXD]

Upon a second thought, with future extensions of the intrinsics, we will add rounding mode and exception intrinsics. The exposure of vxsat, vxrm, and vcsr in vread_csr and vwrite_csr will confuse user and we should remove them. Furthermore, vstart is pretty much always kept to zero, and intrinsic users probably should not have access to them.

With the considerations above, I think vread_csr and vwrite_csr can be removed in the future when the rounding mode and exception intrinsics are added. This is why this patch is opening up a separate function to provide access to vlenb and not choose to extend another member in the enum.

[eopXD]

Update code. Add function vlenb instead of extending inside the vread_csr function.

[eopXD]

clang/include/clang/Basic/riscv_vector.td

1555

Thanks pointing this out. I think my second approach here won't create such problem.

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1565

Inline assembly may not be elegant since it can't be optimized in many ways. We can eliminate some redundant reads of vlenb currently(done in D125564). So I think we may add a builtin function and lower it to llvm.read_register?

[eopXD]

Update code. Apply suggestion from @pcwang-thead.

[eopXD]

clang/include/clang/Basic/riscv_vector.td

1565

Thank you for the tip. Please review.

[• pcwang-thead]

The code is OK to me, except a few small comments.

clang/include/clang/Basic/riscv_vector.td

1579

The value type of read_register is i32 in llvm/test/CodeGen/RISCV/vlenb.ll, but I don't insist on it.

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

2

Add --check-globals or --global-value-regex to check if the metadata is vlenb exactly?

[craig.topper]

clang/include/clang/Basic/riscv_vector.td

1579

Doesn't this need to match the size of long?

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

2

Please test riscv32 as well

[• pcwang-thead]

clang/include/clang/Basic/riscv_vector.td

1579

So what about i32 for rv32 and i64 for rv64?

[eopXD]

Address comments from Craig.

[• pcwang-thead]

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

34

Hmm, why would we emit version info here? I think we should avoid this.
I find a clang option -Qn that can disable emitting this by setting EmitVersionIdentMetadata to false.

[eopXD]

Update code: Avoid emit clang version in test case.
@pcwang-thead Thank you for checking and providing the corresponding resolution. :)

clang/include/clang/Basic/riscv_vector.td

switch (__csr) {
     case RVV_VXSAT:
       __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VXRM:
       __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
       break;
     case RVV_VCSR:
       __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
       break;
   }
 }
 }] in
 def vread_vwrite_csr: RVVHeader;
 
+let HeaderCode =
+[{
+#define vlenb() __builtin_rvv_vlenb()
+}] in
+def vlenb_macro: RVVHeader;
+
+let HasBuiltinAlias = false, HasVL = false, HasMasked = false,
+    UnMaskedPolicyScheme = NonePolicy, MaskedPolicyScheme = NonePolicy,
+    Log2LMUL = [0], IRName = "",
+    ManualCodegen = [{
+    {
+      LLVMContext &Context = CGM.getLLVMContext();
+      llvm::MDBuilder MDHelper(Context);
+
+      llvm::Metadata *Ops[] = {llvm::MDString::get(Context, "vlenb")};
+      llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
+      llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
+      llvm::Function *F =
+        CGM.getIntrinsic(llvm::Intrinsic::read_register, {SizeTy});
+      return Builder.CreateCall(F, Metadata);
+    }
+    }] in
+{
+  def vlenb : RVVBuiltin<"", "u", "i">;
+}
+
 // 6. Configuration-Setting Instructions
 // 6.1. vsetvli/vsetvl instructions
 
 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
 // and LMUL.
 let HeaderCode =
 [{
 #define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)

clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN:     | opt -S -O2 | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
+// RUN:     | opt -S -O2 | FileCheck --check-prefix=RV64 %s
+
+#include <riscv_vector.h>
+
+// RV32-LABEL: @test_vlenb(
+// RV32-NEXT:  entry:
+// RV32-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META3:![0-9]+]])
+// RV32-NEXT:    ret i32 [[TMP0]]
+//
+// RV64-LABEL: @test_vlenb(
+// RV64-NEXT:  entry:
+// RV64-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META3:![0-9]+]])
+// RV64-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long test_vlenb(void) {
+  return vlenb();
+}
+//.
+// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
+//.
+// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
+//.
+// RV32: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV32: !1 = !{i32 1, !"target-abi", !"ilp32d"}
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"vlenb"}
+//.
+// RV64: !0 = !{i32 1, !"wchar_size", i32 4}
+// RV64: !1 = !{i32 1, !"target-abi", !"lp64d"}
+// RV64: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV64: !3 = !{!"vlenb"}
+//.