[RISCV] Match neg (and x, 1) to two shifts to improve codesize

[reames]

Summary

The negate operation is never compressible (as the destination and rs1 register must differ). The two shift versions will be equal size if the input GPR is reused, or smaller if this is the only use of the input.

For clarity, the operation being performed is (select (low-bit-of x), -1, 0).

[reames]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1244

This shouldn't be specific to RV64, but my attempts to write a pattern which used ImmSubFromVLen kept failing type inference. Any suggestions on how to write such a pattern?

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1244

ImmSubFromXLen (XLenVT 1), as the issue is TableGen has no way of knowing that the type of the input is the same as the output, it just sees the input as unconstrained, only the output constrained by its use. Normally that doesn't matter because the input is a pre-existing node whose type is constrained by the pattern being matched.

1245

Why explicit hex?

[reames]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1244

Thanks!

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1244

Any harm in doing this regardless of HasStdExtC? I've sort of been of the opinion that we should avoid CodeGen differences between C and non-C if we can.

[craig.topper]

No RV32 test coverage?

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1246

Wrap this for 80 columns

[asb]

LGTM with Craig's comments addressed + RV32 test coverage.

I think doing this even without the compressed extension probably makes sense. Surprisingly it seems there's a couple of cases in the GCC torture suite at O0 where li a0, 0; sub a0, a0, a1 is selected rather than a neg. This patch also avoids avoids that - not that it's particularly important one way or another given how heavyweight the O0 output is in general.

EDIT: Thanks for Craig pointing out below why this isn't surprising.

[craig.topper]

In D140319#4005826, @asb wrote:

LGTM with Craig's comments addressed + RV32 test coverage.

I think doing this even without the compressed extension probably makes sense. Surprisingly it seems there's a couple of cases in the GCC torture suite at O0 where li a0, 0; sub a0, a0, a1 is selected rather than a neg. This patch also avoids avoids that - not that it's particularly important one way or another given how heavyweight the O0 output is in general.

Probably because we emit a copy from X0 and -O0 doesn't run the coalescer.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 def zexti8 : ComplexPattern<XLenVT, 1, "selectZExtBits<8>">;
 
 class binop_oneuse<SDPatternOperator operator>
     : PatFrag<(ops node:$A, node:$B),
               (operator node:$A, node:$B), [{
   return N->hasOneUse();
 }]>;
 
+def and_oneuse : binop_oneuse<and>;
 def add_oneuse : binop_oneuse<add>;
 def mul_oneuse : binop_oneuse<mul>;
 
 def mul_const_oneuse : PatFrag<(ops node:$A, node:$B),
                                (mul node:$A, node:$B), [{
   if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
     if (N1C->hasOneUse())
       return true;

 def : PatGprGpr<and, AND>;
 def : PatGprSimm12<and, ANDI>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprSimm12<xor, XORI>;
 def : PatGprUimmLog2XLen<shl, SLLI>;
 def : PatGprUimmLog2XLen<srl, SRLI>;
 def : PatGprUimmLog2XLen<sra, SRAI>;
 
+// negate of low bit can be done via two (compressible) shifts.  The negate
+// is never compressible since rs1 and rd can't be the same register.
+def : Pat<(XLenVT (sub 0, (and_oneuse GPR:$rs, 1))),
+          (SRAI (SLLI $rs, (ImmSubFromXLen (XLenVT 1))),
+                (ImmSubFromXLen (XLenVT 1)))>;
+
 // AND with leading/trailing ones mask exceeding simm32/simm12.
 def : Pat<(i64 (and GPR:$rs, LeadingOnesMask:$mask)),
           (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
 def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
           (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
 
 // Match both a plain shift and one where the shift amount is masked (this is
 // typically introduced when the legalizer promotes the shift amount and

llvm/test/CodeGen/RISCV/pr58511.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
 
 define i32 @f(i1 %0, i32 %1, ptr %2) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %BB
 ; CHECK-NEXT:    slliw a3, a1, 11
 ; CHECK-NEXT:    slliw a1, a1, 12
 ; CHECK-NEXT:    subw a1, a1, a3
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    slli a0, a0, 63
+; CHECK-NEXT:    srai a0, a0, 63
 ; CHECK-NEXT:    li a3, 1
 ; CHECK-NEXT:    slli a3, a3, 11
 ; CHECK-NEXT:    or a0, a0, a3
 ; CHECK-NEXT:    sw a1, 0(a2)
 ; CHECK-NEXT:    ret
 BB:
   %I = select i1 %0, i32 -1, i32 0
   %I1 = mul i32 %1, 2048

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s
+; RUN:   | FileCheck --check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s
+; RUN:   | FileCheck --check-prefixes=CHECK,RV64 %s
 
 declare i1 @llvm.vp.reduce.and.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_and_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_v1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_or_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_v1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_v1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_xor_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_v1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_v1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_and_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_or_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_v2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_v2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_xor_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_v2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_v2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_and_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_or_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_v4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_v4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_xor_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_v4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_v4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_and_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_or_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_v8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_v8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_xor_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_v8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_v8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.v10i1(i1, <10 x i1>, <10 x i1>, i32)
 
 define signext i1 @vpreduce_and_v10i1(i1 signext %s, <10 x i1> %v, <10 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_v10i1:

 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.v256i1(i1 %s, <256 x i1> %v, <256 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.v16i1(i1, <16 x i1>, <16 x i1>, i32)
 
 define signext i1 @vpreduce_or_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_v16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_v16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.v16i1(i1, <16 x i1>, <16 x i1>, i32)
 
 define signext i1 @vpreduce_xor_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_v16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_v16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_add_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_v1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_v1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_add_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_v2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_v2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_add_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_v4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_v4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_add_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_v8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_v8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.v16i1(i1, <16 x i1>, <16 x i1>, i32)
 
 define signext i1 @vpreduce_add_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_v16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_v16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smax.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_smax_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_smax_v1i1:

 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smax.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v16i1(i1, <16 x i1>, <16 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v32i1(i1, <32 x i1>, <32 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.v64i1(i1, <64 x i1>, <64 x i1>, i32)
 
 define signext i1 @vpreduce_smin_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_v64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_v64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_v64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v1i1(i1 %s, <1 x i1> %v, <1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v2i1(i1, <2 x i1>, <2 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v2i1(i1 signext %s, <2 x i1> %v, <2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v2i1(i1 %s, <2 x i1> %v, <2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v4i1(i1, <4 x i1>, <4 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v4i1(i1 signext %s, <4 x i1> %v, <4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v4i1(i1 %s, <4 x i1> %v, <4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v8i1(i1, <8 x i1>, <8 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v8i1(i1 signext %s, <8 x i1> %v, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v8i1(i1 %s, <8 x i1> %v, <8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v16i1(i1, <16 x i1>, <16 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v16i1(i1 signext %s, <16 x i1> %v, <16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v16i1(i1 %s, <16 x i1> %v, <16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v32i1(i1, <32 x i1>, <32 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v32i1(i1 signext %s, <32 x i1> %v, <32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v32i1(i1 %s, <32 x i1> %v, <32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.v64i1(i1, <64 x i1>, <64 x i1>, i32)
 
 define signext i1 @vpreduce_umax_v64i1(i1 signext %s, <64 x i1> %v, <64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_v64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_v64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_v64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.v64i1(i1 %s, <64 x i1> %v, <64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umin.v1i1(i1, <1 x i1>, <1 x i1>, i32)
 
 define signext i1 @vpreduce_umin_v1i1(i1 signext %s, <1 x i1> %v, <1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_umin_v1i1:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
 
 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_or_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_or_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_or_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_or_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_xor_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_xor_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_and_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_and_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_and_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_and_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_umax_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_umax_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umax_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_smax_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_smax_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smax_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_umin_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_umin_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_umin_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_smin_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_smin_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_smin_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_or_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_or_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vcpop.m a0, v0
 ; CHECK-NEXT:    seqz a0, a0
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_xor_v2i1(<2 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_xor_v2i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_xor_v2i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_and_v2i1(<2 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v2i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_xor_v4i1(<4 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_xor_v4i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_xor_v4i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_and_v4i1(<4 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v4i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_xor_v8i1(<8 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_xor_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_xor_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_and_v8i1(<8 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v8i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
 
 define signext i1 @vreduce_xor_v16i1(<16 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_xor_v16i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_xor_v16i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
 
 define signext i1 @vreduce_and_v16i1(<16 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_v16i1:

 declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
 
 define signext i1 @vreduce_xor_v32i1(<32 x i1> %v) {
 ; LMULMAX1-LABEL: vreduce_xor_v32i1:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; LMULMAX1-NEXT:    vmxor.mm v8, v0, v8
 ; LMULMAX1-NEXT:    vcpop.m a0, v8
-; LMULMAX1-NEXT:    andi a0, a0, 1
-; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX8-LABEL: vreduce_xor_v32i1:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    li a0, 32
 ; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; LMULMAX8-NEXT:    vcpop.m a0, v0
-; LMULMAX8-NEXT:    andi a0, a0, 1
-; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
 
 define signext i1 @vreduce_and_v32i1(<32 x i1> %v) {

 define signext i1 @vreduce_xor_v64i1(<64 x i1> %v) {
 ; LMULMAX1-LABEL: vreduce_xor_v64i1:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; LMULMAX1-NEXT:    vmxor.mm v8, v8, v10
 ; LMULMAX1-NEXT:    vmxor.mm v9, v0, v9
 ; LMULMAX1-NEXT:    vmxor.mm v8, v9, v8
 ; LMULMAX1-NEXT:    vcpop.m a0, v8
-; LMULMAX1-NEXT:    andi a0, a0, 1
-; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX8-LABEL: vreduce_xor_v64i1:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    li a0, 64
 ; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; LMULMAX8-NEXT:    vcpop.m a0, v0
-; LMULMAX8-NEXT:    andi a0, a0, 1
-; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
 
 define signext i1 @vreduce_and_v64i1(<64 x i1> %v) {

 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
 
 define signext i1 @vreduce_add_v1i1(<1 x i1> %v) {
-; CHECK-LABEL: vreduce_add_v1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_add_v1i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vmv.v.i v8, 0
+; LMULMAX1-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX1-NEXT:    vmv.x.s a0, v8
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_add_v1i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vmv.v.i v8, 0
+; LMULMAX8-NEXT:    vmerge.vim v8, v8, 1, v0
+; LMULMAX8-NEXT:    vmv.x.s a0, v8
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
 
 define signext i1 @vreduce_add_v2i1(<2 x i1> %v) {
-; CHECK-LABEL: vreduce_add_v2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_add_v2i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_add_v2i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
 
 define signext i1 @vreduce_add_v4i1(<4 x i1> %v) {
-; CHECK-LABEL: vreduce_add_v4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_add_v4i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_add_v4i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
 
 define signext i1 @vreduce_add_v8i1(<8 x i1> %v) {
-; CHECK-LABEL: vreduce_add_v8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_add_v8i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_add_v8i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
 
 define signext i1 @vreduce_add_v16i1(<16 x i1> %v) {
-; CHECK-LABEL: vreduce_add_v16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; LMULMAX1-LABEL: vreduce_add_v16i1:
+; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX1-NEXT:    vcpop.m a0, v0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
+; LMULMAX1-NEXT:    ret
+;
+; LMULMAX8-LABEL: vreduce_add_v16i1:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; LMULMAX8-NEXT:    vcpop.m a0, v0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
+; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
 
 define signext i1 @vreduce_add_v32i1(<32 x i1> %v) {
 ; LMULMAX1-LABEL: vreduce_add_v32i1:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; LMULMAX1-NEXT:    vmxor.mm v8, v0, v8
 ; LMULMAX1-NEXT:    vcpop.m a0, v8
-; LMULMAX1-NEXT:    andi a0, a0, 1
-; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX8-LABEL: vreduce_add_v32i1:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    li a0, 32
 ; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
 ; LMULMAX8-NEXT:    vcpop.m a0, v0
-; LMULMAX8-NEXT:    andi a0, a0, 1
-; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
 
 define signext i1 @vreduce_add_v64i1(<64 x i1> %v) {
 ; LMULMAX1-LABEL: vreduce_add_v64i1:
 ; LMULMAX1:       # %bb.0:
 ; LMULMAX1-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; LMULMAX1-NEXT:    vmxor.mm v8, v8, v10
 ; LMULMAX1-NEXT:    vmxor.mm v9, v0, v9
 ; LMULMAX1-NEXT:    vmxor.mm v8, v9, v8
 ; LMULMAX1-NEXT:    vcpop.m a0, v8
-; LMULMAX1-NEXT:    andi a0, a0, 1
-; LMULMAX1-NEXT:    neg a0, a0
+; LMULMAX1-NEXT:    slli a0, a0, 31
+; LMULMAX1-NEXT:    srai a0, a0, 31
 ; LMULMAX1-NEXT:    ret
 ;
 ; LMULMAX8-LABEL: vreduce_add_v64i1:
 ; LMULMAX8:       # %bb.0:
 ; LMULMAX8-NEXT:    li a0, 64
 ; LMULMAX8-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
 ; LMULMAX8-NEXT:    vcpop.m a0, v0
-; LMULMAX8-NEXT:    andi a0, a0, 1
-; LMULMAX8-NEXT:    neg a0, a0
+; LMULMAX8-NEXT:    slli a0, a0, 63
+; LMULMAX8-NEXT:    srai a0, a0, 63
 ; LMULMAX8-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v)
   ret i1 %red
 }

llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s
 
 declare i1 @llvm.vp.reduce.and.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv16i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv40i1(i1, <vscale x 40 x i1>, <vscale x 40 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv40i1(i1 signext %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv40i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv40i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv40i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv40i1(i1 %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.and.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_and_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_and_nxv64i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
 ; CHECK-NEXT:    vmnot.m v9, v0
 ; CHECK-NEXT:    vmv1r.v v0, v8
 ; CHECK-NEXT:    vcpop.m a1, v9, v0.t
 ; CHECK-NEXT:    seqz a1, a1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.and.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.xor.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_xor_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_xor_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_xor_nxv64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_xor_nxv64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.xor.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.or.nxv128i1(i1, <vscale x 128 x i1>, <vscale x 128 x i1>, i32)
 
 define signext i1 @vpreduce_or_nxv128i1(i1 signext %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_or_nxv128i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v11, v0
-; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 3
-; CHECK-NEXT:    sub a3, a1, a2
-; CHECK-NEXT:    sltu a4, a1, a3
-; CHECK-NEXT:    addi a4, a4, -1
-; CHECK-NEXT:    and a3, a4, a3
-; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v10
-; CHECK-NEXT:    vcpop.m a3, v8, v0.t
-; CHECK-NEXT:    snez a3, a3
-; CHECK-NEXT:    bltu a1, a2, .LBB22_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    mv a1, a2
-; CHECK-NEXT:  .LBB22_2:
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v9
-; CHECK-NEXT:    vcpop.m a1, v11, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    or a0, a3, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_or_nxv128i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v11, v0
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 3
+; RV32-NEXT:    sub a3, a1, a2
+; RV32-NEXT:    sltu a4, a1, a3
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    and a3, a4, a3
+; RV32-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v10
+; RV32-NEXT:    vcpop.m a3, v8, v0.t
+; RV32-NEXT:    snez a3, a3
+; RV32-NEXT:    bltu a1, a2, .LBB22_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    mv a1, a2
+; RV32-NEXT:  .LBB22_2:
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v9
+; RV32-NEXT:    vcpop.m a1, v11, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    or a0, a3, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_or_nxv128i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v11, v0
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 3
+; RV64-NEXT:    sub a3, a1, a2
+; RV64-NEXT:    sltu a4, a1, a3
+; RV64-NEXT:    addi a4, a4, -1
+; RV64-NEXT:    and a3, a4, a3
+; RV64-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v10
+; RV64-NEXT:    vcpop.m a3, v8, v0.t
+; RV64-NEXT:    snez a3, a3
+; RV64-NEXT:    bltu a1, a2, .LBB22_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    mv a1, a2
+; RV64-NEXT:  .LBB22_2:
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v9
+; RV64-NEXT:    vcpop.m a1, v11, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    or a0, a3, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.or.nxv128i1(i1 %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.add.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_add_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_add_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_add_nxv64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_add_nxv64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.add.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 
 declare i1 @llvm.vp.reduce.smax.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_smax_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {

 ; CHECK-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.smin.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_smin_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_smin_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_smin_nxv64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_smin_nxv64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.smin.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv1i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv1i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv2i1(i1, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv2i1(i1 signext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv2i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv2i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv4i1(i1, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv4i1(i1 signext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv4i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv4i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv8i1(i1, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv8i1(i1 signext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv8i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv8i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv16i1(i1, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv16i1(i1 signext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv16i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv16i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv32i1(i1, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv32i1(i1 signext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv32i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv32i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umax.nxv64i1(i1, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
 
 define signext i1 @vpreduce_umax_nxv64i1(i1 signext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_umax_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a1, v9, v0.t
-; CHECK-NEXT:    snez a1, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: vpreduce_umax_nxv64i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    vmv1r.v v9, v0
+; RV32-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vcpop.m a1, v9, v0.t
+; RV32-NEXT:    snez a1, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: vpreduce_umax_nxv64i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    vmv1r.v v9, v0
+; RV64-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vcpop.m a1, v9, v0.t
+; RV64-NEXT:    snez a1, a1
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    ret
   %r = call i1 @llvm.vp.reduce.umax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)
   ret i1 %r
 }
 
 declare i1 @llvm.vp.reduce.umin.nxv1i1(i1, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
 
 define signext i1 @vpreduce_umin_nxv1i1(i1 signext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vpreduce_umin_nxv1i1:

llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1>)
 
 define signext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1>)
 
 define signext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
 
 define signext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
 
 define signext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1>)
 
 define signext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1>)
 
 define signext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1>)
 
 define signext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1>)
 
 define signext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv8i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1>)
 
 define signext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
 
 define signext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv16i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>)
 
 define signext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
 
 define signext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv32i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1>)
 
 define signext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {
-; CHECK-LABEL: vreduce_xor_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)
 
 define signext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
 ; CHECK-LABEL: vreduce_and_nxv64i1:

 ; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1>)
 
 define signext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv1i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1>)
 
 define signext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv2i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1>)
 
 define signext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv4i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1>)
 
 define signext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv8i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1>)
 
 define signext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv16i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1>)
 
 define signext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv32i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)
   ret i1 %red
 }
 
 declare i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1>)
 
 define signext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
-; CHECK-LABEL: vreduce_add_nxv64i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT:    vcpop.m a0, v0
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    ret
   %red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)
   ret i1 %red
 }

llvm/test/CodeGen/RISCV/select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64,NOCONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64,CONDOPS %s
 
 define i16 @select_xor_1(i16 %A, i8 %cond) {
 ; RV32-LABEL: select_xor_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a1, a1, 1
-; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    slli a1, a1, 31
+; RV32-NEXT:    srai a1, a1, 31
 ; RV32-NEXT:    andi a1, a1, 43
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_xor_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a1, a1, 1
-; NOCONDOPS-NEXT:    negw a1, a1
+; NOCONDOPS-NEXT:    slli a1, a1, 63
+; NOCONDOPS-NEXT:    srai a1, a1, 63
 ; NOCONDOPS-NEXT:    andi a1, a1, 43
 ; NOCONDOPS-NEXT:    xor a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a1, a1, 1
 ; CONDOPS-NEXT:    seqz a1, a1

  ret i16 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i16 @select_xor_1b(i16 %A, i8 %cond) {
 ; RV32-LABEL: select_xor_1b:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a1, a1, 1
-; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    slli a1, a1, 31
+; RV32-NEXT:    srai a1, a1, 31
 ; RV32-NEXT:    andi a1, a1, 43
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_xor_1b:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a1, a1, 1
-; NOCONDOPS-NEXT:    negw a1, a1
+; NOCONDOPS-NEXT:    slli a1, a1, 63
+; NOCONDOPS-NEXT:    srai a1, a1, 63
 ; NOCONDOPS-NEXT:    andi a1, a1, 43
 ; NOCONDOPS-NEXT:    xor a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_1b:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a1, a1, 1
 ; CONDOPS-NEXT:    li a2, 43
 ; CONDOPS-NEXT:    vt.maskc a1, a2, a1
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 
 define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
 ; RV32-LABEL: select_xor_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_xor_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    xor a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    seqz a2, a2
 ; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
 ; RV32-LABEL: select_xor_2b:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_xor_2b:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    xor a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_2b:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a2
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
 ; RV32-LABEL: select_or:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_or:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    seqz a2, a2
 ; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
 ; RV32-LABEL: select_or_b:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_or_b:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or_b:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
 ; RV32-LABEL: select_or_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_or_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    seqz a2, a2
 ; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp eq i32 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
 ; RV32-LABEL: select_or_1b:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    andi a2, a2, 1
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slli a2, a2, 31
+; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_or_1b:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    andi a2, a2, 1
-; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    slli a2, a2, 63
+; NOCONDOPS-NEXT:    srai a2, a2, 63
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a1, a0
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or_1b:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a2

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

 ; RV64ZBB-NEXT:    ret
   %sub = sub nsw i32 %x, %y
   %cmp = icmp sgt i32 %sub, 0
   %sel = select i1 %cmp, i32 %sub, i32 0
   ret i32 %sel
 }
 
 define i8 @sel_shift_bool_i8(i1 %t) {
-; CHECK-LABEL: sel_shift_bool_i8:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    andi a0, a0, -128
-; CHECK-NEXT:    ret
+; RV32-LABEL: sel_shift_bool_i8:
+; RV32:       # %bb.0:
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai a0, a0, 31
+; RV32-NEXT:    andi a0, a0, -128
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: sel_shift_bool_i8:
+; RV64:       # %bb.0:
+; RV64-NEXT:    slli a0, a0, 63
+; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    andi a0, a0, -128
+; RV64-NEXT:    ret
   %shl = select i1 %t, i8 128, i8 0
   ret i8 %shl
 }
 
 define i16 @sel_shift_bool_i16(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi a0, a0, 1

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 
 define i8 @sext_i1_to_i8(i1 %a) nounwind {
 ; RV32I-LABEL: sext_i1_to_i8:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    slli a0, a0, 31
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sext_i1_to_i8:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    slli a0, a0, 63
+; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    ret
   %1 = sext i1 %a to i8
   ret i8 %1
 }
 
 define i16 @sext_i1_to_i16(i1 %a) nounwind {
 ; RV32I-LABEL: sext_i1_to_i16:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    slli a0, a0, 31
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sext_i1_to_i16:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    slli a0, a0, 63
+; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    ret
   %1 = sext i1 %a to i16
   ret i16 %1
 }
 
 define i32 @sext_i1_to_i32(i1 %a) nounwind {
 ; RV32I-LABEL: sext_i1_to_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    slli a0, a0, 31
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sext_i1_to_i32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    slli a0, a0, 63
+; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    ret
   %1 = sext i1 %a to i32
   ret i32 %1
 }
 
 define i64 @sext_i1_to_i64(i1 %a) nounwind {
 ; RV32I-LABEL: sext_i1_to_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    slli a0, a0, 31
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sext_i1_to_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    andi a0, a0, 1
-; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    slli a0, a0, 63
+; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    ret
   %1 = sext i1 %a to i64
   ret i64 %1
 }
 
 define i16 @sext_i8_to_i16(i8 %a) nounwind {
 ; RV32I-LABEL: sext_i8_to_i16:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

; SFB-NEXT:    ret
   %c = icmp eq i32 %z, 0
   %b = select i1 %c, i32 -1, i32 %x
   ret i32 %b
 }
 
 define i16 @select_xor_1(i16 %A, i8 %cond) {
 ; NOSFB-LABEL: select_xor_1:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a1, a1, 1
-; NOSFB-NEXT:    negw a1, a1
+; NOSFB-NEXT:    slli a1, a1, 63
+; NOSFB-NEXT:    srai a1, a1, 63
 ; NOSFB-NEXT:    andi a1, a1, 43
 ; NOSFB-NEXT:    xor a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_xor_1:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a1, a1, 1
 ; SFB-NEXT:    xori a2, a0, 43

  ret i16 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i16 @select_xor_1b(i16 %A, i8 %cond) {
 ; NOSFB-LABEL: select_xor_1b:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a1, a1, 1
-; NOSFB-NEXT:    negw a1, a1
+; NOSFB-NEXT:    slli a1, a1, 63
+; NOSFB-NEXT:    srai a1, a1, 63
 ; NOSFB-NEXT:    andi a1, a1, 43
 ; NOSFB-NEXT:    xor a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_xor_1b:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a1, a1, 1
 ; SFB-NEXT:    xori a2, a0, 43
 ; SFB-NEXT:    beqz a1, .LBB8_2
 ; SFB-NEXT:  # %bb.1: # %entry
 ; SFB-NEXT:    mv a0, a2
 ; SFB-NEXT:  .LBB8_2: # %entry
 ; SFB-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 
 define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
 ; NOSFB-LABEL: select_xor_2:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    xor a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_xor_2:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB9_2

  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
 ; NOSFB-LABEL: select_xor_2b:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    xor a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_xor_2b:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB10_2
 ; SFB-NEXT:  # %bb.1: # %entry
 ; SFB-NEXT:    xor a0, a0, a1
 ; SFB-NEXT:  .LBB10_2: # %entry
 ; SFB-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
 ; NOSFB-LABEL: select_or:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    or a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_or:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB11_2

  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
 ; NOSFB-LABEL: select_or_b:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    or a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_or_b:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB12_2
 ; SFB-NEXT:  # %bb.1: # %entry
 ; SFB-NEXT:    or a0, a0, a1
 ; SFB-NEXT:  .LBB12_2: # %entry
 ; SFB-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
 ; NOSFB-LABEL: select_or_1:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    or a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_or_1:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB13_2

  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
 ; NOSFB-LABEL: select_or_1b:
 ; NOSFB:       # %bb.0: # %entry
-; NOSFB-NEXT:    andi a2, a2, 1
-; NOSFB-NEXT:    neg a2, a2
+; NOSFB-NEXT:    slli a2, a2, 63
+; NOSFB-NEXT:    srai a2, a2, 63
 ; NOSFB-NEXT:    and a1, a1, a2
 ; NOSFB-NEXT:    or a0, a0, a1
 ; NOSFB-NEXT:    ret
 ;
 ; SFB-LABEL: select_or_1b:
 ; SFB:       # %bb.0: # %entry
 ; SFB-NEXT:    andi a2, a2, 1
 ; SFB-NEXT:    beqz a2, .LBB14_2

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

 ; RV32-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    mv s0, a0
-; RV32-NEXT:    lw a0, 4(a0)
-; RV32-NEXT:    lb a1, 12(s0)
-; RV32-NEXT:    lw a2, 8(s0)
-; RV32-NEXT:    andi a3, a0, 1
-; RV32-NEXT:    neg s1, a3
-; RV32-NEXT:    slli a3, a1, 30
-; RV32-NEXT:    srli a4, a2, 2
-; RV32-NEXT:    or s2, a4, a3
-; RV32-NEXT:    slli a1, a1, 29
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    neg s3, a1
-; RV32-NEXT:    slli a1, a2, 31
-; RV32-NEXT:    srli a0, a0, 1
-; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    lw s4, 0(s0)
-; RV32-NEXT:    slli a2, a2, 30
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    neg a1, a2
-; RV32-NEXT:    li a2, 7
+; RV32-NEXT:    lb a0, 12(a0)
+; RV32-NEXT:    lw a1, 8(s0)
+; RV32-NEXT:    slli a2, a0, 30
+; RV32-NEXT:    lw a3, 4(s0)
+; RV32-NEXT:    srli s1, a1, 2
+; RV32-NEXT:    or s1, s1, a2
+; RV32-NEXT:    slli a2, a1, 31
+; RV32-NEXT:    srli a4, a3, 1
+; RV32-NEXT:    or s2, a4, a2
+; RV32-NEXT:    srli a0, a0, 2
+; RV32-NEXT:    slli a0, a0, 31
+; RV32-NEXT:    srai s3, a0, 31
+; RV32-NEXT:    srli a1, a1, 1
+; RV32-NEXT:    slli a1, a1, 31
+; RV32-NEXT:    lw a0, 0(s0)
+; RV32-NEXT:    srai s4, a1, 31
+; RV32-NEXT:    slli a1, a3, 31
+; RV32-NEXT:    srai a1, a1, 31
+; RV32-NEXT:    li a2, 6
 ; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    call __moddi3@plt
 ; RV32-NEXT:    mv s5, a0
 ; RV32-NEXT:    mv s6, a1
-; RV32-NEXT:    li a2, -5
-; RV32-NEXT:    li a3, -1
+; RV32-NEXT:    li a2, 7
 ; RV32-NEXT:    mv a0, s2
-; RV32-NEXT:    mv a1, s3
+; RV32-NEXT:    mv a1, s4
+; RV32-NEXT:    li a3, 0
 ; RV32-NEXT:    call __moddi3@plt
 ; RV32-NEXT:    mv s2, a0
-; RV32-NEXT:    mv s3, a1
-; RV32-NEXT:    li a2, 6
-; RV32-NEXT:    mv a0, s4
-; RV32-NEXT:    mv a1, s1
-; RV32-NEXT:    li a3, 0
+; RV32-NEXT:    mv s4, a1
+; RV32-NEXT:    li a2, -5
+; RV32-NEXT:    li a3, -1
+; RV32-NEXT:    mv a0, s1
+; RV32-NEXT:    mv a1, s3
 ; RV32-NEXT:    call __moddi3@plt
-; RV32-NEXT:    xori a2, s2, 2
-; RV32-NEXT:    or a2, a2, s3
-; RV32-NEXT:    seqz a2, a2
-; RV32-NEXT:    xori a3, s5, 1
-; RV32-NEXT:    or a3, a3, s6
-; RV32-NEXT:    seqz a3, a3
+; RV32-NEXT:    or a2, s5, s6
+; RV32-NEXT:    snez a2, a2
+; RV32-NEXT:    xori a0, a0, 2
 ; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    snez a0, a0
-; RV32-NEXT:    addi a3, a3, -1
-; RV32-NEXT:    addi a2, a2, -1
-; RV32-NEXT:    neg a1, a0
-; RV32-NEXT:    sw a1, 0(s0)
-; RV32-NEXT:    andi a1, a2, 7
-; RV32-NEXT:    sb a1, 12(s0)
-; RV32-NEXT:    slli a1, a3, 1
+; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    xori a1, s2, 1
+; RV32-NEXT:    or a1, a1, s4
+; RV32-NEXT:    seqz a1, a1
+; RV32-NEXT:    neg a3, a2
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    sw a3, 0(s0)
+; RV32-NEXT:    andi a3, a0, 7
+; RV32-NEXT:    sb a3, 12(s0)
+; RV32-NEXT:    slli a3, a1, 1
+; RV32-NEXT:    or a2, a3, a2
+; RV32-NEXT:    sw a2, 4(s0)
+; RV32-NEXT:    srli a2, a1, 31
+; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    slli a1, a1, 1
+; RV32-NEXT:    or a1, a2, a1
+; RV32-NEXT:    slli a0, a0, 2
 ; RV32-NEXT:    or a0, a1, a0
-; RV32-NEXT:    sw a0, 4(s0)
-; RV32-NEXT:    srli a0, a3, 31
-; RV32-NEXT:    andi a3, a3, 1
-; RV32-NEXT:    slli a3, a3, 1
-; RV32-NEXT:    or a0, a0, a3
-; RV32-NEXT:    slli a2, a2, 2
-; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    sw a0, 8(s0)
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload

 ; RV32M-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
 ; RV32M-NEXT:    mv s0, a0
-; RV32M-NEXT:    lw a0, 4(a0)
-; RV32M-NEXT:    lb a1, 12(s0)
-; RV32M-NEXT:    lw a2, 8(s0)
-; RV32M-NEXT:    andi a3, a0, 1
-; RV32M-NEXT:    neg s1, a3
-; RV32M-NEXT:    slli a3, a1, 30
-; RV32M-NEXT:    srli a4, a2, 2
-; RV32M-NEXT:    or s2, a4, a3
-; RV32M-NEXT:    slli a1, a1, 29
-; RV32M-NEXT:    srli a1, a1, 31
-; RV32M-NEXT:    neg s3, a1
-; RV32M-NEXT:    slli a1, a2, 31
-; RV32M-NEXT:    srli a0, a0, 1
-; RV32M-NEXT:    or a0, a0, a1
-; RV32M-NEXT:    lw s4, 0(s0)
-; RV32M-NEXT:    slli a2, a2, 30
-; RV32M-NEXT:    srli a2, a2, 31
-; RV32M-NEXT:    neg a1, a2
-; RV32M-NEXT:    li a2, 7
+; RV32M-NEXT:    lb a0, 12(a0)
+; RV32M-NEXT:    lw a1, 8(s0)
+; RV32M-NEXT:    slli a2, a0, 30
+; RV32M-NEXT:    lw a3, 4(s0)
+; RV32M-NEXT:    srli s1, a1, 2
+; RV32M-NEXT:    or s1, s1, a2
+; RV32M-NEXT:    slli a2, a1, 31
+; RV32M-NEXT:    srli a4, a3, 1
+; RV32M-NEXT:    or s2, a4, a2
+; RV32M-NEXT:    srli a0, a0, 2
+; RV32M-NEXT:    slli a0, a0, 31
+; RV32M-NEXT:    srai s3, a0, 31
+; RV32M-NEXT:    srli a1, a1, 1
+; RV32M-NEXT:    slli a1, a1, 31
+; RV32M-NEXT:    lw a0, 0(s0)
+; RV32M-NEXT:    srai s4, a1, 31
+; RV32M-NEXT:    slli a1, a3, 31
+; RV32M-NEXT:    srai a1, a1, 31
+; RV32M-NEXT:    li a2, 6
 ; RV32M-NEXT:    li a3, 0
 ; RV32M-NEXT:    call __moddi3@plt
 ; RV32M-NEXT:    mv s5, a0
 ; RV32M-NEXT:    mv s6, a1
-; RV32M-NEXT:    li a2, -5
-; RV32M-NEXT:    li a3, -1
+; RV32M-NEXT:    li a2, 7
 ; RV32M-NEXT:    mv a0, s2
-; RV32M-NEXT:    mv a1, s3
+; RV32M-NEXT:    mv a1, s4
+; RV32M-NEXT:    li a3, 0
 ; RV32M-NEXT:    call __moddi3@plt
 ; RV32M-NEXT:    mv s2, a0
-; RV32M-NEXT:    mv s3, a1
-; RV32M-NEXT:    li a2, 6
-; RV32M-NEXT:    mv a0, s4
-; RV32M-NEXT:    mv a1, s1
-; RV32M-NEXT:    li a3, 0
+; RV32M-NEXT:    mv s4, a1
+; RV32M-NEXT:    li a2, -5
+; RV32M-NEXT:    li a3, -1
+; RV32M-NEXT:    mv a0, s1
+; RV32M-NEXT:    mv a1, s3
 ; RV32M-NEXT:    call __moddi3@plt
-; RV32M-NEXT:    xori a2, s2, 2
-; RV32M-NEXT:    or a2, a2, s3
-; RV32M-NEXT:    seqz a2, a2
-; RV32M-NEXT:    xori a3, s5, 1
-; RV32M-NEXT:    or a3, a3, s6
-; RV32M-NEXT:    seqz a3, a3
+; RV32M-NEXT:    or a2, s5, s6
+; RV32M-NEXT:    snez a2, a2
+; RV32M-NEXT:    xori a0, a0, 2
 ; RV32M-NEXT:    or a0, a0, a1
-; RV32M-NEXT:    snez a0, a0
-; RV32M-NEXT:    addi a3, a3, -1
-; RV32M-NEXT:    addi a2, a2, -1
-; RV32M-NEXT:    neg a1, a0
-; RV32M-NEXT:    sw a1, 0(s0)
-; RV32M-NEXT:    andi a1, a2, 7
-; RV32M-NEXT:    sb a1, 12(s0)
-; RV32M-NEXT:    slli a1, a3, 1
+; RV32M-NEXT:    seqz a0, a0
+; RV32M-NEXT:    xori a1, s2, 1
+; RV32M-NEXT:    or a1, a1, s4
+; RV32M-NEXT:    seqz a1, a1
+; RV32M-NEXT:    neg a3, a2
+; RV32M-NEXT:    addi a1, a1, -1
+; RV32M-NEXT:    addi a0, a0, -1
+; RV32M-NEXT:    sw a3, 0(s0)
+; RV32M-NEXT:    andi a3, a0, 7
+; RV32M-NEXT:    sb a3, 12(s0)
+; RV32M-NEXT:    slli a3, a1, 1
+; RV32M-NEXT:    or a2, a3, a2
+; RV32M-NEXT:    sw a2, 4(s0)
+; RV32M-NEXT:    srli a2, a1, 31
+; RV32M-NEXT:    andi a1, a1, 1
+; RV32M-NEXT:    slli a1, a1, 1
+; RV32M-NEXT:    or a1, a2, a1
+; RV32M-NEXT:    slli a0, a0, 2
 ; RV32M-NEXT:    or a0, a1, a0
-; RV32M-NEXT:    sw a0, 4(s0)
-; RV32M-NEXT:    srli a0, a3, 31
-; RV32M-NEXT:    andi a3, a3, 1
-; RV32M-NEXT:    slli a3, a3, 1
-; RV32M-NEXT:    or a0, a0, a3
-; RV32M-NEXT:    slli a2, a2, 2
-; RV32M-NEXT:    or a0, a0, a2
 ; RV32M-NEXT:    sw a0, 8(s0)
 ; RV32M-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload

 ; RV32MV-NEXT:    sw s4, 44(sp) # 4-byte Folded Spill
 ; RV32MV-NEXT:    sw s5, 40(sp) # 4-byte Folded Spill
 ; RV32MV-NEXT:    sw s6, 36(sp) # 4-byte Folded Spill
 ; RV32MV-NEXT:    addi s0, sp, 64
 ; RV32MV-NEXT:    andi sp, sp, -32
 ; RV32MV-NEXT:    mv s2, a0
 ; RV32MV-NEXT:    lw a0, 8(a0)
 ; RV32MV-NEXT:    lw a1, 4(s2)
-; RV32MV-NEXT:    slli a2, a0, 31
-; RV32MV-NEXT:    srli a3, a1, 1
-; RV32MV-NEXT:    or s3, a3, a2
 ; RV32MV-NEXT:    lb a2, 12(s2)
-; RV32MV-NEXT:    slli a3, a0, 30
-; RV32MV-NEXT:    srli a3, a3, 31
-; RV32MV-NEXT:    neg s4, a3
+; RV32MV-NEXT:    slli a3, a0, 31
+; RV32MV-NEXT:    srli a4, a1, 1
+; RV32MV-NEXT:    or s3, a4, a3
 ; RV32MV-NEXT:    slli a3, a2, 30
-; RV32MV-NEXT:    srli a0, a0, 2
-; RV32MV-NEXT:    or s5, a0, a3
-; RV32MV-NEXT:    slli a2, a2, 29
-; RV32MV-NEXT:    srli a2, a2, 31
+; RV32MV-NEXT:    srli a4, a0, 2
+; RV32MV-NEXT:    or s4, a4, a3
+; RV32MV-NEXT:    srli a0, a0, 1
+; RV32MV-NEXT:    slli a0, a0, 31
+; RV32MV-NEXT:    srai s5, a0, 31
+; RV32MV-NEXT:    srli a2, a2, 2
+; RV32MV-NEXT:    slli a2, a2, 31
 ; RV32MV-NEXT:    lw a0, 0(s2)
-; RV32MV-NEXT:    neg s6, a2
-; RV32MV-NEXT:    andi a1, a1, 1
-; RV32MV-NEXT:    neg a1, a1
+; RV32MV-NEXT:    srai s6, a2, 31
+; RV32MV-NEXT:    slli a1, a1, 31
+; RV32MV-NEXT:    srai a1, a1, 31
 ; RV32MV-NEXT:    li a2, 6
 ; RV32MV-NEXT:    li a3, 0
 ; RV32MV-NEXT:    call __moddi3@plt
 ; RV32MV-NEXT:    sw a1, 4(sp)
 ; RV32MV-NEXT:    sw a0, 0(sp)
 ; RV32MV-NEXT:    li a2, -5
 ; RV32MV-NEXT:    li a3, -1
-; RV32MV-NEXT:    mv a0, s5
+; RV32MV-NEXT:    mv a0, s4
 ; RV32MV-NEXT:    mv a1, s6
 ; RV32MV-NEXT:    call __moddi3@plt
 ; RV32MV-NEXT:    sw a1, 20(sp)
 ; RV32MV-NEXT:    sw a0, 16(sp)
 ; RV32MV-NEXT:    li a2, 7
 ; RV32MV-NEXT:    mv a0, s3
-; RV32MV-NEXT:    mv a1, s4
+; RV32MV-NEXT:    mv a1, s5
 ; RV32MV-NEXT:    li a3, 0
 ; RV32MV-NEXT:    call __moddi3@plt
 ; RV32MV-NEXT:    sw a1, 12(sp)
 ; RV32MV-NEXT:    sw a0, 8(sp)
 ; RV32MV-NEXT:    li a0, 85
 ; RV32MV-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
 ; RV32MV-NEXT:    vmv.s.x v0, a0
 ; RV32MV-NEXT:    vsetivli zero, 8, e32, m2, ta, ma