Disassembler can successfully decode sgpr register when only vgpr
registers are valid for the operand (e.g. VReg_* and VISrc_* operands).
In InstPrinter, detect when operand register class does not contain
register that is being printed. Does not result in an error.
Intended use is for disassembler tests.
Details
Details
Diff Detail
Diff Detail
Event Timeline
| llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | ||
|---|---|---|
| 678 | I don't know what is going on here but if we check for other classes there is a lot of errors. Related to registers with special name not being member of register class, common error is that M0 is not in SReg_32. | |
Comment Actions
Overall looks good.
| llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | ||
|---|---|---|
| 678 | The reason for these failures is that we have two kinds of registers - preudo and real. The latter are necessary to reflect the fact that some registers have different encodings on different GPUs. So you have to use mc2PseudoReg. But this correction is insufficient. We also have some registers which are used in MC only. They are defined as 32-bit registers in td, but MC can use them where wider operands are expected. So your code may be corrected as follows: const MCRegisterClass *RC = &MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
auto Reg = mc2PseudoReg(Op.getReg());
if (!RC->contains(Reg) && !isInlineValue(Reg)) {
StringRef RCName(MRI.getRegClassName(RC));
O << "/*Invalid register, operand has \'" << RCName
<< "\' register class*/";
}
} | |
Comment Actions
LGTM with a nit.
| llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | ||
|---|---|---|
| 1129 ↗ | (On Diff #481645) | Should be tagged LLVM_READNONE. |
I don't know what is going on here but if we check for other classes there is a lot of errors. Related to registers with special name not being member of register class, common error is that M0 is not in SReg_32.