AMDGPU/MC: Make VReg and VISrc decoders more strict

[Petar.Avramovic]

Summary

These are operands that use 9 bit src operand encoding
but still don't allow sgprs and inline immediates.
Report decoding fail when operands are invalid values.

[dp]

By design, disassembler should be able to decode invalid code when possible. It is much more helpful for the user to see something like this:

v_wmma_f32_16x16x16_f16  … s[0:7], …

or

v_wmma_f32_16x16x16_f16  … /*invalid immediate*/, …

than this:

warning: invalid instruction encoding

Would it be possible to modify your patch and decode invalid operands with a comment stating that they are incorrect?

[Petar.Avramovic]

In most cases if instruction can't use some bits in encoding of an operand, those bits are set to default value in td file. Disassembler fails (in generic way) in this cases and does not print e.g. "instruction must use glc" (assembler prints such verbose warnings)

This is the corner case where some combinations of bits in the operand encoding are not allowed. Those cases are too complicated to be implemented in tablegen encoding so I moved it to decoder.

Would it be possible to modify your patch and decode invalid operands with a comment stating that they are incorrect?

I don't know where would be the best place to implement it, but as far I am aware it is not done for any other instruction.
Maybe return errOperand instead of MCOperand() but it does not seem to make any difference.
Another option would be to make new OperandType and write some error msg in InstPrinter (I would print normal src operand + msg that operand value is invalid and reason why(e.g. not vgpr/not vgpr or inline imm)).

[dp]

In most cases if instruction can't use some bits in encoding of an operand, those bits are set to default value in td file.

AFAIK, we use ? as a default value to allow disassembler ignore these bits.

Another option would be to make new OperandType and write some error msg in InstPrinter (I would print normal src operand + msg that operand value is invalid and reason why(e.g. not vgpr/not vgpr or inline imm)).

I think that would be perfect!

[Petar.Avramovic]

Another attempt in D139646, I could to get anything better with tools available in InstPrinter.
OperandType would not make much difference (maybe for printing more verbose error for /*invalid immediate*/), I skipped adding it for now since it was possible to print some meaningful msg without it.

As for better dissasembler diagnostic when sgpr/imm was used in VReg_* and VISrc_*, /*invalid immediate*/ and D139646 address them in good enough way.
It would probably be better if we could make more verbose warning than warning: invalid instruction encoding in some place before InstrPrinter.

[arsenm]

Is this still relevant with D139646 committed?

[Petar.Avramovic]

Implemented D139646 instead.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   bool isVISrc_64V2FP32() const {
     return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);
   }
 
   bool isVISrc_64V2INT32() const {
     return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);
   }
 
+  bool isVISrc_256F32() const {
+    return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);
+  }
+
   bool isVISrc_256B64() const {
     return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);
   }
 
   bool isVISrc_256F64() const {
     return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);
   }
 

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

public:
 
   MCOperand decodeOperand_VS_32(unsigned Val) const;
   MCOperand decodeOperand_VS_64(unsigned Val) const;
   MCOperand decodeOperand_VS_128(unsigned Val) const;
   MCOperand decodeOperand_VSrc16(unsigned Val) const;
   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
   MCOperand decodeOperand_VSrcV232(unsigned Val) const;
 
+  MCOperand decodeOperand_VReg_32(unsigned Val) const;
   MCOperand decodeOperand_VReg_64(unsigned Val) const;
   MCOperand decodeOperand_VReg_96(unsigned Val) const;
   MCOperand decodeOperand_VReg_128(unsigned Val) const;
   MCOperand decodeOperand_VReg_256(unsigned Val) const;
   MCOperand decodeOperand_VReg_288(unsigned Val) const;
   MCOperand decodeOperand_VReg_320(unsigned Val) const;
   MCOperand decodeOperand_VReg_352(unsigned Val) const;
   MCOperand decodeOperand_VReg_384(unsigned Val) const;
public:
 
   static MCOperand decodeIntImmed(unsigned Imm);
   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
   MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
   MCOperand decodeLiteralConstant() const;
 
   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
                         bool MandatoryLiteral = false) const;
+  MCOperand decodeVSrcOp(const OpWidthTy Width, unsigned Val) const;
+  MCOperand decodeVISrcOp(const OpWidthTy Width, unsigned Val,
+                          unsigned TypeSize) const;
   MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
   MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
   MCOperand decodeSpecialReg32(unsigned Val) const;
   MCOperand decodeSpecialReg64(unsigned Val) const;
 
   MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
   MCOperand decodeSDWASrc16(unsigned Val) const;
   MCOperand decodeSDWASrc32(unsigned Val) const;

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

#define DECODE_OPERAND(StaticDecoderName, DecoderName)                         \
   }
 
 #define DECODE_OPERAND_REG(RegClass) \
 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
 
 DECODE_OPERAND_REG(VGPR_32)
 DECODE_OPERAND_REG(VGPR_32_Lo128)
 DECODE_OPERAND_REG(VRegOrLds_32)
-DECODE_OPERAND_REG(VS_32)
 DECODE_OPERAND_REG(VS_64)
 DECODE_OPERAND_REG(VS_128)
 
 DECODE_OPERAND_REG(VReg_64)
 DECODE_OPERAND_REG(VReg_96)
 DECODE_OPERAND_REG(VReg_128)
 DECODE_OPERAND_REG(VReg_256)
 DECODE_OPERAND_REG(VReg_288)

 
 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm,
                                             uint64_t Addr,
                                             const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
 }
 
+static DecodeStatus decodeOperand_VReg_32(MCInst &Inst, unsigned Imm,
+                                          uint64_t Addr,
+                                          const MCDisassembler *Decoder) {
+  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
+  return addOperand(Inst, DAsm->decodeVSrcOp(AMDGPUDisassembler::OPW32, Imm));
+}
+
 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm,
                                           uint64_t Addr,
                                           const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
+  return addOperand(Inst, DAsm->decodeVSrcOp(AMDGPUDisassembler::OPW64, Imm));
 }
 
 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
                                            const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm));
+  return addOperand(Inst, DAsm->decodeVSrcOp(AMDGPUDisassembler::OPW128, Imm));
 }
 
 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm,
                                            uint64_t Addr,
                                            const MCDisassembler *Decoder) {
   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm));
+  return addOperand(Inst, DAsm->decodeVSrcOp(AMDGPUDisassembler::OPW256, Imm));
+}
+
+static DecodeStatus decodeOperand_VISrc_64_64(MCInst &Inst, unsigned Imm,
+                                              uint64_t Addr,
+                                              const MCDisassembler *Decoder) {
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW64, Imm, 64));
+}
+
+static DecodeStatus decodeOperand_VISrc_128(MCInst &Inst, unsigned Imm,
+                                            uint64_t Addr,
+                                            const MCDisassembler *Decoder) {
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW128, Imm, 32));
+}
+
+static DecodeStatus decodeOperand_VISrc_256(MCInst &Inst, unsigned Imm,
+                                            uint64_t Addr,
+                                            const MCDisassembler *Decoder) {
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW256, Imm, 32));
+}
+
+static DecodeStatus decodeOperand_VISrc_256_64(MCInst &Inst, unsigned Imm,
+                                               uint64_t Addr,
+                                               const MCDisassembler *Decoder) {
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW256, Imm, 64));
 }
 
-static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VISrc_512(MCInst &Inst, unsigned Imm,
                                             uint64_t Addr,
                                             const MCDisassembler *Decoder) {
-  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm));
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW512, Imm, 32));
 }
 
-static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm,
+static DecodeStatus decodeOperand_VISrc_1024(MCInst &Inst, unsigned Imm,
                                              uint64_t Addr,
                                              const MCDisassembler *Decoder) {
-  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
-  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm));
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst,
+                    DAsm->decodeVISrcOp(AMDGPUDisassembler::OPW1024, Imm, 32));
 }
 
 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm,
                                           uint64_t Addr,
                                           const MCDisassembler *Decoder) {
   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
 }

 }
 
 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const {
   using namespace AMDGPU::EncValues;
   assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1.
   return decodeSrcOp(OPW512, Val | IS_VGPR);
 }
 
+MCOperand AMDGPUDisassembler::decodeOperand_VReg_32(unsigned Val) const {
+  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
+}
+
 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
 }
 
 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
 }
 
MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,
   case OPW64:
   case OPWV232:
     return decodeSpecialReg64(Val);
   default:
     llvm_unreachable("unexpected immediate type");
   }
 }
 
+MCOperand AMDGPUDisassembler::decodeVSrcOp(const OpWidthTy Width,
+                                           unsigned Val) const {
+  using namespace AMDGPU::EncValues;
+
+  assert(Val < 1024); // enum10
+
+  if (VGPR_MIN <= Val && Val <= VGPR_MAX)
+    return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
+
+  return MCOperand();
+}
+
+MCOperand AMDGPUDisassembler::decodeVISrcOp(const OpWidthTy Width, unsigned Val,
+                                            unsigned TypeSize) const {
+  using namespace AMDGPU::EncValues;
+
+  assert(Val < 1024); // enum10
+
+  if (VGPR_MIN <= Val && Val <= VGPR_MAX)
+    return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
+
+  // Classes that use this are marked with type. However asm parser does not
+  // care about int/float type only bit width. Floating point instruction
+  // accepts integer literal and vice versa.
+  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
+    return decodeIntImmed(Val);
+
+  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) {
+    assert(TypeSize == 32 || TypeSize == 64);
+    if (TypeSize == 32)
+      return MCOperand::createImm(getInlineImmVal32(Val));
+    return MCOperand::createImm(getInlineImmVal64(Val));
+  }
+
+  return MCOperand();
+}
+
 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
   using namespace AMDGPU::EncValues;
 
   assert(Val < 128);
   assert(Width == OPW256 || Width == OPW512);
 
   if (Val <= SGPR_MAX) {
     // "SGPR_MIN <= Val" is always true and causes compilation warning.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

 //===----------------------------------------------------------------------===//
 //  VRegSrc_* Operands with a VGPR
 //===----------------------------------------------------------------------===//
 
 // This is for operands with the enum(9), VSrc encoding restriction,
 // but only allows VGPRs.
 def VRegSrc_32 : RegisterOperand<VGPR_32> {
   //let ParserMatchClass = RegImmMatcher<"VRegSrc32">;
-  let DecoderMethod = "DecodeVS_32RegisterClass";
+  let DecoderMethod = "decodeOperand_VReg_32";
 }
 
 def VRegSrc_64 : RegisterOperand<VReg_64> {
   let DecoderMethod = "decodeOperand_VReg_64";
 }
 
 def VRegSrc_128 : RegisterOperand<VReg_128> {
   let DecoderMethod = "decodeOperand_VReg_128";

 
 defm VCSrc : RegInlineOperand<"VS", "VCSrc">;
 defm VCSrcT : SIRegOperand16<"VS", "VCSrcT", "OPERAND_REG_INLINE_C">;
 
 //===----------------------------------------------------------------------===//
 //  VISrc_* Operands with a VGPR or an inline constant
 //===----------------------------------------------------------------------===//
 
+let DecoderMethod = "decodeOperand_VISrc_32" in
 defm VISrc : RegInlineOperand32<"VGPR", "VISrc">;
-let DecoderMethod = "decodeOperand_VReg_64" in
-defm VISrc_64   : RegInlineOperand64<"VReg", "VISrc_64",   "_64">;
+let DecoderMethod = "decodeOperand_VISrc_128" in
 defm VISrc_128  : RegInlineOperandAC<"VReg", "VISrc_128",  "_128">;
-let DecoderMethod = "decodeOperand_VReg_256" in
-defm VISrc_256  : RegInlineOperand64<"VReg", "VISrc_256",  "_256">;
+
+def VISrc_256_f32 : RegisterOperand<!cast<RegisterClass>(VReg_256)> {
+  let OperandNamespace = "AMDGPU";
+  let OperandType = "OPERAND_REG_INLINE_C_FP32";
+  let ParserMatchClass = RegImmMatcher<"VISrc_256F32">;
+  let DecoderMethod = "decodeOperand_VISrc_256";
+}
+
+let DecoderMethod = "decodeOperand_VISrc_512" in
 defm VISrc_512  : RegInlineOperandAC<"VReg", "VISrc_512",  "_512">;
+let DecoderMethod = "decodeOperand_VISrc_1024" in
 defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">;
 
+let DecoderMethod = "decodeOperand_VISrc_64_64" in
+defm VISrc_64   : RegInlineOperand64<"VReg", "VISrc_64",   "_64">;
+let DecoderMethod = "decodeOperand_VISrc_256_64" in
+defm VISrc_256  : RegInlineOperand64<"VReg", "VISrc_256",  "_256">;
+
 //===----------------------------------------------------------------------===//
 //  AVSrc_*, AVDst_*, AVLdSt_* Operands with an AGPR or VGPR
 //===----------------------------------------------------------------------===//
 
 def AVSrc_32 : RegisterOperand<AV_32> {
   let DecoderMethod = "DecodeAV_32RegisterClass";
   let EncoderMethod = "getAVOperandEncoding";
 }

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

 
 def : MnemonicAlias<"v_accvgpr_read",  "v_accvgpr_read_b32">;
 def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
 
 class VOPProfileWMMA<VOPProfile P, string Suffix, RegisterOperand _Src01RC64, bit _HasClamp, bit _HasOpSel> : VOP3P_Profile<P> {
   let DstRC = !if(!eq(Suffix, "_w32"), VDst_256, VDst_128);
   let Src0RC64 = _Src01RC64;
   let Src1RC64 = _Src01RC64;
-  let Src2RC64 = !if(!eq(Suffix, "_w32"), VISrc_256_f64, VISrc_128_f32);
+  let Src2RC64 = !if(!eq(Suffix, "_w32"), VISrc_256_f32, VISrc_128_f32);
   let HasClamp = _HasClamp;
   let HasOpSel = _HasOpSel;
   let IsPacked = 1;
   let IsWMMA = 1;
 }
 
 def VOP_V8F32_V16F16_V16F16_V8F32 : VOPProfile <[v8f32, v16f16, v16f16, v8f32]>;
 def VOP_V8F32_V16I16_V16I16_V8F32 : VOPProfile <[v8f32, v16i16, v16i16, v8f32]>;

llvm/test/MC/Disassembler/AMDGPU/decode-err.txt

 # RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefix=GCN %s
-# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W32 %s
-# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=GFX11,W64 %s
+# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefix=W32 %s
+# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck --implicit-check-not=warning: --check-prefix=W32-ERR %s
+# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding < %s | FileCheck -check-prefix=W64 %s
+# RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-WavefrontSize32,+WavefrontSize64 -disassemble -show-encoding %s 2>&1 | FileCheck --implicit-check-not=warning: --check-prefix=W64-ERR %s
 
 # GCN: warning: invalid instruction encoding
+# W32-ERR: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0xdf,0x00,0x00,0x02]
 
 # this is buffer_atomic_csub_u32 v5, off, s[8:11], s3 offset:4095. Invalid without glc
-# GFX11: warning: invalid instruction encoding
+# W32-ERR: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03]
 
 # W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
-# W64: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], /*invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], /*invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W32-ERR: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c] # src0 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W32-ERR: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] # src0 sgpr0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b] # src2 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W32-ERR: warning: invalid instruction encoding
+# W64-ERR: warning: invalid instruction encoding
 [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18] # src2 sgpr0