AMDGPU: Check if operand RC contains register used when printing

[Petar.Avramovic]

Summary

Disassembler can successfully decode sgpr register when only vgpr
registers are valid for the operand (e.g. VReg_* and VISrc_* operands).
In InstPrinter, detect when operand register class does not contain
register that is being printed. Does not result in an error.
Intended use is for disassembler tests.

[Petar.Avramovic]

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

678

I don't know what is going on here but if we check for other classes there is a lot of errors. Related to registers with special name not being member of register class, common error is that M0 is not in SReg_32.

[dp]

Overall looks good.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

678

The reason for these failures is that we have two kinds of registers - preudo and real. The latter are necessary to reflect the fact that some registers have different encodings on different GPUs. So you have to use mc2PseudoReg.

But this correction is insufficient. We also have some registers which are used in MC only. They are defined as 32-bit registers in td, but MC can use them where wider operands are expected.

So your code may be corrected as follows:

const MCRegisterClass *RC = &MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
auto Reg = mc2PseudoReg(Op.getReg());
if (!RC->contains(Reg) && !isInlineValue(Reg)) {
    StringRef RCName(MRI.getRegClassName(RC));
    O << "/*Invalid register, operand has \'" << RCName
      << "\' register class*/";
  }
}

[dp]

LGTM with a nit.

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

1134

Should be tagged LLVM_READNONE.

[Petar.Avramovic]

Thanks for the review.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

FPLiteral.convert(*getFltSemantics(Bitwidth / 8),
                     APFloat::rmNearestTiesToEven, &Lost);
   Inst.addOperand(MCOperand::createImm(FPLiteral.bitcastToAPInt().getZExtValue()));
 }
 
 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {
   Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
 }
 
-static bool isInlineValue(unsigned Reg) {
-  switch (Reg) {
-  case AMDGPU::SRC_SHARED_BASE_LO:
-  case AMDGPU::SRC_SHARED_BASE:
-  case AMDGPU::SRC_SHARED_LIMIT_LO:
-  case AMDGPU::SRC_SHARED_LIMIT:
-  case AMDGPU::SRC_PRIVATE_BASE_LO:
-  case AMDGPU::SRC_PRIVATE_BASE:
-  case AMDGPU::SRC_PRIVATE_LIMIT_LO:
-  case AMDGPU::SRC_PRIVATE_LIMIT:
-  case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
-    return true;
-  case AMDGPU::SRC_VCCZ:
-  case AMDGPU::SRC_EXECZ:
-  case AMDGPU::SRC_SCC:
-    return true;
-  case AMDGPU::SGPR_NULL:
-    return true;
-  default:
-    return false;
-  }
-}
-
 bool AMDGPUOperand::isInlineValue() const {
   return isRegKind() && ::isInlineValue(getReg());
 }
 
 //===----------------------------------------------------------------------===//
 // AsmParser
 //===----------------------------------------------------------------------===//
 

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
   if (OpNo >= MI->getNumOperands()) {
     O << "/*Missing OP" << OpNo << "*/";
     return;
   }
 
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegOperand(Op.getReg(), O, MRI);
+
+    // Check if operand register class contains register used.
+    // Intention: print disassembler message when invalid code is decoded,
+    // for example sgpr register used in VReg or VISrc(VReg or imm) operand.
+    int RCID = Desc.OpInfo[OpNo].RegClass;
+    if (RCID != -1) {
+      const MCRegisterClass RC = MRI.getRegClass(RCID);
+      auto Reg = mc2PseudoReg(Op.getReg());
+      if (!RC.contains(Reg) && !isInlineValue(Reg)) {
+        O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC)
+          << "\' register class*/";
+      }
+    }
   } else if (Op.isImm()) {
     const uint8_t OpTy = Desc.OpInfo[OpNo].OperandType;
     switch (OpTy) {
     case AMDGPU::OPERAND_REG_IMM_INT32:
     case AMDGPU::OPERAND_REG_IMM_FP32:
     case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
     case AMDGPU::OPERAND_REG_INLINE_C_INT32:
     case AMDGPU::OPERAND_REG_INLINE_C_FP32:

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 /// If \p Reg is a pseudo reg, return the correct hardware register given
 /// \p STI otherwise return \p Reg.
 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
 
 /// Convert hardware register \p Reg to a pseudo register
 LLVM_READNONE
 unsigned mc2PseudoReg(unsigned Reg);
 
+LLVM_READNONE
+bool isInlineValue(unsigned Reg);
+
 /// Is this an AMDGPU specific source operand? These include registers,
 /// inline constants, literals and mandatory literals (KImm).
 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// Is this a KImm operand?
 bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
 /// Is this floating-point operand?

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 #define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
 #define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
 #define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
 
 unsigned mc2PseudoReg(unsigned Reg) {
   MAP_REG2REG
 }
 
+bool isInlineValue(unsigned Reg) {
+  switch (Reg) {
+  case AMDGPU::SRC_SHARED_BASE_LO:
+  case AMDGPU::SRC_SHARED_BASE:
+  case AMDGPU::SRC_SHARED_LIMIT_LO:
+  case AMDGPU::SRC_SHARED_LIMIT:
+  case AMDGPU::SRC_PRIVATE_BASE_LO:
+  case AMDGPU::SRC_PRIVATE_BASE:
+  case AMDGPU::SRC_PRIVATE_LIMIT_LO:
+  case AMDGPU::SRC_PRIVATE_LIMIT:
+  case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
+    return true;
+  case AMDGPU::SRC_VCCZ:
+  case AMDGPU::SRC_EXECZ:
+  case AMDGPU::SRC_SCC:
+    return true;
+  case AMDGPU::SGPR_NULL:
+    return true;
+  default:
+    return false;
+  }
+}
+
 #undef CASE_CI_VI
 #undef CASE_VI_GFX9PLUS
 #undef CASE_GFXPRE11_GFX11PLUS
 #undef CASE_GFXPRE11_GFX11PLUS_TO
 #undef MAP_REG2REG
 
 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
   assert(OpNo < Desc.NumOperands);

llvm/test/MC/Disassembler/AMDGPU/decode-err.txt

 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], /*invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], /*invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0
 
-# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
+# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
 0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0