[SPARC] Mark the %g0 register as constant & use it to materialize zeros

[koakuma]

Summary

Materialize zeros by copying from %g0, which is now marked as constant.
This makes it possible for some common operations (like integer negation) to be performed in fewer instructions.

This continues @arichardson's patch at D132561.

[jrtc27]

llvm/test/CodeGen/SPARC/bigreturn.ll

139

This is a bit nonsense, it copies the %g0+%g1 register pair into %i4+%i5 then copies %g0 into %i5... it works but it's a regression and points at something very suspect going on

[koakuma]

• Mark i64 zero materialization as for 64-bit target only.
• Use ORrr instead of the default COPY to zero the upper half of a register pair. Using COPY there will result in LLVM changing the COPY G0 operation to a COPY G0_G1 operation, which is not what we want in this case. Note that in all other cases turning COPY G0 to COPY G0_G1 is the right thing to do; zeroing is simply an exception to that rule.

[brad]

@jrtc27 @arsenm

[brad]

The tests pass fine with the clang-x86_64-debian-fast buildbot, but fail with the llvm-clang-x86_64-expensive-checks-debian buildbot..

******************** TEST 'LLVM :: CodeGen/SPARC/bigreturn.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll -mtriple=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck --check-prefix=SPARC /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll
: 'RUN: at line 3';   /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll -mtriple=sparc64 -disable-sparc-delay-filler -disable-sparc-leaf-proc | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck --check-prefix=SPARC64 /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll
--
Exit Code: 2
Command Output (stderr):
--
+ : 'RUN: at line 2'
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck --check-prefix=SPARC /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc
# After Instruction Selection
# Machine code for function ret_i64_pair: IsSSA, TracksLiveness
Function Live Ins: $i2 in %2, $i3 in %3
bb.0 (%ir-block.0):
  liveins: $i2, $i3
  %3:intregs = COPY $i3
  %2:intregs = COPY $i2
  %4:intpair = LDDrr %2:intregs, $g0 :: (load (s64) from %ir.p)
  %5:intregs = COPY %4.sub_even:intpair
  %6:intregs = COPY %4.sub_odd:intpair
  %7:intregs = ORrr $g0, $g0
  %9:intpair = IMPLICIT_DEF
  %8:intpair = INSERT_SUBREG %9:intpair(tied-def 0), killed %7:intregs, %subreg.sub_even
  %10:intpair = INSERT_SUBREG %8:intpair(tied-def 0), $g0, %subreg.sub_odd
  STDrr %2:intregs, $g0, killed %10:intpair :: (store (s64) into %ir.p)
  %11:intpair = LDDrr %3:intregs, $g0 :: (load (s64) from %ir.q)
  %12:intregs = COPY %11.sub_even:intpair
  %13:intregs = COPY %11.sub_odd:intpair
  $i0 = COPY %5:intregs
  $i1 = COPY %6:intregs
  $i2 = COPY %12:intregs
  $i3 = COPY %13:intregs
  RETL 8, implicit $i0, implicit $i1, implicit $i2, implicit $i3
# End machine code for function ret_i64_pair.
*** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***
- function:    ret_i64_pair
- basic block: %bb.0  (0x8b124a8)
- instruction: %10:intpair = INSERT_SUBREG %8:intpair(tied-def 0), $g0, %subreg.sub_odd
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'Verify generated machine code' on function '@ret_i64_pair'
 #0 0x0000000002d5f413 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2d5f413)
 #1 0x0000000002d5d19e llvm::sys::RunSignalHandlers() (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2d5d19e)
 #2 0x0000000002d5f79f SignalHandler(int) Signals.cpp:0:0
 #3 0x00007f4563855140 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x13140)
 #4 0x00007f4563339ce1 raise (/lib/x86_64-linux-gnu/libc.so.6+0x38ce1)
 #5 0x00007f4563323537 abort (/lib/x86_64-linux-gnu/libc.so.6+0x22537)
 #6 0x0000000002cd2470 llvm::report_fatal_error(llvm::Twine const&, bool) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2cd2470)
 #7 0x00000000021a8a5f (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x21a8a5f)
 #8 0x00000000020e8162 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x20e8162)
 #9 0x000000000256da8a llvm::FPPassManager::runOnFunction(llvm::Function&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x256da8a)
#10 0x00000000025742f8 llvm::FPPassManager::runOnModule(llvm::Module&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x25742f8)
#11 0x000000000256e1b7 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x256e1b7)
#12 0x000000000075b2ec main (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x75b2ec)
#13 0x00007f4563324d0a __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x23d0a)
#14 0x000000000075894a _start (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x75894a)
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck --check-prefix=SPARC /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/bigreturn.ll

******************** TEST 'LLVM :: CodeGen/SPARC/mult-alt-generic-sparc.ll' FAILED ********************
Script:
--
: 'RUN: at line 1';   /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll -march=sparc -no-integrated-as
--
Exit Code: 134
Command Output (stderr):
--
+ : 'RUN: at line 1'
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -march=sparc -no-integrated-as
# After Instruction Selection
# Machine code for function single_E: IsSSA, TracksLiveness
Frame Objects:
  fi#0: size=8, align=8, at location [SP]
bb.0.entry:
  %0:intregs = ORrr $g0, $g0
  %2:intpair = IMPLICIT_DEF
  %1:intpair = INSERT_SUBREG %2:intpair(tied-def 0), killed %0:intregs, %subreg.sub_even
  %3:intpair = INSERT_SUBREG %1:intpair(tied-def 0), $g0, %subreg.sub_odd
  STDri %stack.0.out0, 0, killed %3:intpair :: (store (s64) into %ir.out0)
  RETL 8
# End machine code for function single_E.
*** Bad machine code: INSERT_SUBREG expected inserted value to have equal or lesser size than the subreg it was inserted into ***
- function:    single_E
- basic block: %bb.0 entry (0x72aca58)
- instruction: %3:intpair = INSERT_SUBREG %1:intpair(tied-def 0), $g0, %subreg.sub_odd
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -march=sparc -no-integrated-as
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'Verify generated machine code' on function '@single_E'
 #0 0x0000000002d5f413 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2d5f413)
 #1 0x0000000002d5d19e llvm::sys::RunSignalHandlers() (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2d5d19e)
 #2 0x0000000002d5f79f SignalHandler(int) Signals.cpp:0:0
 #3 0x00007f0e4b8c8140 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x13140)
 #4 0x00007f0e4b3acce1 raise (/lib/x86_64-linux-gnu/libc.so.6+0x38ce1)
 #5 0x00007f0e4b396537 abort (/lib/x86_64-linux-gnu/libc.so.6+0x22537)
 #6 0x0000000002cd2470 llvm::report_fatal_error(llvm::Twine const&, bool) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x2cd2470)
 #7 0x00000000021a8a5f (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x21a8a5f)
 #8 0x00000000020e8162 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x20e8162)
 #9 0x000000000256da8a llvm::FPPassManager::runOnFunction(llvm::Function&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x256da8a)
#10 0x00000000025742f8 llvm::FPPassManager::runOnModule(llvm::Module&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x25742f8)
#11 0x000000000256e1b7 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x256e1b7)
#12 0x000000000075b2ec main (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x75b2ec)
#13 0x00007f0e4b397d0a __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x23d0a)
#14 0x000000000075894a _start (/b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc+0x75894a)
/b/1/llvm-clang-x86_64-expensive-checks-debian/build/test/CodeGen/SPARC/Output/mult-alt-generic-sparc.ll.script: line 1: 371281 Aborted                 /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -march=sparc -no-integrated-as < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll

[koakuma]

Anything else that I need to do here? I can't seem to reproduce the errors locally.

[jrtc27]

Are you trying with -DLLVM_ENABLE_EXPENSIVE_CHECKS=ON?

[brad]

In D138887#3980307, @jrtc27 wrote:

Are you trying with -DLLVM_ENABLE_EXPENSIVE_CHECKS=ON?

I was going to ask what the expensive checks part of the build bot name was referring to, but that is probably it.

[koakuma]

In D138887#3980307, @jrtc27 wrote:

Are you trying with -DLLVM_ENABLE_EXPENSIVE_CHECKS=ON?

This should be passed on to cmake, right? I think I haven't enabled this, let me try again with it turned on.

[brad]

In D138887#3980314, @koakuma wrote:

This should be passed on to cmake, right? I think I haven't enabled this, let me try again with it turned on.

Yes.

[craig.topper]

In D138887#3980315, @brad wrote:

In D138887#3980314, @koakuma wrote:

This should be passed on to cmake, right? I think I haven't enabled this, let me try again with it turned on.

Yes.

You might be able to add -verify-machine-instrs to the llc command line of the failing test instead of rebuilding the compiler.

[koakuma]

I noticed that in the "Zero register pair" pattern, LLVM really does not like using an explicit copying from %g0 to set the lower half, even when bitcasted into i32 as in the previous version of the patch, so I generalized the pattern to match the materialization of any (0, X) register pair. This works since we really only care about preventing LLVM from selecting a register pair copy (i.e. COPY G0_G1) during the filling of the upper part.

This should fix the two problematic testcases without affecting the rest.

llvm/lib/Target/Sparc/SparcInstr64Bit.td

 //
 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
 // immediates may require more code. There may be a point where it is
 // preferable to use a constant pool load instead, depending on the
 // microarchitecture.
 
 // Single-instruction patterns.
 
+// Zero immediate.
+def : Pat<(i64 0), (COPY (i64 G0))>,
+  Requires<[Is64Bit]>;
+
 // The ALU instructions want their simm13 operands as i32 immediates.
 def as_i32imm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
 
 // Double-instruction patterns.

llvm/lib/Target/Sparc/SparcInstrInfo.td

def WRPRri : F3_2<2, 0b110010,
                    "wrpr $rs1, $simm13, $rd", []>;
 }
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
 // Zero immediate.
-def : Pat<(i32 0),
-          (ORrr (i32 G0), (i32 G0))>;
+def : Pat<(i32 0), (COPY (i32 G0))>;
 // Small immediates.
 def : Pat<(i32 simm13:$val),
           (ORri (i32 G0), imm:$val)>;
 // Arbitrary immediates.
 def : Pat<(i32 imm:$val),
           (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 
 

 // atomic_store val, addr -> store val, addr
 def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
 def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
 def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
 def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
 
+// A register pair with zero upper half.
+// The upper part is done with ORrr instead of `COPY G0`
+// or a normal register copy, since `COPY G0`s in that place
+// will be converted into `COPY G0_G1` later on, which is not
+// what we want in this case.
+def : Pat<(build_vector (i32 0), (i32 IntRegs:$a2)),
+          (INSERT_SUBREG (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
+            (ORrr (i32 G0), (i32 G0)), sub_even),
+            (i32 IntRegs:$a2), sub_odd)>;
+
 // extract_vector
 def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
           (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
           (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
 
 // build_vector
 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
           (INSERT_SUBREG
       (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
             (i32 IntRegs:$a2), sub_odd)>;
 
 
 include "SparcInstr64Bit.td"
 include "SparcInstrVIS.td"
 include "SparcInstrAliases.td"

llvm/lib/Target/Sparc/SparcRegisterInfo.td

 def CWP : SparcCtrlReg<9, "CWP">;
 def CANSAVE : SparcCtrlReg<10, "CANSAVE">;
 def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">;
 def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">;
 def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
 def WSTATE : SparcCtrlReg<14, "WSTATE">;
 
 // Integer registers
-def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
+def G0 : Ri< 0, "G0">, DwarfRegNum<[0]> {
+  let isConstant = true;
+}
 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
(add C0_C1,   C2_C3,   C4_C5,   C6_C7,
          C16_C17, C18_C19, C20_C21, C22_C23,
          C24_C25, C26_C27, C28_C29, C30_C31)>;
 }
 
 // Privileged Registers
 def PRRegs : RegisterClass<"SP", [i64], 64,
     (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
          CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;
+

llvm/test/CodeGen/SPARC/64bit.ll

 }
 
 ; Immediate materialization. Many of these patterns could actually be merged
 ; into the restore instruction:
 ;
 ;     restore %g0, %g0, %o0
 ;
 ; CHECK: ret_imm0
-; CHECK: mov 0, %i0
+; CHECK: mov %g0, %i0
 
 ; OPT: ret_imm0
 ; OPT: retl
-; OPT: mov 0, %o0
+; OPT: mov %g0, %o0
 define i64 @ret_imm0() {
   ret i64 0
 }
 
 ; CHECK: ret_simm13
 ; CHECK: mov -4096, %i0
 
 ; OPT:   ret_simm13

llvm/test/CodeGen/SPARC/64cond.ll

 define i64 @select_consti64_xcc(i64 %x, i64 %y) {
 entry:
   %tobool = icmp sgt i64 %x, %y
   %rv = select i1 %tobool, i64 123, i64 0
   ret i64 %rv
 }
 
 ; CHECK-LABEL: setcc_resultty
-; CHECK-DAG:       mov 0, %o0
+; CHECK-DAG:       mov %g0, %o0
 ; CHECK-DAG:       mov %i0, %o1
-; CHECK-DAG:       mov %o0, %o2
+; CHECK-DAG:       mov %g0, %o2
 ; CHECK-DAG:       mov 32, %o3
 ; CHECK-DAG:       call __multi3
 ; CHECK:       movrnz %o0, 1, [[R:%[gilo][0-7]]]
 ; CHECK:       or [[R]], %i1, %i0
 
 define i1 @setcc_resultty(i64 %a, i1 %b) {
   %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
   %a1 = extractvalue { i64, i1 } %a0, 1
   %a4 = or i1 %a1, %b
   ret i1 %a4
 }
 
 declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)

llvm/test/CodeGen/SPARC/atomics.ll

 ; SPARC:       mov  255, %o3
 ; SPARC:       sll %o3, %o1, %o5
 ; SPARC:       xor %o5, -1, %o3
 ; SPARC:       mov  123, %o4
 ; SPARC:       ld [%o2], %g2
 ; SPARC:       sll %o4, %o1, %o4
 ; SPARC:       and %o0, 255, %o0
 ; SPARC:       sll %o0, %o1, %o0
-; SPARC:       andn %g2, %o5, %g2
-; SPARC:       mov %g0, %o5
+; SPARC:       andn %g2, %o5, %o5
 ; SPARC:      [[LABEL1:\.L.*]]:
-; SPARC:       or %g2, %o4, %g3
-; SPARC:       or %g2, %o0, %g4
-; SPARC:       cas [%o2], %g4, %g3
-; SPARC:       cmp %g3, %g4
-; SPARC:       mov  %o5, %g4
+; SPARC:       or %o5, %o4, %g2
+; SPARC:       or %o5, %o0, %g3
+; SPARC:       cas [%o2], %g3, %g2
+; SPARC:       mov %g0, %g4
+; SPARC:       cmp %g2, %g3
 ; SPARC:       move %icc, 1, %g4
 ; SPARC:       cmp %g4, 0
 ; SPARC:       bne %icc, [[LABEL2:\.L.*]]
 ; SPARC:       nop
-; SPARC:       and %g3, %o3, %g4
-; SPARC:       cmp %g2, %g4
+; SPARC:       and %g2, %o3, %g3
+; SPARC:       cmp %o5, %g3
 ; SPARC:       bne %icc, [[LABEL1]]
-; SPARC:       mov  %g4, %g2
+; SPARC:       mov  %g3, %o5
 ; SPARC:      [[LABEL2]]:
 ; SPARC:       retl
-; SPARC:       srl %g3, %o1, %o0
+; SPARC:       srl %g2, %o1, %o0
 ; SPARC64-LABEL: test_cmpxchg_i8
 ; SPARC64:       and %o1, -4, %o2
 ; SPARC64:       mov  3, %o3
 ; SPARC64:       andn %o3, %o1, %o1
 ; SPARC64:       sll %o1, 3, %o1
 ; SPARC64:       mov  255, %o3
 ; SPARC64:       sll %o3, %o1, %o5
 ; SPARC64:       xor %o5, -1, %o3
 ; SPARC64:       mov  123, %o4
 ; SPARC64:       ld [%o2], %g2
 ; SPARC64:       sll %o4, %o1, %o4
 ; SPARC64:       and %o0, 255, %o0
 ; SPARC64:       sll %o0, %o1, %o0
-; SPARC64:       andn %g2, %o5, %g2
-; SPARC64:       mov %g0, %o5
+; SPARC64:       andn %g2, %o5, %o5
 ; SPARC64:      [[LABEL1:\.L.*]]:
-; SPARC64:       or %g2, %o4, %g3
-; SPARC64:       or %g2, %o0, %g4
-; SPARC64:       cas [%o2], %g4, %g3
-; SPARC64:       cmp %g3, %g4
-; SPARC64:       mov  %o5, %g4
+; SPARC64:       or %o5, %o4, %g2
+; SPARC64:       or %o5, %o0, %g3
+; SPARC64:       cas [%o2], %g3, %g2
+; SPARC64:       mov %g0, %g4
+; SPARC64:       cmp %g2, %g3
 ; SPARC64:       move %icc, 1, %g4
 ; SPARC64:       cmp %g4, 0
 ; SPARC64:       bne %icc, [[LABEL2:\.L.*]]
 ; SPARC64:       nop
-; SPARC64:       and %g3, %o3, %g4
-; SPARC64:       cmp %g2, %g4
+; SPARC64:       and %g2, %o3, %g3
+; SPARC64:       cmp %o5, %g3
 ; SPARC64:       bne %icc, [[LABEL1]]
-; SPARC64:       mov  %g4, %g2
+; SPARC64:       mov  %g3, %o5
 ; SPARC64:      [[LABEL2]]:
 ; SPARC64:       retl
-; SPARC64:       srl %g3, %o1, %o0
+; SPARC64:       srl %g2, %o1, %o0
 define i8 @test_cmpxchg_i8(i8 %a, i8* %ptr) {
 entry:
   %pair = cmpxchg i8* %ptr, i8 %a, i8 123 monotonic monotonic
   %b = extractvalue { i8, i1 } %pair, 0
   ret i8 %b
 }
 
 ; SPARC-LABEL: test_cmpxchg_i16
 
 ; SPARC:       and %o1, -4, %o2
 ; SPARC:       and %o1, 3, %o1
 ; SPARC:       xor %o1, 2, %o1
 ; SPARC:       sll %o1, 3, %o1
 ; SPARC:       sethi 63, %o3
 ; SPARC:       or %o3, 1023, %o4
 ; SPARC:       sll %o4, %o1, %o5
 ; SPARC:       xor %o5, -1, %o3
 ; SPARC:       and %o0, %o4, %o4
 ; SPARC:       ld [%o2], %g2
 ; SPARC:       mov  123, %o0
 ; SPARC:       sll %o0, %o1, %o0
 ; SPARC:       sll %o4, %o1, %o4
-; SPARC:       andn %g2, %o5, %g2
-; SPARC:       mov %g0, %o5
+; SPARC:       andn %g2, %o5, %o5
 ; SPARC:      [[LABEL1:\.L.*]]:
-; SPARC:       or %g2, %o0, %g3
-; SPARC:       or %g2, %o4, %g4
-; SPARC:       cas [%o2], %g4, %g3
-; SPARC:       cmp %g3, %g4
-; SPARC:       mov  %o5, %g4
+; SPARC:       or %o5, %o0, %g2
+; SPARC:       or %o5, %o4, %g3
+; SPARC:       cas [%o2], %g3, %g2
+; SPARC:       mov %g0, %g4
+; SPARC:       cmp %g2, %g3
 ; SPARC:       move %icc, 1, %g4
 ; SPARC:       cmp %g4, 0
 ; SPARC:       bne %icc, [[LABEL2:\.L.*]]
 ; SPARC:       nop
-; SPARC:       and %g3, %o3, %g4
-; SPARC:       cmp %g2, %g4
+; SPARC:       and %g2, %o3, %g3
+; SPARC:       cmp %o5, %g3
 ; SPARC:       bne %icc, [[LABEL1]]
-; SPARC:       mov  %g4, %g2
+; SPARC:       mov  %g3, %o5
 ; SPARC:      [[LABEL2]]:
 ; SPARC:       retl
-; SPARC:       srl %g3, %o1, %o0
+; SPARC:       srl %g2, %o1, %o0
 ; SPARC64:       and %o1, -4, %o2
 ; SPARC64:       and %o1, 3, %o1
 ; SPARC64:       xor %o1, 2, %o1
 ; SPARC64:       sll %o1, 3, %o1
 ; SPARC64:       sethi 63, %o3
 ; SPARC64:       or %o3, 1023, %o4
 ; SPARC64:       sll %o4, %o1, %o5
 ; SPARC64:       xor %o5, -1, %o3
 ; SPARC64:       and %o0, %o4, %o4
 ; SPARC64:       ld [%o2], %g2
 ; SPARC64:       mov  123, %o0
 ; SPARC64:       sll %o0, %o1, %o0
 ; SPARC64:       sll %o4, %o1, %o4
-; SPARC64:       andn %g2, %o5, %g2
-; SPARC64:       mov %g0, %o5
+; SPARC64:       andn %g2, %o5, %o5
 ; SPARC64:      [[LABEL1:\.L.*]]:
-; SPARC64:       or %g2, %o0, %g3
-; SPARC64:       or %g2, %o4, %g4
-; SPARC64:       cas [%o2], %g4, %g3
-; SPARC64:       cmp %g3, %g4
-; SPARC64:       mov  %o5, %g4
+; SPARC64:       or %o5, %o0, %g2
+; SPARC64:       or %o5, %o4, %g3
+; SPARC64:       cas [%o2], %g3, %g2
+; SPARC64:       mov %g0, %g4
+; SPARC64:       cmp %g2, %g3
 ; SPARC64:       move %icc, 1, %g4
 ; SPARC64:       cmp %g4, 0
 ; SPARC64:       bne %icc, [[LABEL2:\.L.*]]
 ; SPARC64:       nop
-; SPARC64:       and %g3, %o3, %g4
-; SPARC64:       cmp %g2, %g4
+; SPARC64:       and %g2, %o3, %g3
+; SPARC64:       cmp %o5, %g3
 ; SPARC64:       bne %icc, [[LABEL1]]
-; SPARC64:       mov  %g4, %g2
+; SPARC64:       mov  %g3, %o5
 ; SPARC64:      [[LABEL2]]:
 ; SPARC64:       retl
-; SPARC64:       srl %g3, %o1, %o0
+; SPARC64:       srl %g2, %o1, %o0
 define i16 @test_cmpxchg_i16(i16 %a, i16* %ptr) {
 entry:
   %pair = cmpxchg i16* %ptr, i16 %a, i16 123 monotonic monotonic
   %b = extractvalue { i16, i1 } %pair, 0
   ret i16 %b
 }
 
 ; SPARC-LABEL: test_cmpxchg_i32

 define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
 entry:
   %0 = atomicrmw sub i16* %p, i16 %v seq_cst
   ret i16 %0
 }
 
 ; SPARC-LABEL: test_load_add_i32
 ; SPARC: membar
-; SPARC: mov %g0
 ; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
 ; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
 ; SPARC: cas [%o0], [[V]], [[V2]]
 ; SPARC: membar
 ; SPARC64-LABEL: test_load_add_i32
 ; SPARC64: membar
-; SPARC64: mov %g0
 ; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
 ; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
 ; SPARC64: cas [%o0], [[V]], [[V2]]
 ; SPARC64: membar
 define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
 entry:
   %0 = atomicrmw add i32* %p, i32 %v seq_cst
   ret i32 %0

llvm/test/CodeGen/SPARC/bigreturn.ll

 ; SPARC-LABEL: ret_i64_pair:
 ; SPARC:         .cfi_startproc
 ; SPARC-NEXT:  ! %bb.0:
 ; SPARC-NEXT:    save %sp, -96, %sp
 ; SPARC-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC-NEXT:    .cfi_window_save
 ; SPARC-NEXT:    .cfi_register %o7, %i7
 ; SPARC-NEXT:    mov %g0, %i4
 ; SPARC-NEXT:    ldd [%i2], %i0
-; SPARC-NEXT:    mov %i4, %i5
+; SPARC-NEXT:    mov %g0, %i5
 ; SPARC-NEXT:    std %i4, [%i2]
 ; SPARC-NEXT:    ldd [%i3], %i2
 ; SPARC-NEXT:    restore
 ; SPARC-NEXT:    retl
 ; SPARC-NEXT:    nop
 ;
 ; SPARC64-LABEL: ret_i64_pair:
 ; SPARC64:         .cfi_startproc

llvm/test/CodeGen/SPARC/cttz.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s
 
 define i32 @f(i32 %x) {
 ; CHECK-LABEL: f:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
-; CHECK-NEXT:    mov %g0, %o1
-; CHECK-NEXT:    sub %o1, %o0, %o1
+; CHECK-NEXT:    sub %g0, %o0, %o1
 ; CHECK-NEXT:    and %o0, %o1, %o1
 ; CHECK-NEXT:    sethi 122669, %o2
 ; CHECK-NEXT:    or %o2, 305, %o2
 ; CHECK-NEXT:    smul %o1, %o2, %o1
 ; CHECK-NEXT:    srl %o1, 27, %o1
 ; CHECK-NEXT:    sethi %hi(.LCPI0_0), %o2
 ; CHECK-NEXT:    add %o2, %lo(.LCPI0_0), %o2
 ; CHECK-NEXT:    ldub [%o2+%o1], %o1
entry:
   %conv = zext i8 %3 to i32
   ret i32 %conv
 }
 
 define i64 @g(i64 %x) {
 ; CHECK-LABEL: g:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
-; CHECK-NEXT:    mov %g0, %o2
-; CHECK-NEXT:    sub %o2, %o1, %o3
-; CHECK-NEXT:    and %o1, %o3, %o3
-; CHECK-NEXT:    sethi 122669, %o4
-; CHECK-NEXT:    or %o4, 305, %o4
-; CHECK-NEXT:    smul %o3, %o4, %o3
-; CHECK-NEXT:    sethi %hi(.LCPI1_0), %o5
-; CHECK-NEXT:    add %o5, %lo(.LCPI1_0), %o5
-; CHECK-NEXT:    sub %o2, %o0, %g2
-; CHECK-NEXT:    and %o0, %g2, %g2
-; CHECK-NEXT:    smul %g2, %o4, %o4
-; CHECK-NEXT:    srl %o4, 27, %o4
-; CHECK-NEXT:    ldub [%o5+%o4], %o4
+; CHECK-NEXT:    sub %g0, %o1, %o2
+; CHECK-NEXT:    and %o1, %o2, %o2
+; CHECK-NEXT:    sethi 122669, %o3
+; CHECK-NEXT:    or %o3, 305, %o3
+; CHECK-NEXT:    smul %o2, %o3, %o2
+; CHECK-NEXT:    sethi %hi(.LCPI1_0), %o4
+; CHECK-NEXT:    add %o4, %lo(.LCPI1_0), %o4
+; CHECK-NEXT:    sub %g0, %o0, %o5
+; CHECK-NEXT:    and %o0, %o5, %o5
+; CHECK-NEXT:    smul %o5, %o3, %o3
 ; CHECK-NEXT:    srl %o3, 27, %o3
-; CHECK-NEXT:    ldub [%o5+%o3], %o5
-; CHECK-NEXT:    add %o4, 32, %o3
+; CHECK-NEXT:    ldub [%o4+%o3], %o3
+; CHECK-NEXT:    srl %o2, 27, %o2
+; CHECK-NEXT:    ldub [%o4+%o2], %o4
+; CHECK-NEXT:    add %o3, 32, %o2
 ; CHECK-NEXT:    cmp %o1, 0
-; CHECK-NEXT:    movne %icc, %o5, %o3
+; CHECK-NEXT:    movne %icc, %o4, %o2
 ; CHECK-NEXT:    or %o1, %o0, %o0
 ; CHECK-NEXT:    cmp %o0, 0
-; CHECK-NEXT:    move %icc, 0, %o3
-; CHECK-NEXT:    mov %o2, %o0
+; CHECK-NEXT:    move %icc, 0, %o2
+; CHECK-NEXT:    mov %g0, %o0
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    mov %o3, %o1
+; CHECK-NEXT:    mov %o2, %o1
 entry:
   %0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
   %1 = icmp eq i64 %x, 0
   %2 = select i1 %1, i64 0, i64 %0
   %3 = trunc i64 %2 to i32
   %conv = zext i32 %3 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
 declare i32 @llvm.cttz.i32(i32, i1 immarg) #0
 declare i64 @llvm.cttz.i64(i64, i1 immarg) #0
 
 attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }

llvm/test/CodeGen/SPARC/float-constants.ll

 }
 
 ;; Same thing for a call using a double (which gets passed in integer
 ;; registers)
 
 ; CHECK-LABEL: test_call
 ; CHECK: sethi 1049856, %o0
 ; CHECK: mov %g0, %o1
-; CHECK-LE: mov %g0, %o0
 ; CHECK-LE: sethi 1049856, %o1
+; CHECK-LE: mov %g0, %o0
 declare void @a(double)
 define void @test_call() {
   call void @a(double 5.0)
   ret void
 }
 
 ;; And for a libcall emitted from the pow intrinsic.  (libcall
 ;; emission happens after SelectionDAG type legalization, so is a bit
 ;; different than a normal function call. This was crashing before,
 ;; due to an earlier broken workaround for this issue.)
 
 ; CHECK-LABEL: test_intrins_call
 ; CHECK: sethi 1048576, %o0
 ; CHECK: mov %g0, %o1
 ; CHECK: mov %o0, %o2
-; CHECK: mov %o1, %o3
-; CHECK-LE: mov %g0, %o0
+; CHECK: mov %g0, %o3
 ; CHECK-LE: sethi 1048576, %o1
+; CHECK-LE: mov %g0, %o0
 declare double @llvm.pow.f64(double, double)
 define double @test_intrins_call() {
   %1 = call double @llvm.pow.f64(double 2.0, double 2.0)
   ret double %1
 }

llvm/test/CodeGen/SPARC/fshl.ll

bb:
   ret <2 x i64> %i
 }
 
 define i32 @PR47303() {
 ; CHECK-LABEL: PR47303:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %bb
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:    mov 0, %o0
+; CHECK-NEXT:    mov %g0, %o0
 bb:
   %i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
   %i1 = add <4 x i64> %i, zeroinitializer
   %i2 = add <4 x i64> %i1, zeroinitializer
   %i3 = extractelement <4 x i64> %i2, i32 0
   %i4 = add i64 0, %i3
   %i5 = xor i64 0, %i4
   %i6 = trunc i64 %i5 to i32
   %i7 = mul i32 %i6, 797982799
   ret i32 %i7
 }
 
 declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)

llvm/test/CodeGen/SPARC/inlineasm.ll

entry:
   %conv = sext i32 %foo to i64
   tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
   ret i32 %o
 }
 attributes #0 = { "frame-pointer"="all" }
 
 ;; Ensures that tied in and out gets allocated properly.
 ; CHECK-LABEL: test_i64_inout:
-; CHECK: mov %g0, %i2
 ; CHECK: mov 5, %i3
+; CHECK: mov %g0, %i2
 ; CHECK: xor %i2, %g0, %i2
 ; CHECK: mov %i2, %i0
 ; CHECK: ret
 define i64 @test_i64_inout() {
 entry:
   %0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
   ret i64 %0
 }

llvm/test/CodeGen/SPARC/missinglabel.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs | FileCheck %s
 
 target datalayout = "E-m:e-i64:64-n32:64-S128"
 target triple = "sparc64-unknown-linux-gnu"
 
 define void @f(i64 %a0) align 2 {
 ; CHECK-LABEL: f:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
 ; CHECK-NEXT:    cmp %o0, 0
 ; CHECK-NEXT:    be %xcc, .LBB0_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.1: ! %cond.false
 ; CHECK-NEXT:  .LBB0_2: ! %targetblock
-; CHECK-NEXT:    mov %g0, %o0
-; CHECK-NEXT:    cmp %o0, 0
+; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    bne %icc, .LBB0_4
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.3: ! %cond.false.i83
 ; CHECK-NEXT:  .LBB0_4: ! %exit.i85
 entry:
   %cmp = icmp eq i64 %a0, 0
   br i1 %cmp, label %targetblock, label %cond.false
 

llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
 ; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC-LABEL: muloti_test:
 ; SPARC:         .cfi_startproc
 ; SPARC-NEXT:  ! %bb.0: ! %start
 ; SPARC-NEXT:    save %sp, -136, %sp
 ; SPARC-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC-NEXT:    .cfi_window_save
 ; SPARC-NEXT:    .cfi_register %o7, %i7
-; SPARC-NEXT:    ld [%fp+92], %l2
-; SPARC-NEXT:    ld [%fp+96], %l3
-; SPARC-NEXT:    mov %i3, %l7
-; SPARC-NEXT:    mov %i2, %l5
-; SPARC-NEXT:    mov %i1, %l4
-; SPARC-NEXT:    mov %i0, %l6
+; SPARC-NEXT:    ld [%fp+92], %l1
+; SPARC-NEXT:    ld [%fp+96], %l2
+; SPARC-NEXT:    mov %i3, %l6
+; SPARC-NEXT:    mov %i2, %l4
+; SPARC-NEXT:    mov %i1, %i3
+; SPARC-NEXT:    mov %i0, %l3
 ; SPARC-NEXT:    sra %i0, 31, %o4
 ; SPARC-NEXT:    st %o4, [%sp+96]
 ; SPARC-NEXT:    st %o4, [%sp+92]
 ; SPARC-NEXT:    mov %i4, %o0
 ; SPARC-NEXT:    mov %i5, %o1
-; SPARC-NEXT:    mov %l2, %o2
-; SPARC-NEXT:    mov %l3, %o3
+; SPARC-NEXT:    mov %l1, %o2
+; SPARC-NEXT:    mov %l2, %o3
 ; SPARC-NEXT:    call __multi3
 ; SPARC-NEXT:    mov %o4, %o5
 ; SPARC-NEXT:    st %o0, [%fp+-12] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %o1, [%fp+-16] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %o2, [%fp+-20] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %o3, [%fp+-24] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %i5, [%sp+96]
-; SPARC-NEXT:    mov %g0, %l0
 ; SPARC-NEXT:    st %i4, [%sp+92]
-; SPARC-NEXT:    mov %l0, %o0
-; SPARC-NEXT:    mov %l0, %o1
+; SPARC-NEXT:    mov %g0, %o0
+; SPARC-NEXT:    mov %g0, %o1
 ; SPARC-NEXT:    mov %i2, %o2
-; SPARC-NEXT:    mov %i3, %o3
-; SPARC-NEXT:    mov %l0, %o4
+; SPARC-NEXT:    mov %l6, %o3
+; SPARC-NEXT:    mov %g0, %o4
 ; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l0, %o5
+; SPARC-NEXT:    mov %g0, %o5
 ; SPARC-NEXT:    st %o0, [%fp+-28] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %o1, [%fp+-32] ! 4-byte Folded Spill
-; SPARC-NEXT:    st %o2, [%fp+-36] ! 4-byte Folded Spill
-; SPARC-NEXT:    mov %o3, %i3
-; SPARC-NEXT:    st %l3, [%sp+96]
-; SPARC-NEXT:    st %l2, [%sp+92]
-; SPARC-NEXT:    mov %l0, %o0
-; SPARC-NEXT:    mov %l0, %o1
-; SPARC-NEXT:    mov %i2, %o2
-; SPARC-NEXT:    mov %l7, %o3
-; SPARC-NEXT:    mov %l0, %o4
-; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l0, %o5
-; SPARC-NEXT:    mov %o0, %i0
-; SPARC-NEXT:    mov %o1, %i1
+; SPARC-NEXT:    mov %o2, %l0
+; SPARC-NEXT:    mov %o3, %i2
+; SPARC-NEXT:    st %l2, [%sp+96]
+; SPARC-NEXT:    st %l1, [%sp+92]
+; SPARC-NEXT:    mov %g0, %o0
+; SPARC-NEXT:    mov %g0, %o1
+; SPARC-NEXT:    mov %l4, %o2
+; SPARC-NEXT:    mov %l6, %o3
+; SPARC-NEXT:    mov %g0, %o4
+; SPARC-NEXT:    call __multi3
+; SPARC-NEXT:    mov %g0, %o5
+; SPARC-NEXT:    mov %o0, %i1
+; SPARC-NEXT:    mov %o1, %i0
 ; SPARC-NEXT:    st %o2, [%fp+-4] ! 4-byte Folded Spill
 ; SPARC-NEXT:    st %o3, [%fp+-8] ! 4-byte Folded Spill
-; SPARC-NEXT:    st %l3, [%sp+96]
-; SPARC-NEXT:    st %l2, [%sp+92]
-; SPARC-NEXT:    mov %l0, %o0
-; SPARC-NEXT:    mov %l0, %o1
-; SPARC-NEXT:    mov %l6, %o2
-; SPARC-NEXT:    mov %l4, %o3
-; SPARC-NEXT:    mov %l0, %o4
+; SPARC-NEXT:    st %l2, [%sp+96]
+; SPARC-NEXT:    st %l1, [%sp+92]
+; SPARC-NEXT:    mov %g0, %o0
+; SPARC-NEXT:    mov %g0, %o1
+; SPARC-NEXT:    mov %l3, %o2
+; SPARC-NEXT:    mov %i3, %o3
+; SPARC-NEXT:    mov %g0, %o4
 ; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l0, %o5
-; SPARC-NEXT:    mov %o0, %l2
-; SPARC-NEXT:    mov %o1, %l3
-; SPARC-NEXT:    mov %o2, %l1
-; SPARC-NEXT:    mov %o3, %i2
-; SPARC-NEXT:    st %l7, [%sp+96]
+; SPARC-NEXT:    mov %g0, %o5
+; SPARC-NEXT:    mov %o0, %l1
+; SPARC-NEXT:    mov %o1, %l2
+; SPARC-NEXT:    mov %o2, %l5
+; SPARC-NEXT:    mov %o3, %l7
+; SPARC-NEXT:    st %l6, [%sp+96]
 ; SPARC-NEXT:    sra %i4, 31, %o0
-; SPARC-NEXT:    st %l5, [%sp+92]
+; SPARC-NEXT:    st %l4, [%sp+92]
 ; SPARC-NEXT:    mov %o0, %o1
 ; SPARC-NEXT:    mov %o0, %o2
 ; SPARC-NEXT:    mov %o0, %o3
-; SPARC-NEXT:    mov %l6, %o4
+; SPARC-NEXT:    mov %l3, %o4
 ; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l4, %o5
+; SPARC-NEXT:    mov %i3, %o5
 ; SPARC-NEXT:    st %i5, [%sp+96]
 ; SPARC-NEXT:    st %i4, [%sp+92]
 ; SPARC-NEXT:    ld [%fp+-24], %i4 ! 4-byte Folded Reload
 ; SPARC-NEXT:    addcc %o3, %i4, %i4
 ; SPARC-NEXT:    ld [%fp+-20], %i5 ! 4-byte Folded Reload
 ; SPARC-NEXT:    addxcc %o2, %i5, %i5
 ; SPARC-NEXT:    ld [%fp+-16], %g2 ! 4-byte Folded Reload
-; SPARC-NEXT:    addxcc %o1, %g2, %l5
+; SPARC-NEXT:    addxcc %o1, %g2, %l4
 ; SPARC-NEXT:    ld [%fp+-12], %g2 ! 4-byte Folded Reload
-; SPARC-NEXT:    addxcc %o0, %g2, %l7
-; SPARC-NEXT:    addcc %i2, %i1, %i1
-; SPARC-NEXT:    addxcc %l1, %i0, %i0
-; SPARC-NEXT:    addxcc %l3, 0, %i2
-; SPARC-NEXT:    addxcc %l2, 0, %g2
-; SPARC-NEXT:    addcc %i3, %i1, %i1
-; SPARC-NEXT:    ld [%fp+-36], %i3 ! 4-byte Folded Reload
-; SPARC-NEXT:    addxcc %i3, %i0, %i0
-; SPARC-NEXT:    ld [%fp+-32], %i3 ! 4-byte Folded Reload
-; SPARC-NEXT:    addxcc %i3, 0, %i3
-; SPARC-NEXT:    ld [%fp+-28], %g3 ! 4-byte Folded Reload
-; SPARC-NEXT:    addxcc %g3, 0, %g3
-; SPARC-NEXT:    addcc %i2, %i3, %i2
-; SPARC-NEXT:    addxcc %g2, %g3, %i3
-; SPARC-NEXT:    addxcc %l0, 0, %l1
-; SPARC-NEXT:    addxcc %l0, 0, %l2
-; SPARC-NEXT:    mov %l0, %o0
-; SPARC-NEXT:    mov %l0, %o1
-; SPARC-NEXT:    mov %l6, %o2
-; SPARC-NEXT:    mov %l4, %o3
-; SPARC-NEXT:    mov %l0, %o4
+; SPARC-NEXT:    addxcc %o0, %g2, %l6
+; SPARC-NEXT:    addcc %l7, %i0, %i0
+; SPARC-NEXT:    addxcc %l5, %i1, %g2
+; SPARC-NEXT:    addxcc %l2, 0, %g3
+; SPARC-NEXT:    addxcc %l1, 0, %g4
+; SPARC-NEXT:    addcc %i2, %i0, %i1
+; SPARC-NEXT:    addxcc %l0, %g2, %i0
+; SPARC-NEXT:    ld [%fp+-32], %i2 ! 4-byte Folded Reload
+; SPARC-NEXT:    addxcc %i2, 0, %i2
+; SPARC-NEXT:    ld [%fp+-28], %g2 ! 4-byte Folded Reload
+; SPARC-NEXT:    addxcc %g2, 0, %g2
+; SPARC-NEXT:    addcc %g3, %i2, %i2
+; SPARC-NEXT:    addxcc %g4, %g2, %l0
+; SPARC-NEXT:    addxcc %g0, 0, %l1
+; SPARC-NEXT:    addxcc %g0, 0, %l2
+; SPARC-NEXT:    mov %g0, %o0
+; SPARC-NEXT:    mov %g0, %o1
+; SPARC-NEXT:    mov %l3, %o2
+; SPARC-NEXT:    mov %i3, %o3
+; SPARC-NEXT:    mov %g0, %o4
 ; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l0, %o5
+; SPARC-NEXT:    mov %g0, %o5
 ; SPARC-NEXT:    addcc %o3, %i2, %i2
-; SPARC-NEXT:    addxcc %o2, %i3, %i3
+; SPARC-NEXT:    addxcc %o2, %l0, %i3
 ; SPARC-NEXT:    addxcc %o1, %l1, %g2
 ; SPARC-NEXT:    addxcc %o0, %l2, %g3
 ; SPARC-NEXT:    addcc %i2, %i4, %i2
 ; SPARC-NEXT:    addxcc %i3, %i5, %i3
-; SPARC-NEXT:    addxcc %g2, %l5, %i4
-; SPARC-NEXT:    addxcc %g3, %l7, %i5
+; SPARC-NEXT:    addxcc %g2, %l4, %i4
+; SPARC-NEXT:    addxcc %g3, %l6, %i5
 ; SPARC-NEXT:    sra %i0, 31, %g2
 ; SPARC-NEXT:    xor %i5, %g2, %i5
 ; SPARC-NEXT:    xor %i3, %g2, %i3
 ; SPARC-NEXT:    or %i3, %i5, %i3
 ; SPARC-NEXT:    xor %i4, %g2, %i4
 ; SPARC-NEXT:    xor %i2, %g2, %i2
 ; SPARC-NEXT:    or %i2, %i4, %i2
 ; SPARC-NEXT:    or %i2, %i3, %i2
 ; SPARC-NEXT:    cmp %i2, 0
-; SPARC-NEXT:    be .LBB0_2
+; SPARC-NEXT:    bne .LBB0_1
 ; SPARC-NEXT:    nop
-; SPARC-NEXT:  ! %bb.1:
-; SPARC-NEXT:    mov 1, %l0
-; SPARC-NEXT:  .LBB0_2: ! %start
+; SPARC-NEXT:  ! %bb.2: ! %start
+; SPARC-NEXT:    ba .LBB0_3
+; SPARC-NEXT:    mov %g0, %i4
+; SPARC-NEXT:  .LBB0_1:
+; SPARC-NEXT:    mov 1, %i4
+; SPARC-NEXT:  .LBB0_3: ! %start
 ; SPARC-NEXT:    ld [%fp+-4], %i2 ! 4-byte Folded Reload
 ; SPARC-NEXT:    ld [%fp+-8], %i3 ! 4-byte Folded Reload
 ; SPARC-NEXT:    ret
-; SPARC-NEXT:    restore %g0, %l0, %o4
+; SPARC-NEXT:    restore
 ;
 ; SPARC64-LABEL: muloti_test:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:    .register %g2, #scratch
 ; SPARC64-NEXT:    .register %g3, #scratch
 ; SPARC64-NEXT:  ! %bb.0: ! %start
-; SPARC64-NEXT:    save %sp, -192, %sp
+; SPARC64-NEXT:    save %sp, -176, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
 ; SPARC64-NEXT:    .cfi_register %o7, %i7
 ; SPARC64-NEXT:    mov %i3, %i4
 ; SPARC64-NEXT:    mov %i1, %i3
 ; SPARC64-NEXT:    srax %i0, 63, %o2
 ; SPARC64-NEXT:    mov %i2, %o0
 ; SPARC64-NEXT:    mov %i4, %o1
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %o2, %o3
 ; SPARC64-NEXT:    mov %o0, %i1
 ; SPARC64-NEXT:    mov %o1, %i5
 ; SPARC64-NEXT:    srax %i2, 63, %o0
 ; SPARC64-NEXT:    mov %o0, %o1
 ; SPARC64-NEXT:    mov %i0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i3, %o3
 ; SPARC64-NEXT:    srlx %i5, 32, %g2
 ; SPARC64-NEXT:    srlx %o1, 32, %g3
 ; SPARC64-NEXT:    srlx %i1, 32, %g4
 ; SPARC64-NEXT:    srlx %o0, 32, %g5
-; SPARC64-NEXT:    addcc %o1, %i5, %i5
-; SPARC64-NEXT:    st %i5, [%fp+2043] ! 4-byte Folded Spill
-; SPARC64-NEXT:    addxcc %g3, %g2, %l2
-; SPARC64-NEXT:    addxcc %o0, %i1, %l3
-; SPARC64-NEXT:    addxcc %g5, %g4, %l4
-; SPARC64-NEXT:    mov 0, %i5
-; SPARC64-NEXT:    mov %i5, %o0
+; SPARC64-NEXT:    addcc %o1, %i5, %l0
+; SPARC64-NEXT:    addxcc %g3, %g2, %l1
+; SPARC64-NEXT:    addxcc %o0, %i1, %l2
+; SPARC64-NEXT:    addxcc %g5, %g4, %l3
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i3, %o1
-; SPARC64-NEXT:    mov %i5, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i4, %o3
-; SPARC64-NEXT:    mov %o0, %l0
+; SPARC64-NEXT:    mov %o0, %i5
 ; SPARC64-NEXT:    mov %o1, %i1
-; SPARC64-NEXT:    mov %i5, %o0
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i0, %o1
-; SPARC64-NEXT:    mov %i5, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i4, %o3
-; SPARC64-NEXT:    srlx %l0, 32, %i4
+; SPARC64-NEXT:    srlx %i5, 32, %i4
 ; SPARC64-NEXT:    srlx %o1, 32, %g2
 ; SPARC64-NEXT:    srlx %o0, 32, %g3
-; SPARC64-NEXT:    addcc %o1, %l0, %l0
+; SPARC64-NEXT:    addcc %o1, %i5, %i5
 ; SPARC64-NEXT:    addxcc %g2, %i4, %i4
-; SPARC64-NEXT:    addxcc %o0, 0, %l5
-; SPARC64-NEXT:    addxcc %g3, 0, %l6
-; SPARC64-NEXT:    mov %i5, %o0
+; SPARC64-NEXT:    addxcc %o0, 0, %l4
+; SPARC64-NEXT:    addxcc %g3, 0, %l5
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i3, %o1
-; SPARC64-NEXT:    mov %i5, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i2, %o3
 ; SPARC64-NEXT:    srlx %o1, 32, %i3
 ; SPARC64-NEXT:    srlx %o0, 32, %g2
-; SPARC64-NEXT:    addcc %o1, %l0, %l0
+; SPARC64-NEXT:    addcc %o1, %i5, %i5
 ; SPARC64-NEXT:    addxcc %i3, %i4, %i3
 ; SPARC64-NEXT:    addxcc %o0, 0, %i4
 ; SPARC64-NEXT:    addxcc %g2, 0, %g2
-; SPARC64-NEXT:    mov %g0, %l7
-; SPARC64-NEXT:    addcc %l5, %i4, %i4
-; SPARC64-NEXT:    addxcc %l6, %g2, %l5
-; SPARC64-NEXT:    addxcc %l7, 0, %l6
-; SPARC64-NEXT:    addxcc %l7, 0, %l1
-; SPARC64-NEXT:    mov %i5, %o0
+; SPARC64-NEXT:    addcc %l4, %i4, %i4
+; SPARC64-NEXT:    addxcc %l5, %g2, %l4
+; SPARC64-NEXT:    addxcc %g0, 0, %l5
+; SPARC64-NEXT:    addxcc %g0, 0, %l6
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i0, %o1
-; SPARC64-NEXT:    mov %i5, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i2, %o3
+; SPARC64-NEXT:    mov %g0, %i2
 ; SPARC64-NEXT:    srlx %o1, 32, %i0
-; SPARC64-NEXT:    srlx %o0, 32, %i2
 ; SPARC64-NEXT:    addcc %o1, %i4, %i4
-; SPARC64-NEXT:    addxcc %i0, %l5, %i0
-; SPARC64-NEXT:    addxcc %o0, %l6, %i5
-; SPARC64-NEXT:    addxcc %i2, %l1, %i2
-; SPARC64-NEXT:    ld [%fp+2043], %g2 ! 4-byte Folded Reload
-; SPARC64-NEXT:    addcc %i4, %g2, %i4
-; SPARC64-NEXT:    addxcc %i0, %l2, %i0
-; SPARC64-NEXT:    addxcc %i5, %l3, %i5
-; SPARC64-NEXT:    addxcc %i2, %l4, %i2
-; SPARC64-NEXT:    srl %i5, 0, %i5
-; SPARC64-NEXT:    sllx %i2, 32, %i2
-; SPARC64-NEXT:    or %i2, %i5, %i2
+; SPARC64-NEXT:    srlx %o0, 32, %g2
+; SPARC64-NEXT:    addxcc %i0, %l4, %i0
+; SPARC64-NEXT:    addxcc %o0, %l5, %g3
+; SPARC64-NEXT:    addxcc %g2, %l6, %g2
+; SPARC64-NEXT:    addcc %i4, %l0, %i4
+; SPARC64-NEXT:    addxcc %i0, %l1, %i0
+; SPARC64-NEXT:    addxcc %g3, %l2, %g3
+; SPARC64-NEXT:    addxcc %g2, %l3, %g2
+; SPARC64-NEXT:    srl %g3, 0, %g3
+; SPARC64-NEXT:    sllx %g2, 32, %g2
+; SPARC64-NEXT:    or %g2, %g3, %g2
 ; SPARC64-NEXT:    sllx %i3, 32, %i3
-; SPARC64-NEXT:    srax %i3, 63, %i5
-; SPARC64-NEXT:    xor %i2, %i5, %i2
+; SPARC64-NEXT:    srax %i3, 63, %g3
+; SPARC64-NEXT:    xor %g2, %g3, %g2
 ; SPARC64-NEXT:    srl %i4, 0, %i4
 ; SPARC64-NEXT:    sllx %i0, 32, %i0
 ; SPARC64-NEXT:    or %i0, %i4, %i0
-; SPARC64-NEXT:    xor %i0, %i5, %i0
-; SPARC64-NEXT:    or %i0, %i2, %i0
-; SPARC64-NEXT:    movrnz %i0, 1, %l7
-; SPARC64-NEXT:    srl %l0, 0, %i0
+; SPARC64-NEXT:    xor %i0, %g3, %i0
+; SPARC64-NEXT:    or %i0, %g2, %i0
+; SPARC64-NEXT:    movrnz %i0, 1, %i2
+; SPARC64-NEXT:    srl %i5, 0, %i0
 ; SPARC64-NEXT:    or %i3, %i0, %i0
-; SPARC64-NEXT:    srl %l7, 0, %i2
+; SPARC64-NEXT:    srl %i2, 0, %i2
 ; SPARC64-NEXT:    ret
 ; SPARC64-NEXT:    restore
 start:
   %0 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
   %4 = insertvalue { i128, i8 } undef, i128 %1, 0

llvm/test/CodeGen/SPARC/tailcall.ll

 
 ; Do not tail call optimize if stack is used to pass parameters.
 
 define i32 @caller_args() #0 {
 ; V8-LABEL: caller_args:
 ; V8:       ! %bb.0: ! %entry
 ; V8-NEXT:    save %sp, -104, %sp
 ; V8-NEXT:    mov 6, %i0
-; V8-NEXT:    mov %g0, %o0
 ; V8-NEXT:    mov 1, %o1
 ; V8-NEXT:    mov 2, %o2
 ; V8-NEXT:    mov 3, %o3
 ; V8-NEXT:    mov 4, %o4
 ; V8-NEXT:    mov 5, %o5
-; V8-NEXT:    call foo7
 ; V8-NEXT:    st %i0, [%sp+92]
+; V8-NEXT:    call foo7
+; V8-NEXT:    mov %g0, %o0
 ; V8-NEXT:    ret
 ; V8-NEXT:    restore %g0, %o0, %o0
 ;
 ; V9-LABEL: caller_args:
 ; V9:       ! %bb.0: ! %entry
 ; V9-NEXT:    save %sp, -192, %sp
 ; V9-NEXT:    mov 6, %i0
-; V9-NEXT:    mov 0, %o0
 ; V9-NEXT:    mov 1, %o1
 ; V9-NEXT:    mov 2, %o2
 ; V9-NEXT:    mov 3, %o3
 ; V9-NEXT:    mov 4, %o4
 ; V9-NEXT:    mov 5, %o5
-; V9-NEXT:    call foo7
 ; V9-NEXT:    stx %i0, [%sp+2223]
+; V9-NEXT:    call foo7
+; V9-NEXT:    mov %g0, %o0
 ; V9-NEXT:    ret
 ; V9-NEXT:    restore %g0, %o0, %o0
 entry:
   %r = tail call i32 @foo7(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
   ret i32 %r
 }
 
 ; Byval parameters hand the function a pointer directly into the stack area

llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
 ; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC-LABEL: muloti_test:
 ; SPARC:         .cfi_startproc
 ; SPARC-NEXT:  ! %bb.0: ! %start
-; SPARC-NEXT:    save %sp, -120, %sp
+; SPARC-NEXT:    save %sp, -112, %sp
 ; SPARC-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC-NEXT:    .cfi_window_save
 ; SPARC-NEXT:    .cfi_register %o7, %i7
 ; SPARC-NEXT:    ld [%fp+92], %l4
 ; SPARC-NEXT:    ld [%fp+96], %g2
 ; SPARC-NEXT:    umul %i2, %i5, %g3
 ; SPARC-NEXT:    rd %y, %g4
 ; SPARC-NEXT:    st %g4, [%fp+-12] ! 4-byte Folded Spill
 ; SPARC-NEXT:    umul %i4, %i3, %g4
-; SPARC-NEXT:    rd %y, %l0
-; SPARC-NEXT:    st %l0, [%fp+-16] ! 4-byte Folded Spill
+; SPARC-NEXT:    rd %y, %l5
 ; SPARC-NEXT:    st %g2, [%sp+96]
-; SPARC-NEXT:    umul %i5, %i3, %l0
+; SPARC-NEXT:    umul %i5, %i3, %l1
 ; SPARC-NEXT:    rd %y, %l6
 ; SPARC-NEXT:    st %l4, [%sp+92]
 ; SPARC-NEXT:    umul %l4, %i1, %l2
-; SPARC-NEXT:    rd %y, %l1
-; SPARC-NEXT:    st %l1, [%fp+-4] ! 4-byte Folded Spill
+; SPARC-NEXT:    rd %y, %l0
+; SPARC-NEXT:    st %l0, [%fp+-4] ! 4-byte Folded Spill
 ; SPARC-NEXT:    add %g4, %g3, %g3
 ; SPARC-NEXT:    umul %i0, %g2, %g4
-; SPARC-NEXT:    rd %y, %l1
-; SPARC-NEXT:    st %l1, [%fp+-8] ! 4-byte Folded Spill
+; SPARC-NEXT:    rd %y, %l0
+; SPARC-NEXT:    st %l0, [%fp+-8] ! 4-byte Folded Spill
 ; SPARC-NEXT:    add %l6, %g3, %l3
 ; SPARC-NEXT:    umul %i1, %g2, %g2
-; SPARC-NEXT:    rd %y, %l1
+; SPARC-NEXT:    rd %y, %l0
 ; SPARC-NEXT:    add %g4, %l2, %g3
-; SPARC-NEXT:    add %l1, %g3, %l2
-; SPARC-NEXT:    addcc %g2, %l0, %l7
-; SPARC-NEXT:    mov %g0, %l0
-; SPARC-NEXT:    addxcc %l2, %l3, %l5
-; SPARC-NEXT:    mov %l0, %o0
-; SPARC-NEXT:    mov %l0, %o1
+; SPARC-NEXT:    add %l0, %g3, %l2
+; SPARC-NEXT:    addcc %g2, %l1, %l1
+; SPARC-NEXT:    addxcc %l2, %l3, %l7
+; SPARC-NEXT:    mov %g0, %o0
+; SPARC-NEXT:    mov %g0, %o1
 ; SPARC-NEXT:    mov %i2, %o2
 ; SPARC-NEXT:    mov %i3, %o3
-; SPARC-NEXT:    mov %l0, %o4
+; SPARC-NEXT:    mov %g0, %o4
 ; SPARC-NEXT:    call __multi3
-; SPARC-NEXT:    mov %l0, %o5
-; SPARC-NEXT:    addcc %o1, %l7, %i3
-; SPARC-NEXT:    addxcc %o0, %l5, %g2
-; SPARC-NEXT:    mov 1, %g3
+; SPARC-NEXT:    mov %g0, %o5
+; SPARC-NEXT:    addcc %o1, %l1, %g3
+; SPARC-NEXT:    addxcc %o0, %l7, %g2
+; SPARC-NEXT:    mov 1, %g4
 ; SPARC-NEXT:    cmp %g2, %o0
+; SPARC-NEXT:    mov %o3, %i3
 ; SPARC-NEXT:    bcs .LBB0_2
-; SPARC-NEXT:    mov %g3, %o4
+; SPARC-NEXT:    mov %g4, %o3
 ; SPARC-NEXT:  ! %bb.1: ! %start
-; SPARC-NEXT:    mov %l0, %o4
+; SPARC-NEXT:    mov %g0, %o3
 ; SPARC-NEXT:  .LBB0_2: ! %start
-; SPARC-NEXT:    cmp %i3, %o1
+; SPARC-NEXT:    cmp %g3, %o1
 ; SPARC-NEXT:    bcs .LBB0_4
-; SPARC-NEXT:    mov %g3, %g4
+; SPARC-NEXT:    mov %g4, %l1
 ; SPARC-NEXT:  ! %bb.3: ! %start
-; SPARC-NEXT:    mov %l0, %g4
+; SPARC-NEXT:    mov %g0, %l1
 ; SPARC-NEXT:  .LBB0_4: ! %start
 ; SPARC-NEXT:    cmp %g2, %o0
 ; SPARC-NEXT:    be .LBB0_6
 ; SPARC-NEXT:    nop
 ; SPARC-NEXT:  ! %bb.5: ! %start
-; SPARC-NEXT:    mov %o4, %g4
+; SPARC-NEXT:    mov %o3, %l1
 ; SPARC-NEXT:  .LBB0_6: ! %start
 ; SPARC-NEXT:    cmp %i2, 0
 ; SPARC-NEXT:    bne .LBB0_8
-; SPARC-NEXT:    mov %g3, %i2
+; SPARC-NEXT:    mov %g4, %i2
 ; SPARC-NEXT:  ! %bb.7: ! %start
-; SPARC-NEXT:    mov %l0, %i2
+; SPARC-NEXT:    mov %g0, %i2
 ; SPARC-NEXT:  .LBB0_8: ! %start
 ; SPARC-NEXT:    cmp %i4, 0
 ; SPARC-NEXT:    bne .LBB0_10
-; SPARC-NEXT:    mov %g3, %o1
+; SPARC-NEXT:    mov %g4, %o1
 ; SPARC-NEXT:  ! %bb.9: ! %start
-; SPARC-NEXT:    mov %l0, %o1
+; SPARC-NEXT:    mov %g0, %o1
 ; SPARC-NEXT:  .LBB0_10: ! %start
-; SPARC-NEXT:    ld [%fp+-16], %l5 ! 4-byte Folded Reload
 ; SPARC-NEXT:    cmp %l5, 0
 ; SPARC-NEXT:    bne .LBB0_12
-; SPARC-NEXT:    mov %g3, %o0
+; SPARC-NEXT:    mov %g4, %o0
 ; SPARC-NEXT:  ! %bb.11: ! %start
-; SPARC-NEXT:    mov %l0, %o0
+; SPARC-NEXT:    mov %g0, %o0
 ; SPARC-NEXT:  .LBB0_12: ! %start
 ; SPARC-NEXT:    ld [%fp+-12], %l5 ! 4-byte Folded Reload
 ; SPARC-NEXT:    cmp %l5, 0
 ; SPARC-NEXT:    bne .LBB0_14
-; SPARC-NEXT:    mov %g3, %l5
+; SPARC-NEXT:    mov %g4, %l5
 ; SPARC-NEXT:  ! %bb.13: ! %start
-; SPARC-NEXT:    mov %l0, %l5
+; SPARC-NEXT:    mov %g0, %l5
 ; SPARC-NEXT:  .LBB0_14: ! %start
 ; SPARC-NEXT:    cmp %l3, %l6
 ; SPARC-NEXT:    bcs .LBB0_16
-; SPARC-NEXT:    mov %g3, %l3
+; SPARC-NEXT:    mov %g4, %l3
 ; SPARC-NEXT:  ! %bb.15: ! %start
-; SPARC-NEXT:    mov %l0, %l3
+; SPARC-NEXT:    mov %g0, %l3
 ; SPARC-NEXT:  .LBB0_16: ! %start
 ; SPARC-NEXT:    cmp %l4, 0
 ; SPARC-NEXT:    bne .LBB0_18
-; SPARC-NEXT:    mov %g3, %l4
+; SPARC-NEXT:    mov %g4, %l4
 ; SPARC-NEXT:  ! %bb.17: ! %start
-; SPARC-NEXT:    mov %l0, %l4
+; SPARC-NEXT:    mov %g0, %l4
 ; SPARC-NEXT:  .LBB0_18: ! %start
 ; SPARC-NEXT:    cmp %i0, 0
 ; SPARC-NEXT:    bne .LBB0_20
-; SPARC-NEXT:    mov %g3, %l7
+; SPARC-NEXT:    mov %g4, %l7
 ; SPARC-NEXT:  ! %bb.19: ! %start
-; SPARC-NEXT:    mov %l0, %l7
+; SPARC-NEXT:    mov %g0, %l7
 ; SPARC-NEXT:  .LBB0_20: ! %start
 ; SPARC-NEXT:    ld [%fp+-8], %l6 ! 4-byte Folded Reload
 ; SPARC-NEXT:    cmp %l6, 0
 ; SPARC-NEXT:    bne .LBB0_22
-; SPARC-NEXT:    mov %g3, %l6
+; SPARC-NEXT:    mov %g4, %l6
 ; SPARC-NEXT:  ! %bb.21: ! %start
-; SPARC-NEXT:    mov %l0, %l6
+; SPARC-NEXT:    mov %g0, %l6
 ; SPARC-NEXT:  .LBB0_22: ! %start
 ; SPARC-NEXT:    and %o1, %i2, %i2
 ; SPARC-NEXT:    ld [%fp+-4], %o1 ! 4-byte Folded Reload
 ; SPARC-NEXT:    cmp %o1, 0
 ; SPARC-NEXT:    and %l7, %l4, %o1
 ; SPARC-NEXT:    bne .LBB0_24
-; SPARC-NEXT:    mov %g3, %l4
+; SPARC-NEXT:    mov %g4, %l4
 ; SPARC-NEXT:  ! %bb.23: ! %start
-; SPARC-NEXT:    mov %l0, %l4
+; SPARC-NEXT:    mov %g0, %l4
 ; SPARC-NEXT:  .LBB0_24: ! %start
 ; SPARC-NEXT:    or %i2, %o0, %l7
-; SPARC-NEXT:    cmp %l2, %l1
+; SPARC-NEXT:    cmp %l2, %l0
 ; SPARC-NEXT:    or %o1, %l6, %l2
 ; SPARC-NEXT:    bcs .LBB0_26
-; SPARC-NEXT:    mov %g3, %i2
+; SPARC-NEXT:    mov %g4, %i2
 ; SPARC-NEXT:  ! %bb.25: ! %start
-; SPARC-NEXT:    mov %l0, %i2
+; SPARC-NEXT:    mov %g0, %i2
 ; SPARC-NEXT:  .LBB0_26: ! %start
-; SPARC-NEXT:    or %l7, %l5, %l1
+; SPARC-NEXT:    or %l7, %l5, %l0
 ; SPARC-NEXT:    or %i5, %i4, %i4
 ; SPARC-NEXT:    cmp %i4, 0
 ; SPARC-NEXT:    or %l2, %l4, %l2
 ; SPARC-NEXT:    bne .LBB0_28
-; SPARC-NEXT:    mov %g3, %i4
+; SPARC-NEXT:    mov %g4, %i4
 ; SPARC-NEXT:  ! %bb.27: ! %start
-; SPARC-NEXT:    mov %l0, %i4
+; SPARC-NEXT:    mov %g0, %i4
 ; SPARC-NEXT:  .LBB0_28: ! %start
-; SPARC-NEXT:    or %l1, %l3, %i5
+; SPARC-NEXT:    or %l0, %l3, %i5
 ; SPARC-NEXT:    or %i1, %i0, %i0
 ; SPARC-NEXT:    cmp %i0, 0
 ; SPARC-NEXT:    bne .LBB0_30
 ; SPARC-NEXT:    or %l2, %i2, %i0
 ; SPARC-NEXT:  ! %bb.29: ! %start
-; SPARC-NEXT:    mov %l0, %g3
+; SPARC-NEXT:    mov %g0, %g4
 ; SPARC-NEXT:  .LBB0_30: ! %start
-; SPARC-NEXT:    and %g3, %i4, %i1
+; SPARC-NEXT:    and %g4, %i4, %i1
 ; SPARC-NEXT:    or %i1, %i0, %i0
 ; SPARC-NEXT:    or %i0, %i5, %i0
-; SPARC-NEXT:    or %i0, %g4, %i0
+; SPARC-NEXT:    or %i0, %l1, %i0
 ; SPARC-NEXT:    and %i0, 1, %i4
 ; SPARC-NEXT:    mov %g2, %i0
-; SPARC-NEXT:    mov %i3, %i1
-; SPARC-NEXT:    mov %o2, %i2
+; SPARC-NEXT:    mov %g3, %i1
 ; SPARC-NEXT:    ret
-; SPARC-NEXT:    restore %g0, %o3, %o3
+; SPARC-NEXT:    restore %g0, %o2, %o2
 ;
 ; SPARC64-LABEL: muloti_test:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:    .register %g2, #scratch
 ; SPARC64-NEXT:    .register %g3, #scratch
 ; SPARC64-NEXT:  ! %bb.0: ! %start
 ; SPARC64-NEXT:    save %sp, -176, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
 ; SPARC64-NEXT:    .cfi_register %o7, %i7
-; SPARC64-NEXT:    mov 0, %i4
-; SPARC64-NEXT:    mov %i4, %o0
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i2, %o1
-; SPARC64-NEXT:    mov %i4, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i1, %o3
-; SPARC64-NEXT:    mov %o0, %i5
-; SPARC64-NEXT:    mov %o1, %l0
-; SPARC64-NEXT:    mov %i4, %o0
+; SPARC64-NEXT:    mov %o0, %i4
+; SPARC64-NEXT:    mov %o1, %i5
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i0, %o1
-; SPARC64-NEXT:    mov %i4, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i3, %o3
-; SPARC64-NEXT:    mov %o0, %l1
-; SPARC64-NEXT:    add %o1, %l0, %l0
-; SPARC64-NEXT:    mov %i4, %o0
+; SPARC64-NEXT:    mov %o0, %l0
+; SPARC64-NEXT:    add %o1, %i5, %i5
+; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i1, %o1
-; SPARC64-NEXT:    mov %i4, %o2
+; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i3, %o3
-; SPARC64-NEXT:    add %o0, %l0, %i1
 ; SPARC64-NEXT:    mov %g0, %i3
+; SPARC64-NEXT:    mov %g0, %g2
+; SPARC64-NEXT:    mov %g0, %g3
+; SPARC64-NEXT:    mov %g0, %g4
+; SPARC64-NEXT:    mov %g0, %g5
+; SPARC64-NEXT:    add %o0, %i5, %i1
 ; SPARC64-NEXT:    cmp %i1, %o0
-; SPARC64-NEXT:    mov %i3, %i4
-; SPARC64-NEXT:    movcs %xcc, 1, %i4
-; SPARC64-NEXT:    mov %i3, %g2
-; SPARC64-NEXT:    movrnz %l1, 1, %g2
-; SPARC64-NEXT:    mov %i3, %g3
+; SPARC64-NEXT:    movrnz %l0, 1, %g2
 ; SPARC64-NEXT:    movrnz %i2, 1, %g3
-; SPARC64-NEXT:    mov %i3, %i2
-; SPARC64-NEXT:    movrnz %i0, 1, %i2
-; SPARC64-NEXT:    and %i2, %g3, %i0
+; SPARC64-NEXT:    movrnz %i0, 1, %g4
+; SPARC64-NEXT:    movcs %xcc, 1, %i3
+; SPARC64-NEXT:    and %g4, %g3, %i0
 ; SPARC64-NEXT:    or %i0, %g2, %i0
-; SPARC64-NEXT:    movrnz %i5, 1, %i3
+; SPARC64-NEXT:    movrnz %i4, 1, %g5
+; SPARC64-NEXT:    or %i0, %g5, %i0
 ; SPARC64-NEXT:    or %i0, %i3, %i0
-; SPARC64-NEXT:    or %i0, %i4, %i0
 ; SPARC64-NEXT:    srl %i0, 0, %i2
 ; SPARC64-NEXT:    mov %i1, %i0
 ; SPARC64-NEXT:    ret
 ; SPARC64-NEXT:    restore %g0, %o1, %o1
 start:
   %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.generated.expected

 ; CHECK-LABEL: check_boundaries:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0:
 ; CHECK-NEXT:    save %sp, -112, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    st %g0, [%fp+-4]
-; CHECK-NEXT:    mov %g0, %i0
-; CHECK-NEXT:    cmp %i0, 0
+; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    st %g0, [%fp+-8]
 ; CHECK-NEXT:    be .LBB0_1
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:  ! %bb.2:
 ; CHECK-NEXT:    ba .LBB0_3
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:  .LBB0_1:
 ; CHECK-NEXT:    st %i0, [%fp+-8]

 ; CHECK-NEXT:    mov 4, %i4
 ; CHECK-NEXT:    st %i4, [%fp+-20]
 ; CHECK-NEXT:    st %i1, [%i0+%lo(x)]
 ; CHECK-NEXT:    !APP
 ; CHECK-NEXT:    !NO_APP
 ; CHECK-NEXT:    st %i1, [%fp+-8]
 ; CHECK-NEXT:    st %i2, [%fp+-12]
 ; CHECK-NEXT:    st %i3, [%fp+-16]
-; CHECK-NEXT:    mov %g0, %i0
 ; CHECK-NEXT:    st %i4, [%fp+-20]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:    restore
+; CHECK-NEXT:    restore %g0, %g0, %o0

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/sparc_generated_funcs.ll.nogenerated.expected

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -enable-machine-outliner -mtriple=sparc-unknown-linux < %s | FileCheck %s
 
 ; NOTE: Machine outliner doesn't run.
 @x = global i32 0, align 4
 
 define dso_local i32 @check_boundaries() #0 {
 ; CHECK-LABEL: check_boundaries:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0:
 ; CHECK-NEXT:    save %sp, -112, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    st %g0, [%fp+-4]
-; CHECK-NEXT:    mov %g0, %i0
-; CHECK-NEXT:    cmp %i0, 0
+; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    st %g0, [%fp+-8]
 ; CHECK-NEXT:    be .LBB0_1
 ; CHECK-NEXT:    mov 1, %i0
 ; CHECK-NEXT:  ! %bb.2:
 ; CHECK-NEXT:    ba .LBB0_3
 ; CHECK-NEXT:    st %i0, [%fp+-16]
 ; CHECK-NEXT:  .LBB0_1:
 ; CHECK-NEXT:    st %i0, [%fp+-8]

 ; CHECK-NEXT:    mov 4, %i4
 ; CHECK-NEXT:    st %i4, [%fp+-20]
 ; CHECK-NEXT:    st %i1, [%i0+%lo(x)]
 ; CHECK-NEXT:    !APP
 ; CHECK-NEXT:    !NO_APP
 ; CHECK-NEXT:    st %i1, [%fp+-8]
 ; CHECK-NEXT:    st %i2, [%fp+-12]
 ; CHECK-NEXT:    st %i3, [%fp+-16]
-; CHECK-NEXT:    mov %g0, %i0
 ; CHECK-NEXT:    st %i4, [%fp+-20]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:    restore
+; CHECK-NEXT:    restore %g0, %g0, %o0
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
 
   store i32 0, i32* %1, align 4
   store i32 0, i32* @x, align 4