[ARM,MVE] Update MVE_VMLA_qr for architecture change.

[simon_tatham]

Summary

In revision B.q and before of the Armv8-M architecture reference
manual, the vector/scalar forms of the vmla and vmlas instructions
came in signed and unsigned integer forms, such as vmla.s8 q0,q1,r2
or vmlas.u32 q3,q4,r5.

Revision B.r has changed this. There are no longer signed and unsigned
versions of these instructions, since they were functionally identical
anyway. Now there is just vmla.i8 (or i16 or i32, and similarly
for vmlas). Bit 28 of the instruction encoding, which was previously
0 for signed or 1 for unsigned, is now expected to be 0 always.

This change updates LLVM to the new version of the architecture. The
obsoleted encodings for unsigned integers are now decoding errors, and
only the still-valid encoding is ever emitted. This shouldn't break
any existing assembly code, because the old signed and unsigned
versions of the mnemonic are still accepted by the assembler (which is
standard practice anyway for all signedness-agnostic MVE integer
instructions).

[dmgreen]

LGTM. Thanks.
It's worth checking the downstream schedules for any fixups they need too.

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VFMAMLA_qr<string iname, string suffix,
   let Inst{8} = 0b0;
   let Inst{5} = 0b0;
   let validForTailPredication = 1;
   let hasSideEffects = 0;
 }
 
 multiclass MVE_VMLA_qr_multi<string iname, MVEVectorVTInfo VTI,
                              bit scalar_addend> {
-  def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size,
+  def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, 0b0, VTI.Size,
                          scalar_addend, VTI.Size>;
   defvar Inst = !cast<Instruction>(NAME);
   defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # iname # "_n_predicated");
   defvar v1   = (VTI.Vec MQPR:$v1);
   defvar v2   = (VTI.Vec MQPR:$v2);
   defvar vs   = (VTI.Vec (ARMvdup rGPR:$s));
   defvar s    = (i32 rGPR:$s);
   defvar pred = (VTI.Pred VCCR:$pred);
 
-  // The signed and unsigned variants of this instruction have different
-  // encodings, but they're functionally identical. For the sake of
-  // determinism, we generate only the unsigned variant.
-  if VTI.Unsigned then let Predicates = [HasMVEInt] in {
+  let Predicates = [HasMVEInt] in {
     if scalar_addend then {
       def : Pat<(VTI.Vec (add (mul v1, v2), vs)),
                 (VTI.Vec (Inst v1, v2, s))>;
     } else {
       def : Pat<(VTI.Vec (add (mul v2, vs), v1)),
                 (VTI.Vec (Inst v1, v2, s))>;
     }
 
     def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)),
               (VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred, zero_reg))>;
   }
 }
 
-defm MVE_VMLA_qr_s8   : MVE_VMLA_qr_multi<"vmla", MVE_v16s8, 0b0>;
-defm MVE_VMLA_qr_s16  : MVE_VMLA_qr_multi<"vmla", MVE_v8s16, 0b0>;
-defm MVE_VMLA_qr_s32  : MVE_VMLA_qr_multi<"vmla", MVE_v4s32, 0b0>;
-defm MVE_VMLA_qr_u8   : MVE_VMLA_qr_multi<"vmla", MVE_v16u8, 0b0>;
-defm MVE_VMLA_qr_u16  : MVE_VMLA_qr_multi<"vmla", MVE_v8u16, 0b0>;
-defm MVE_VMLA_qr_u32  : MVE_VMLA_qr_multi<"vmla", MVE_v4u32, 0b0>;
-
-defm MVE_VMLAS_qr_s8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16s8, 0b1>;
-defm MVE_VMLAS_qr_s16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8s16, 0b1>;
-defm MVE_VMLAS_qr_s32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4s32, 0b1>;
-defm MVE_VMLAS_qr_u8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16u8, 0b1>;
-defm MVE_VMLAS_qr_u16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8u16, 0b1>;
-defm MVE_VMLAS_qr_u32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4u32, 0b1>;
+defm MVE_VMLA_qr_i8   : MVE_VMLA_qr_multi<"vmla", MVE_v16i8, 0b0>;
+defm MVE_VMLA_qr_i16  : MVE_VMLA_qr_multi<"vmla", MVE_v8i16, 0b0>;
+defm MVE_VMLA_qr_i32  : MVE_VMLA_qr_multi<"vmla", MVE_v4i32, 0b0>;
+
+defm MVE_VMLAS_qr_i8  : MVE_VMLA_qr_multi<"vmlas", MVE_v16i8, 0b1>;
+defm MVE_VMLAS_qr_i16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8i16, 0b1>;
+defm MVE_VMLAS_qr_i32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4i32, 0b1>;
 
 multiclass MVE_VFMA_qr_multi<string iname, MVEVectorVTInfo VTI,
                              bit scalar_addend> {
   def "": MVE_VFMAMLA_qr<iname, VTI.Suffix, VTI.Size{0}, 0b11, scalar_addend, VTI.Size>;
   defvar Inst = !cast<Instruction>(NAME);
   defvar pred_int = int_arm_mve_fma_predicated;
   defvar v1   = (VTI.Vec MQPR:$v1);
   defvar v2   = (VTI.Vec MQPR:$v2);

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

 ; CHECK-NEXT:    dls lr, r3
 ; CHECK-NEXT:  .LBB0_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrbt.u32 q2, [r1], #4
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmla.u32 q0, q2, r0
+; CHECK-NEXT:    vmla.i32 q0, q2, r0
 ; CHECK-NEXT:    le lr, .LBB0_2
 ; CHECK-NEXT:  @ %bb.3: @ %middle.block
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp7 = icmp eq i32 %N, 0
   br i1 %cmp7, label %for.cond.cleanup, label %vector.ph

 ; CHECK-NEXT:    dls lr, r3
 ; CHECK-NEXT:  .LBB1_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrht.s32 q2, [r1], #8
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmla.u32 q0, q2, r0
+; CHECK-NEXT:    vmla.i32 q0, q2, r0
 ; CHECK-NEXT:    le lr, .LBB1_2
 ; CHECK-NEXT:  @ %bb.3: @ %middle.block
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp7 = icmp eq i32 %N, 0
   br i1 %cmp7, label %for.cond.cleanup, label %vector.ph

 ; CHECK-NEXT:    dls lr, r3
 ; CHECK-NEXT:  .LBB2_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrbt.u32 q2, [r1], #4
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmla.u32 q0, q2, r0
+; CHECK-NEXT:    vmla.i32 q0, q2, r0
 ; CHECK-NEXT:    le lr, .LBB2_2
 ; CHECK-NEXT:  @ %bb.3: @ %middle.block
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp7 = icmp eq i32 %N, 0
   br i1 %cmp7, label %for.cond.cleanup, label %vector.ph

 ; CHECK-NEXT:    dls lr, r3
 ; CHECK-NEXT:  .LBB3_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrht.u32 q2, [r1], #8
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmla.u32 q0, q2, r0
+; CHECK-NEXT:    vmla.i32 q0, q2, r0
 ; CHECK-NEXT:    le lr, .LBB3_2
 ; CHECK-NEXT:  @ %bb.3: @ %middle.block
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp7 = icmp eq i32 %N, 0
   br i1 %cmp7, label %for.cond.cleanup, label %vector.ph

 ; CHECK-NEXT:    dls lr, r3
 ; CHECK-NEXT:  .LBB4_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q2, [r1], #16
 ; CHECK-NEXT:    vmov q1, q0
-; CHECK-NEXT:    vmla.u32 q0, q2, r0
+; CHECK-NEXT:    vmla.i32 q0, q2, r0
 ; CHECK-NEXT:    le lr, .LBB4_2
 ; CHECK-NEXT:  @ %bb.3: @ %middle.block
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp6 = icmp eq i32 %N, 0
   br i1 %cmp6, label %for.cond.cleanup, label %vector.ph

 ; CHECK-NEXT:    mov.w r8, #0
 ; CHECK-NEXT:    b .LBB5_8
 ; CHECK-NEXT:  .LBB5_4: @ %vector.ph
 ; CHECK-NEXT:    dlstp.32 lr, r4
 ; CHECK-NEXT:  .LBB5_5: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrb.u32 q0, [r0], #4
 ; CHECK-NEXT:    vldrb.u32 q1, [r1], #4
-; CHECK-NEXT:    vmlas.u32 q1, q0, r2
+; CHECK-NEXT:    vmlas.i32 q1, q0, r2
 ; CHECK-NEXT:    vstrw.32 q1, [r3], #16
 ; CHECK-NEXT:    letp lr, .LBB5_5
 ; CHECK-NEXT:    b .LBB5_11
 ; CHECK-NEXT:  .LBB5_6: @ %for.body.preheader.new
 ; CHECK-NEXT:    bic r7, r4, #3
 ; CHECK-NEXT:    movs r6, #1
 ; CHECK-NEXT:    subs r7, #4
 ; CHECK-NEXT:    add.w r5, r3, #8

 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    popeq {r4, pc}
 ; CHECK-NEXT:  .LBB6_1: @ %vector.ph
 ; CHECK-NEXT:    dlstp.32 lr, r12
 ; CHECK-NEXT:  .LBB6_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.s32 q0, [r0], #8
 ; CHECK-NEXT:    vldrh.s32 q1, [r1], #8
-; CHECK-NEXT:    vmlas.u32 q1, q0, r2
+; CHECK-NEXT:    vmlas.i32 q1, q0, r2
 ; CHECK-NEXT:    vstrw.32 q1, [r3], #16
 ; CHECK-NEXT:    letp lr, .LBB6_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %vector.ph
 

 ; CHECK-NEXT:    mov.w r8, #0
 ; CHECK-NEXT:    b .LBB7_8
 ; CHECK-NEXT:  .LBB7_4: @ %vector.ph
 ; CHECK-NEXT:    dlstp.32 lr, r4
 ; CHECK-NEXT:  .LBB7_5: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrb.u32 q0, [r0], #4
 ; CHECK-NEXT:    vldrb.u32 q1, [r1], #4
-; CHECK-NEXT:    vmlas.u32 q1, q0, r2
+; CHECK-NEXT:    vmlas.i32 q1, q0, r2
 ; CHECK-NEXT:    vstrw.32 q1, [r3], #16
 ; CHECK-NEXT:    letp lr, .LBB7_5
 ; CHECK-NEXT:    b .LBB7_11
 ; CHECK-NEXT:  .LBB7_6: @ %for.body.preheader.new
 ; CHECK-NEXT:    bic r7, r4, #3
 ; CHECK-NEXT:    movs r6, #1
 ; CHECK-NEXT:    subs r7, #4
 ; CHECK-NEXT:    add.w r5, r3, #8

 ; CHECK-NEXT:    it eq
 ; CHECK-NEXT:    popeq {r4, pc}
 ; CHECK-NEXT:  .LBB8_1: @ %vector.ph
 ; CHECK-NEXT:    dlstp.32 lr, r12
 ; CHECK-NEXT:  .LBB8_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u32 q0, [r0], #8
 ; CHECK-NEXT:    vldrh.u32 q1, [r1], #8
-; CHECK-NEXT:    vmlas.u32 q1, q0, r2
+; CHECK-NEXT:    vmlas.i32 q1, q0, r2
 ; CHECK-NEXT:    vstrw.32 q1, [r3], #16
 ; CHECK-NEXT:    letp lr, .LBB8_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %vector.ph
 

 ; CHECK-NEXT:    mov.w r8, #0
 ; CHECK-NEXT:    b .LBB9_8
 ; CHECK-NEXT:  .LBB9_4: @ %vector.ph
 ; CHECK-NEXT:    dlstp.32 lr, r4
 ; CHECK-NEXT:  .LBB9_5: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r1], #16
-; CHECK-NEXT:    vmlas.u32 q1, q0, r2
+; CHECK-NEXT:    vmlas.i32 q1, q0, r2
 ; CHECK-NEXT:    vstrw.32 q1, [r3], #16
 ; CHECK-NEXT:    letp lr, .LBB9_5
 ; CHECK-NEXT:    b .LBB9_11
 ; CHECK-NEXT:  .LBB9_6: @ %for.body.preheader.new
 ; CHECK-NEXT:    bic r7, r4, #3
 ; CHECK-NEXT:    movs r6, #1
 ; CHECK-NEXT:    subs r7, #4
 ; CHECK-NEXT:    add.w r5, r3, #8

llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll

 ; CHECK-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    vctp.16 r6
 ; CHECK-NEXT:    subs r6, #8
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrht.u16 q0, [r5]
 ; CHECK-NEXT:    vshr.u16 q1, q0, #3
 ; CHECK-NEXT:    vand q1, q1, q2
 ; CHECK-NEXT:    vmov q2, q4
-; CHECK-NEXT:    vmla.u16 q2, q1, r2
+; CHECK-NEXT:    vmla.i16 q2, q1, r2
 ; CHECK-NEXT:    vshr.u16 q1, q2, #5
 ; CHECK-NEXT:    vshl.i16 q2, q0, #3
 ; CHECK-NEXT:    vand q3, q1, q5
 ; CHECK-NEXT:    vmov q1, q7
 ; CHECK-NEXT:    vand q2, q2, q6
 ; CHECK-NEXT:    vmov q7, q6
 ; CHECK-NEXT:    vmov q6, q5
 ; CHECK-NEXT:    vmov q5, q4
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vshr.u16 q0, q0, #9
-; CHECK-NEXT:    vmla.u16 q4, q2, r2
+; CHECK-NEXT:    vmla.i16 q4, q2, r2
 ; CHECK-NEXT:    vshr.u16 q2, q4, #11
 ; CHECK-NEXT:    vmov q4, q5
 ; CHECK-NEXT:    vmov q5, q6
 ; CHECK-NEXT:    vmov q6, q7
 ; CHECK-NEXT:    vmov q7, q1
 ; CHECK-NEXT:    vorr q1, q3, q2
 ; CHECK-NEXT:    vldrw.u32 q2, [sp, #16] @ 16-byte Reload
 ; CHECK-NEXT:    vand q0, q0, q7
-; CHECK-NEXT:    vmla.u16 q2, q0, r2
+; CHECK-NEXT:    vmla.i16 q2, q0, r2
 ; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vand q0, q2, q0
 ; CHECK-NEXT:    vldrw.u32 q2, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vorr q0, q1, q0
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vstrht.16 q0, [r5], #16
 ; CHECK-NEXT:    le lr, .LBB0_3
 ; CHECK-NEXT:  @ %bb.4: @ %for.cond3.for.cond.cleanup7_crit_edge.us

 ; CHECK-NEXT:    @ Parent Loop BB1_3 Depth=1
 ; CHECK-NEXT:    @ => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    vldrh.u16 q0, [r5]
 ; CHECK-NEXT:    vmov.f64 d6, d4
 ; CHECK-NEXT:    vmov.f64 d7, d5
 ; CHECK-NEXT:    vshl.i16 q1, q0, #3
 ; CHECK-NEXT:    vand q1, q1, q2
 ; CHECK-NEXT:    vmov q2, q4
-; CHECK-NEXT:    vmla.u16 q2, q1, r3
+; CHECK-NEXT:    vmla.i16 q2, q1, r3
 ; CHECK-NEXT:    vshr.u16 q1, q0, #3
 ; CHECK-NEXT:    vand q1, q1, q5
 ; CHECK-NEXT:    vmov.f64 d14, d10
 ; CHECK-NEXT:    vmov.f64 d15, d11
 ; CHECK-NEXT:    vmov.f64 d10, d8
 ; CHECK-NEXT:    vmov.f64 d11, d9
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #32] @ 16-byte Reload
 ; CHECK-NEXT:    vshr.u16 q0, q0, #9
-; CHECK-NEXT:    vmla.u16 q4, q1, r3
+; CHECK-NEXT:    vmla.i16 q4, q1, r3
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #48] @ 16-byte Reload
 ; CHECK-NEXT:    vand q0, q0, q1
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #16] @ 16-byte Reload
-; CHECK-NEXT:    vmla.u16 q1, q0, r3
+; CHECK-NEXT:    vmla.i16 q1, q0, r3
 ; CHECK-NEXT:    vshr.u16 q0, q2, #11
 ; CHECK-NEXT:    vshr.u16 q2, q4, #5
 ; CHECK-NEXT:    vand q2, q2, q6
 ; CHECK-NEXT:    vorr q0, q2, q0
 ; CHECK-NEXT:    vmov.f64 d4, d6
 ; CHECK-NEXT:    vmov.f64 d5, d7
 ; CHECK-NEXT:    vldrw.u32 q3, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.f64 d8, d10

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir

body:             |
   ; CHECK:   renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
   ; CHECK: bb.2.for.body:
   ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
   ; CHECK:   liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12
   ; CHECK:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
   ; CHECK:   renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
   ; CHECK:   renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
   ; CHECK:   renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
-  ; CHECK:   renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
+  ; CHECK:   renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
   ; CHECK:   renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, $noreg, undef renamable $q2
   ; CHECK:   renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q3
   ; CHECK:   renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg, $noreg
   ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
   ; CHECK: bb.3.for.cond.cleanup:
   ; CHECK:   liveins: $r12
   ; CHECK:   $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
   ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0
bb.2.for.body:
     renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg
     MVE_VPST 8, implicit $vpr
     renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
     MVE_VPST 8, implicit $vpr
     renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
     renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
     renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
     renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg
-    renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
+    renamable $q3 = MVE_VMLAS_qr_i32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
     MVE_VPST 2, implicit $vpr
     renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
     renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q3
     renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg
     renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14 /* CC::al */, $noreg
 
   bb.3.for.cond.cleanup:
     liveins: $r12
 
     $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
     frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0
 
 ...

llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll

 ; CHECK-NEXT:    vldrw.u32 q1, [r4]
 ; CHECK-NEXT:    mov.w lr, #12
 ; CHECK-NEXT:    movs r4, #8
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:  .LBB7_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmov q3, q0
 ; CHECK-NEXT:    vadd.i32 q2, q1, r4
-; CHECK-NEXT:    vmla.u32 q3, q1, lr
+; CHECK-NEXT:    vmla.i32 q3, q1, lr
 ; CHECK-NEXT:    vmul.i32 q1, q1, r12
 ; CHECK-NEXT:    vldrw.u32 q4, [q3, #24]
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vstrw.32 q1, [r3]
 ; CHECK-NEXT:    vmov q1, q2
 ; CHECK-NEXT:    vstrb.8 q4, [r1], #16
 ; CHECK-NEXT:    bne .LBB7_1
 ; CHECK-NEXT:  @ %bb.2: @ %end

 ; CHECK-NEXT:    mov.w lr, #12
 ; CHECK-NEXT:    movs r4, #8
 ; CHECK-NEXT:    vdup.32 q0, r0
 ; CHECK-NEXT:    vdup.32 q1, r5
 ; CHECK-NEXT:  .LBB8_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmov q4, q0
 ; CHECK-NEXT:    vadd.i32 q3, q2, r4
-; CHECK-NEXT:    vmla.u32 q4, q2, lr
+; CHECK-NEXT:    vmla.i32 q4, q2, lr
 ; CHECK-NEXT:    subs r2, #4
 ; CHECK-NEXT:    vldrw.u32 q5, [q4, #24]
 ; CHECK-NEXT:    vmov q4, q1
-; CHECK-NEXT:    vmla.u32 q4, q2, r12
+; CHECK-NEXT:    vmla.i32 q4, q2, r12
 ; CHECK-NEXT:    vmov q2, q3
 ; CHECK-NEXT:    vstrb.8 q5, [r1], #16
 ; CHECK-NEXT:    vstrw.32 q4, [r3]
 ; CHECK-NEXT:    bne .LBB8_1
 ; CHECK-NEXT:  @ %bb.2: @ %end
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11}
 ; CHECK-NEXT:    pop {r4, r5, r7, pc}
 ; CHECK-NEXT:    .p2align 4

 ; CHECK-NEXT:    vdup.32 q5, r7
 ; CHECK-NEXT:    vldrw.u32 q0, [sp] @ 16-byte Reload
 ; CHECK-NEXT:    vshl.i32 q5, q5, #2
 ; CHECK-NEXT:    vmov q6, q1
 ; CHECK-NEXT:    vadd.i32 q5, q5, r0
 ; CHECK-NEXT:    dls lr, r10
 ; CHECK-NEXT:    vmov.i32 q4, #0x0
 ; CHECK-NEXT:    vadd.i32 q5, q5, q0
-; CHECK-NEXT:    vmlas.u32 q6, q2, r5
+; CHECK-NEXT:    vmlas.i32 q6, q2, r5
 ; CHECK-NEXT:  .LBB9_3: @ %vector.body
 ; CHECK-NEXT:    @ Parent Loop BB9_1 Depth=1
 ; CHECK-NEXT:    @ Parent Loop BB9_2 Depth=2
 ; CHECK-NEXT:    @ => This Inner Loop Header: Depth=3
 ; CHECK-NEXT:    vadd.i32 q7, q6, q3
 ; CHECK-NEXT:    vldrw.u32 q0, [r1, q6, uxtw #2]
 ; CHECK-NEXT:    vldrw.u32 q6, [q5, #32]!
 ; CHECK-NEXT:    vmul.i32 q0, q0, q6

 ; CHECK-NEXT:    movs r4, #0
 ; CHECK-NEXT:    mov.w r10, #0
 ; CHECK-NEXT:    b .LBB10_13
 ; CHECK-NEXT:  .LBB10_10: @ %vector.ph
 ; CHECK-NEXT:    @ in Loop: Header=BB10_8 Depth=2
 ; CHECK-NEXT:    ldr r0, [sp, #16] @ 4-byte Reload
 ; CHECK-NEXT:    vmov q5, q1
 ; CHECK-NEXT:    vmov.i32 q4, #0x0
-; CHECK-NEXT:    vmlas.u32 q5, q2, r8
+; CHECK-NEXT:    vmlas.i32 q5, q2, r8
 ; CHECK-NEXT:    dls lr, r0
 ; CHECK-NEXT:    ldr r3, [sp, #20] @ 4-byte Reload
 ; CHECK-NEXT:  .LBB10_11: @ %vector.body
 ; CHECK-NEXT:    @ Parent Loop BB10_5 Depth=1
 ; CHECK-NEXT:    @ Parent Loop BB10_8 Depth=2
 ; CHECK-NEXT:    @ => This Inner Loop Header: Depth=3
 ; CHECK-NEXT:    vadd.i32 q6, q5, q3
 ; CHECK-NEXT:    vldrh.s32 q7, [r1, q5, uxtw #1]

 ; CHECK-NEXT:    @ Parent Loop BB11_2 Depth=2
 ; CHECK-NEXT:    @ Parent Loop BB11_3 Depth=3
 ; CHECK-NEXT:    @ => This Loop Header: Depth=4
 ; CHECK-NEXT:    @ Child Loop BB11_5 Depth 5
 ; CHECK-NEXT:    mul r4, r11, r6
 ; CHECK-NEXT:    vdup.32 q3, r5
 ; CHECK-NEXT:    vdup.32 q2, r7
 ; CHECK-NEXT:    vadd.i32 q4, q1, r4
-; CHECK-NEXT:    vmla.u32 q3, q4, r2
+; CHECK-NEXT:    vmla.i32 q3, q4, r2
 ; CHECK-NEXT:    adds r4, #113
 ; CHECK-NEXT:    vadd.i32 q4, q1, r4
 ; CHECK-NEXT:    mov r4, r8
-; CHECK-NEXT:    vmla.u32 q2, q4, r2
+; CHECK-NEXT:    vmla.i32 q2, q4, r2
 ; CHECK-NEXT:  .LBB11_5: @ %vector.body
 ; CHECK-NEXT:    @ Parent Loop BB11_1 Depth=1
 ; CHECK-NEXT:    @ Parent Loop BB11_2 Depth=2
 ; CHECK-NEXT:    @ Parent Loop BB11_3 Depth=3
 ; CHECK-NEXT:    @ Parent Loop BB11_4 Depth=4
 ; CHECK-NEXT:    @ => This Inner Loop Header: Depth=5
 ; CHECK-NEXT:    vldrb.s32 q6, [r0, q2]
 ; CHECK-NEXT:    vadd.i32 q5, q2, q0

llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll

 ; CHECK-NEXT:    movs r1, #3
 ; CHECK-NEXT:  .LBB2_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vctp.32 r3
 ; CHECK-NEXT:    subs r3, #4
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vldrwt.u32 q2, [r4], #16
 ; CHECK-NEXT:    vmul.i32 q3, q2, r1
-; CHECK-NEXT:    vmla.u32 q0, q2, r1
+; CHECK-NEXT:    vmla.i32 q0, q2, r1
 ; CHECK-NEXT:    vpst
 ; CHECK-NEXT:    vstrwt.32 q3, [q1, #80]!
 ; CHECK-NEXT:    le lr, .LBB2_1
 ; CHECK-NEXT:  @ %bb.2: @ %middle.block
 ; CHECK-NEXT:    vaddv.u32 r0, q0
 ; CHECK-NEXT:    str.w r0, [r2, r12, lsl #2]
 ; CHECK-NEXT:    pop {r4, pc}
 ; CHECK-NEXT:    .p2align 4

 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB3_2: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrb.u32 q4, [r0, q0]
 ; CHECK-NEXT:    vldrb.u32 q3, [r0, q1]
 ; CHECK-NEXT:    vldrb.u32 q5, [r0, q2]
 ; CHECK-NEXT:    adds r0, #12
 ; CHECK-NEXT:    vmul.i32 q6, q4, r11
-; CHECK-NEXT:    vmla.u32 q6, q3, r8
-; CHECK-NEXT:    vmla.u32 q6, q5, r12
+; CHECK-NEXT:    vmla.i32 q6, q3, r8
+; CHECK-NEXT:    vmla.i32 q6, q5, r12
 ; CHECK-NEXT:    vadd.i32 q6, q6, r3
 ; CHECK-NEXT:    vshr.u32 q6, q6, #16
 ; CHECK-NEXT:    vstrb.32 q6, [r1, q1]
 ; CHECK-NEXT:    vmul.i32 q6, q4, r4
 ; CHECK-NEXT:    vmul.i32 q4, q4, r10
-; CHECK-NEXT:    vmla.u32 q6, q3, r5
-; CHECK-NEXT:    vmla.u32 q4, q3, r7
-; CHECK-NEXT:    vmla.u32 q6, q5, r6
-; CHECK-NEXT:    vmla.u32 q4, q5, r9
+; CHECK-NEXT:    vmla.i32 q6, q3, r5
+; CHECK-NEXT:    vmla.i32 q4, q3, r7
+; CHECK-NEXT:    vmla.i32 q6, q5, r6
+; CHECK-NEXT:    vmla.i32 q4, q5, r9
 ; CHECK-NEXT:    vadd.i32 q6, q6, r3
 ; CHECK-NEXT:    vadd.i32 q3, q4, r3
 ; CHECK-NEXT:    vshr.u32 q6, q6, #16
 ; CHECK-NEXT:    vshr.u32 q3, q3, #16
 ; CHECK-NEXT:    vstrb.32 q3, [r1, q0]
 ; CHECK-NEXT:    vstrb.32 q6, [r1, q2]
 ; CHECK-NEXT:    adds r1, #12
 ; CHECK-NEXT:    letp lr, .LBB3_2

llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

entry:
   %0 = fneg <4 x float> %c
   %1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %0, <4 x float> %a)
   ret <4 x float> %1
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
 ; CHECK-LABEL: test_vmlaq_n_s8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    vmla.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   %0 = mul <16 x i8> %.splat, %b
   %1 = add <16 x i8> %0, %a
   ret <16 x i8> %1
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
 ; CHECK-LABEL: test_vmlaq_n_s16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    vmla.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   %0 = mul <8 x i16> %.splat, %b
   %1 = add <8 x i16> %0, %a
   ret <8 x i16> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
 ; CHECK-LABEL: test_vmlaq_n_s32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    vmla.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   %0 = mul <4 x i32> %.splat, %b
   %1 = add <4 x i32> %0, %a
   ret <4 x i32> %1
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {
 ; CHECK-LABEL: test_vmlaq_n_u8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    vmla.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   %0 = mul <16 x i8> %.splat, %b
   %1 = add <16 x i8> %0, %a
   ret <16 x i8> %1
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {
 ; CHECK-LABEL: test_vmlaq_n_u16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    vmla.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   %0 = mul <8 x i16> %.splat, %b
   %1 = add <8 x i16> %0, %a
   ret <8 x i16> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
 ; CHECK-LABEL: test_vmlaq_n_u32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    vmla.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   %0 = mul <4 x i32> %.splat, %b
   %1 = add <4 x i32> %0, %a
   ret <4 x i32> %1
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
 ; CHECK-LABEL: test_vmlasq_n_s8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u8 q1, q0, r0
+; CHECK-NEXT:    vmlas.i8 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <16 x i8> %b, %a
   %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   %1 = add <16 x i8> %.splat, %0
   ret <16 x i8> %1
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c) {
 ; CHECK-LABEL: test_vmlasq_n_s16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u16 q1, q0, r0
+; CHECK-NEXT:    vmlas.i16 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <8 x i16> %b, %a
   %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   %1 = add <8 x i16> %.splat, %0
   ret <8 x i16> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
 ; CHECK-LABEL: test_vmlasq_n_s32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u32 q1, q0, r0
+; CHECK-NEXT:    vmlas.i32 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <4 x i32> %b, %a
   %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   %1 = add <4 x i32> %.splat, %0
   ret <4 x i32> %1
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c) {
 ; CHECK-LABEL: test_vmlasq_n_u8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u8 q1, q0, r0
+; CHECK-NEXT:    vmlas.i8 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <16 x i8> %b, %a
   %.splatinsert = insertelement <16 x i8> undef, i8 %c, i32 0
   %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   %1 = add <16 x i8> %.splat, %0
   ret <16 x i8> %1
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c) {
 ; CHECK-LABEL: test_vmlasq_n_u16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u16 q1, q0, r0
+; CHECK-NEXT:    vmlas.i16 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <8 x i16> %b, %a
   %.splatinsert = insertelement <8 x i16> undef, i16 %c, i32 0
   %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   %1 = add <8 x i16> %.splat, %0
   ret <8 x i16> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c) {
 ; CHECK-LABEL: test_vmlasq_n_u32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u32 q1, q0, r0
+; CHECK-NEXT:    vmlas.i32 q1, q0, r0
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = mul <4 x i32> %b, %a
   %.splatinsert = insertelement <4 x i32> undef, i32 %c, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   %1 = add <4 x i32> %.splat, %0
   ret <4 x i32> %1
entry:
   ret <4 x float> %3
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_s8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u8 q0, q1, r0
+; CHECK-NEXT:    vmlat.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i8 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
   %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_s16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u16 q0, q1, r0
+; CHECK-NEXT:    vmlat.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
   %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_s32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u32 q0, q1, r0
+; CHECK-NEXT:    vmlat.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
   ret <4 x i32> %2
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_u8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u8 q0, q1, r0
+; CHECK-NEXT:    vmlat.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i8 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
   %3 = tail call <16 x i8> @llvm.arm.mve.vmla.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlaq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_u16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u16 q0, q1, r0
+; CHECK-NEXT:    vmlat.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
   %3 = tail call <8 x i16> @llvm.arm.mve.vmla.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlaq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlaq_m_n_u32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlat.u32 q0, q1, r0
+; CHECK-NEXT:    vmlat.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   %2 = tail call <4 x i32> @llvm.arm.mve.vmla.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
   ret <4 x i32> %2
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_s8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u8 q0, q1, r0
+; CHECK-NEXT:    vmlast.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i8 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
   %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_s16(<8 x i16> %a, <8 x i16> %b, i16 signext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_s16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u16 q0, q1, r0
+; CHECK-NEXT:    vmlast.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
   %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_s32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_s32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u32 q0, q1, r0
+; CHECK-NEXT:    vmlast.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
   ret <4 x i32> %2
 }
 
 define arm_aapcs_vfpcc <16 x i8> @test_vmlasq_m_n_u8(<16 x i8> %a, <16 x i8> %b, i8 zeroext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_u8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u8 q0, q1, r0
+; CHECK-NEXT:    vmlast.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i8 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1)
   %3 = tail call <16 x i8> @llvm.arm.mve.vmlas.n.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 %0, <16 x i1> %2)
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmlasq_m_n_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_u16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u16 q0, q1, r0
+; CHECK-NEXT:    vmlast.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %c to i32
   %1 = zext i16 %p to i32
   %2 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1)
   %3 = tail call <8 x i16> @llvm.arm.mve.vmlas.n.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 %0, <8 x i1> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlasq_m_n_u32(<4 x i32> %a, <4 x i32> %b, i32 %c, i16 zeroext %p) {
 ; CHECK-LABEL: test_vmlasq_m_n_u32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpst
-; CHECK-NEXT:    vmlast.u32 q0, q1, r0
+; CHECK-NEXT:    vmlast.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = zext i16 %p to i32
   %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
   %2 = tail call <4 x i32> @llvm.arm.mve.vmlas.n.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c, <4 x i1> %1)
   ret <4 x i32> %2
 }
 

llvm/test/CodeGen/Thumb2/mve-qrintr.ll

 ; CHECK-NEXT:    it lt
 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB22_1: @ %for.body.preheader
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB22_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmla.u32 q1, q0, r3
+; CHECK-NEXT:    vmla.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB22_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %.splatinsert = insertelement <4 x i32> poison, i32 %z, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
   %cmp14 = icmp sgt i32 %n, 0

 ; CHECK-NEXT:    it lt
 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB23_1: @ %for.body.preheader
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB23_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmla.u32 q1, q0, r3
+; CHECK-NEXT:    vmla.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB23_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp15 = icmp sgt i32 %n, 0
   br i1 %cmp15, label %for.body, label %for.cond.cleanup
 

 ; CHECK-NEXT:    it lt
 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB24_1: @ %for.body.preheader
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB24_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r1]
-; CHECK-NEXT:    vmlas.u32 q1, q0, r3
+; CHECK-NEXT:    vmlas.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB24_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %.splatinsert = insertelement <4 x i32> poison, i32 %z, i32 0
   %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
   %cmp14 = icmp sgt i32 %n, 0

 ; CHECK-NEXT:    it lt
 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB25_1: @ %for.body.preheader
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB25_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmlas.u32 q1, q0, r3
+; CHECK-NEXT:    vmlas.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB25_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp15 = icmp sgt i32 %n, 0
   br i1 %cmp15, label %for.body, label %for.cond.cleanup
 

llvm/test/CodeGen/Thumb2/mve-qrintrsplat.ll

 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB22_1: @ %for.body.preheader
 ; CHECK-NEXT:    movs r3, #10
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB22_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmla.u32 q1, q0, r3
+; CHECK-NEXT:    vmla.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB22_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp14 = icmp sgt i32 %n, 0
   br i1 %cmp14, label %for.body, label %for.cond.cleanup
 

 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB23_1: @ %for.body.preheader
 ; CHECK-NEXT:    movs r3, #10
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB23_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmla.u32 q1, q0, r3
+; CHECK-NEXT:    vmla.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB23_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp15 = icmp sgt i32 %n, 0
   br i1 %cmp15, label %for.body, label %for.cond.cleanup
 

 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB24_1: @ %for.body.preheader
 ; CHECK-NEXT:    movs r3, #10
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB24_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r1]
-; CHECK-NEXT:    vmlas.u32 q1, q0, r3
+; CHECK-NEXT:    vmlas.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB24_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp14 = icmp sgt i32 %n, 0
   br i1 %cmp14, label %for.body, label %for.cond.cleanup
 

 ; CHECK-NEXT:    poplt {r7, pc}
 ; CHECK-NEXT:  .LBB25_1: @ %for.body.preheader
 ; CHECK-NEXT:    movs r3, #10
 ; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB25_2: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r1]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
-; CHECK-NEXT:    vmlas.u32 q1, q0, r3
+; CHECK-NEXT:    vmlas.i32 q1, q0, r3
 ; CHECK-NEXT:    vstrw.32 q1, [r1], #16
 ; CHECK-NEXT:    letp lr, .LBB25_2
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %cmp15 = icmp sgt i32 %n, 0
   br i1 %cmp15, label %for.body, label %for.cond.cleanup
 

llvm/test/CodeGen/Thumb2/mve-vmla.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
 
 define arm_aapcs_vfpcc <4 x i32> @vmlau32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
 ; CHECK-LABEL: vmlau32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    vmla.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <4 x i32> undef, i32 %X, i32 0
   %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
   %2 = mul nsw <4 x i32> %B, %1
   %3 = add nsw <4 x i32> %A, %2
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vmlau32b(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
 ; CHECK-LABEL: vmlau32b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u32 q0, q1, r0
+; CHECK-NEXT:    vmla.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <4 x i32> undef, i32 %X, i32 0
   %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
   %2 = mul nsw <4 x i32> %1, %B
   %3 = add nsw <4 x i32> %2, %A
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vmlau16(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
 ; CHECK-LABEL: vmlau16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    vmla.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <8 x i16> undef, i16 %X, i32 0
   %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
   %2 = mul nsw <8 x i16> %B, %1
   %3 = add nsw <8 x i16> %A, %2
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vmlau16b(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
 ; CHECK-LABEL: vmlau16b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u16 q0, q1, r0
+; CHECK-NEXT:    vmla.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <8 x i16> undef, i16 %X, i32 0
   %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
   %2 = mul nsw <8 x i16> %1, %B
   %3 = add nsw <8 x i16> %2, %A
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <16 x i8> @vmlau8(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
 ; CHECK-LABEL: vmlau8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    vmla.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <16 x i8> undef, i8 %X, i32 0
   %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
   %2 = mul nsw <16 x i8> %B, %1
   %3 = add nsw <16 x i8> %A, %2
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <16 x i8> @vmlau8b(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
 ; CHECK-LABEL: vmlau8b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmla.u8 q0, q1, r0
+; CHECK-NEXT:    vmla.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <16 x i8> undef, i8 %X, i32 0
   %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
   %2 = mul nsw <16 x i8> %1, %B
   %3 = add nsw <16 x i8> %2, %A
   ret <16 x i8> %3
 }
 
 define void @vmla32_in_loop(i32* %s1, i32 %x, i32* %d, i32 %n) {
 ; CHECK-LABEL: vmla32_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB6_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
 ; CHECK-NEXT:    vldrw.u32 q1, [r2]
 ; CHECK-NEXT:    subs r3, #4
-; CHECK-NEXT:    vmla.u32 q1, q0, r1
+; CHECK-NEXT:    vmla.i32 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB6_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert8 = insertelement <4 x i32> undef, i32 %x, i32 0
   %broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
   br label %vector.body

 define void @vmla16_in_loop(i16* %s1, i16 %x, i16* %d, i32 %n) {
 ; CHECK-LABEL: vmla16_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB7_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q0, [r0], #16
 ; CHECK-NEXT:    vldrh.u16 q1, [r2]
 ; CHECK-NEXT:    subs r3, #8
-; CHECK-NEXT:    vmla.u16 q1, q0, r1
+; CHECK-NEXT:    vmla.i16 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB7_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert11 = insertelement <8 x i16> undef, i16 %x, i32 0
   %broadcast.splat12 = shufflevector <8 x i16> %broadcast.splatinsert11, <8 x i16> undef, <8 x i32> zeroinitializer
   br label %vector.body

 define void @vmla8_in_loop(i8* %s1, i8 %x, i8* %d, i32 %n) {
 ; CHECK-LABEL: vmla8_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB8_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q0, [r0], #16
 ; CHECK-NEXT:    vldrh.u16 q1, [r2]
 ; CHECK-NEXT:    subs r3, #16
-; CHECK-NEXT:    vmla.u8 q1, q0, r1
+; CHECK-NEXT:    vmla.i8 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB8_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert11 = insertelement <16 x i8> undef, i8 %x, i32 0
   %broadcast.splat12 = shufflevector <16 x i8> %broadcast.splatinsert11, <16 x i8> undef, <16 x i32> zeroinitializer
   br label %vector.body

 for.cond.cleanup:
   ret void
 }
 
 
 define arm_aapcs_vfpcc <4 x i32> @vmlasu32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
 ; CHECK-LABEL: vmlasu32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u32 q0, q1, r0
+; CHECK-NEXT:    vmlas.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <4 x i32> undef, i32 %X, i32 0
   %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
   %2 = mul nsw <4 x i32> %A, %B
   %3 = add nsw <4 x i32> %1, %2
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vmlasu32b(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
 ; CHECK-LABEL: vmlasu32b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u32 q0, q1, r0
+; CHECK-NEXT:    vmlas.i32 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <4 x i32> undef, i32 %X, i32 0
   %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
   %2 = mul nsw <4 x i32> %A, %B
   %3 = add nsw <4 x i32> %2, %1
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vmlasu16(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
 ; CHECK-LABEL: vmlasu16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u16 q0, q1, r0
+; CHECK-NEXT:    vmlas.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <8 x i16> undef, i16 %X, i32 0
   %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
   %2 = mul nsw <8 x i16> %A, %B
   %3 = add nsw <8 x i16> %1, %2
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vmlasu16b(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
 ; CHECK-LABEL: vmlasu16b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u16 q0, q1, r0
+; CHECK-NEXT:    vmlas.i16 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <8 x i16> undef, i16 %X, i32 0
   %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
   %2 = mul nsw <8 x i16> %A, %B
   %3 = add nsw <8 x i16> %2, %1
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <16 x i8> @vmlasu8(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
 ; CHECK-LABEL: vmlasu8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u8 q0, q1, r0
+; CHECK-NEXT:    vmlas.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <16 x i8> undef, i8 %X, i32 0
   %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
   %2 = mul nsw <16 x i8> %A, %B
   %3 = add nsw <16 x i8> %1, %2
   ret <16 x i8> %3
 }
 
 define arm_aapcs_vfpcc <16 x i8> @vmlasu8b(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
 ; CHECK-LABEL: vmlasu8b:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmlas.u8 q0, q1, r0
+; CHECK-NEXT:    vmlas.i8 q0, q1, r0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = insertelement <16 x i8> undef, i8 %X, i32 0
   %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
   %2 = mul nsw <16 x i8> %A, %B
   %3 = add nsw <16 x i8> %2, %1
   ret <16 x i8> %3
 }
 
 define void @vmlas32_in_loop(i32* %s1, i32 %x, i32* %d, i32 %n) {
 ; CHECK-LABEL: vmlas32_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB15_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrw.u32 q0, [r2]
 ; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
 ; CHECK-NEXT:    subs r3, #4
-; CHECK-NEXT:    vmlas.u32 q1, q0, r1
+; CHECK-NEXT:    vmlas.i32 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB15_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert8 = insertelement <4 x i32> undef, i32 %x, i32 0
   %broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
   br label %vector.body

 define void @vmlas16_in_loop(i16* %s1, i16 %x, i16* %d, i32 %n) {
 ; CHECK-LABEL: vmlas16_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB16_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q0, [r2]
 ; CHECK-NEXT:    vldrh.u16 q1, [r0], #16
 ; CHECK-NEXT:    subs r3, #8
-; CHECK-NEXT:    vmlas.u16 q1, q0, r1
+; CHECK-NEXT:    vmlas.i16 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB16_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert11 = insertelement <8 x i16> undef, i16 %x, i32 0
   %broadcast.splat12 = shufflevector <8 x i16> %broadcast.splatinsert11, <8 x i16> undef, <8 x i32> zeroinitializer
   br label %vector.body

 define void @vmlas8_in_loop(i8* %s1, i8 %x, i8* %d, i32 %n) {
 ; CHECK-LABEL: vmlas8_in_loop:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:  .LBB17_1: @ %vector.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vldrh.u16 q0, [r2]
 ; CHECK-NEXT:    vldrh.u16 q1, [r0], #16
 ; CHECK-NEXT:    subs r3, #16
-; CHECK-NEXT:    vmlas.u8 q1, q0, r1
+; CHECK-NEXT:    vmlas.i8 q1, q0, r1
 ; CHECK-NEXT:    vstrb.8 q1, [r2], #16
 ; CHECK-NEXT:    bne .LBB17_1
 ; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
 ; CHECK-NEXT:    bx lr
 entry:
   %broadcast.splatinsert11 = insertelement <16 x i8> undef, i8 %x, i32 0
   %broadcast.splat12 = shufflevector <16 x i8> %broadcast.splatinsert11, <16 x i8> undef, <16 x i32> zeroinitializer
   br label %vector.body

llvm/test/CodeGen/Thumb2/mve-vmovlloop.ll

 ; CHECK-NEXT:    dlstp.16 lr, r1
 ; CHECK-NEXT:  .LBB3_1: @ %do.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovlb.u8 q1, q1
 ; CHECK-NEXT:    vsub.i16 q3, q0, q1
 ; CHECK-NEXT:    vmovlb.u8 q2, q2
 ; CHECK-NEXT:    vmul.i16 q3, q2, q3
 ; CHECK-NEXT:    vldrb.u16 q2, [r0], #8
-; CHECK-NEXT:    vmla.u16 q3, q1, r3
+; CHECK-NEXT:    vmla.i16 q3, q1, r3
 ; CHECK-NEXT:    vldrb.u16 q1, [r2], #8
 ; CHECK-NEXT:    vshr.u16 q3, q3, #8
 ; CHECK-NEXT:    vstrb.16 q3, [r0, #-16]
 ; CHECK-NEXT:    letp lr, .LBB3_1
 ; CHECK-NEXT:  @ %bb.2: @ %do.end
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
   %conv3 = sext i16 %0 to i32

llvm/test/MC/ARM/mve-qdest-rsrc.s

 # CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
 # CHECK-NOFP-NOT: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
 vfmas.f16 q0, q0, r12
 
 # CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
 # CHECK-NOFP-NOT: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
 vfmas.f32 q0, q3, lr
 
-# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
-# CHECK-NOFP: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK: vmlas.i8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.i8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+vmlas.i8 q0, q0, r6
+
+# CHECK: vmlas.i16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOFP: vmlas.i16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+vmlas.i16 q0, q2, r9
+
+# CHECK: vmlas.i32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.i32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+vmlas.i32 q0, q7, r6
+
+# CHECK: vmlas.i8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.i8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
 vmlas.s8 q0, q0, r6
 
-# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
-# CHECK-NOFP: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK: vmlas.i16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOFP: vmlas.i16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
 vmlas.s16 q0, q2, r9
 
-# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
-# CHECK-NOFP: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK: vmlas.i32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.i32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
 vmlas.s32 q0, q7, r6
 
-# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
-# CHECK-NOFP: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK: vmlas.i8 q0, q5, lr  @ encoding: [0x0b,0xee,0x4e,0x1e]
+# CHECK-NOFP: vmlas.i8 q0, q5, lr  @ encoding: [0x0b,0xee,0x4e,0x1e]
 vmlas.u8 q0, q5, lr
 
-# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
-# CHECK-NOFP: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK: vmlas.i16 q0, q3, r12  @ encoding: [0x17,0xee,0x4c,0x1e]
+# CHECK-NOFP: vmlas.i16 q0, q3, r12  @ encoding: [0x17,0xee,0x4c,0x1e]
 vmlas.u16 q0, q3, r12
 
-# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
-# CHECK-NOFP: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK: vmlas.i32 q1, q1, r11  @ encoding: [0x23,0xee,0x4b,0x3e]
+# CHECK-NOFP: vmlas.i32 q1, q1, r11  @ encoding: [0x23,0xee,0x4b,0x3e]
 vmlas.u32 q1, q1, r11
 
 # CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
 # CHECK-NOFP-NOT: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
 vfma.f16 q1, q1, r6
 
 # CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
 # CHECK-NOFP-NOT: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
 vfmas.f32 q7, q4, r6
 
-# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
-# CHECK-NOFP: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK: vmla.i8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOFP: vmla.i8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+vmla.i8 q0, q3, r8
+
+# CHECK: vmla.i16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.i16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+vmla.i16 q1, q3, r10
+
+# CHECK: vmla.i32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOFP: vmla.i32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+vmla.i32 q1, q3, r1
+
+# CHECK: vmla.i8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOFP: vmla.i8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
 vmla.s8 q0, q3, r8
 
-# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
-# CHECK-NOFP: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK: vmla.i16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.i16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
 vmla.s16 q1, q3, r10
 
-# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
-# CHECK-NOFP: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK: vmla.i32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOFP: vmla.i32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
 vmla.s32 q1, q3, r1
 
-# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
-# CHECK-NOFP: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK: vmla.i8 q0, q7, r10  @ encoding: [0x0f,0xee,0x4a,0x0e]
+# CHECK-NOFP: vmla.i8 q0, q7, r10  @ encoding: [0x0f,0xee,0x4a,0x0e]
 vmla.u8 q0, q7, r10
 
-# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
-# CHECK-NOFP: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK: vmla.i16 q0, q0, r7  @ encoding: [0x11,0xee,0x47,0x0e]
+# CHECK-NOFP: vmla.i16 q0, q0, r7  @ encoding: [0x11,0xee,0x47,0x0e]
 vmla.u16 q0, q0, r7
 
-# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
-# CHECK-NOFP: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK: vmla.i32 q1, q6, r10  @ encoding: [0x2d,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.i32 q1, q6, r10  @ encoding: [0x2d,0xee,0x4a,0x2e]
 vmla.u32 q1, q6, r10
 
 # CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
 # CHECK-NOFP: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
 vqdmlash.s8 q0, q0, r5
 
 # CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
 # CHECK-NOFP: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]

llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt

 # CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x31,0xfe,0x4c,0x1e]
 
 # CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x37,0xee,0x4e,0x1e]
 
-# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK: vmlas.i8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x01,0xee,0x46,0x1e]
 
-# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK: vmlas.i16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x15,0xee,0x49,0x1e]
 
-# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK: vmlas.i32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x2f,0xee,0x46,0x1e]
 
-# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0b,0xfe,0x4e,0x1e]
 
-# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x17,0xfe,0x4c,0x1e]
 
-# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x23,0xfe,0x4b,0x3e]
 
 # CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x33,0xfe,0x46,0x2e]
 
 # CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x39,0xee,0x46,0xfe]
 
-# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK: vmla.i8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x07,0xee,0x48,0x0e]
 
-# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK: vmla.i16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x17,0xee,0x4a,0x2e]
 
-# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK: vmla.i32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x27,0xee,0x41,0x2e]
 
-# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x0f,0xfe,0x4a,0x0e]
 
-# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x11,0xfe,0x47,0x0e]
 
-# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x2d,0xfe,0x4a,0x2e]
 
 # CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x00,0xee,0x65,0x1e]
 
 # CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]

llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll

for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i64 [ 0, %entry ], [ %add, %for.body ]
   ret i64 %r.0.lcssa
 }
 
-; 4x to use VMLA.u32
+; 4x to use VMLA.i32
 define i32 @mla_i32_i32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i32_i32(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP8]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 3
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4
for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
   ret i32 %r.0.lcssa
 }
 
-; 8x to use VMLA.u16
+; 8x to use VMLA.i16
 define i32 @mla_i16_i32(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i16_i32(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
   ret i32 %r.0.lcssa
 }
 
-; 16x to use VMLA.u8
+; 16x to use VMLA.i8
 define i32 @mla_i8_i32(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i8_i32(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
   ret i32 %r.0.lcssa
 }
 
-; 8x to use VMLA.u16
+; 8x to use VMLA.i16
 define signext i16 @mla_i16_i16(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i16_i16(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 7
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -8
for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
   ret i16 %r.0.lcssa
 }
 
-; 16x to use VMLA.u8
+; 16x to use VMLA.i8
 define signext i16 @mla_i8_i16(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i8_i16(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP11]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
for.body:                                         ; preds = %entry, %for.body
   %exitcond = icmp eq i32 %inc, %n
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.body, %entry
   %r.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ]
   ret i16 %r.0.lcssa
 }
 
-; 16x to use VMLA.u8
+; 16x to use VMLA.i8
 define zeroext i8 @mla_i8_i8(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i8_i8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP10]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
for.body:                                         ; preds = %for.body.preheader, %for.body
   %cmp = icmp slt i32 %iv.next, %n
   br i1 %cmp, label %for.body, label %exit
 
 exit:
   %ret.lcssa = phi i32 [ 0, %entry ], [ %red.2, %for.body ]
   ret i32 %ret.lcssa
 }
 
-; 16x to use VMLA.u8, same as mla_i8_i32 with multiple uses of the ext `add(mul(x, x))`
+; 16x to use VMLA.i8, same as mla_i8_i32 with multiple uses of the ext `add(mul(x, x))`
 define i32 @mla_i8_i32_multiuse(i8* nocapture readonly %x, i8* nocapture readonly %y, i32 %n) #0 {
 ; CHECK-LABEL: @mla_i8_i32_multiuse(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP9]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       vector.ph:
 ; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[N]], 15
 ; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16

llvm/unittests/Target/ARM/MachineInstrTest.cpp

auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VMLSLDAVs16:
     case MVE_VMLSLDAVs32:
     case MVE_VRMLALDAVHas32:
     case MVE_VRMLALDAVHau32:
     case MVE_VRMLALDAVHs32:
     case MVE_VRMLALDAVHu32:
     case MVE_VRMLSLDAVHas32:
     case MVE_VRMLSLDAVHs32:
-    case MVE_VMLAS_qr_s16:
-    case MVE_VMLAS_qr_s32:
-    case MVE_VMLAS_qr_s8:
-    case MVE_VMLAS_qr_u16:
-    case MVE_VMLAS_qr_u32:
-    case MVE_VMLAS_qr_u8:
-    case MVE_VMLA_qr_s16:
-    case MVE_VMLA_qr_s32:
-    case MVE_VMLA_qr_s8:
-    case MVE_VMLA_qr_u16:
-    case MVE_VMLA_qr_u32:
-    case MVE_VMLA_qr_u8:
+    case MVE_VMLAS_qr_i16:
+    case MVE_VMLAS_qr_i32:
+    case MVE_VMLAS_qr_i8:
+    case MVE_VMLA_qr_i16:
+    case MVE_VMLA_qr_i32:
+    case MVE_VMLA_qr_i8:
     case MVE_VHADD_qr_s16:
     case MVE_VHADD_qr_s32:
     case MVE_VHADD_qr_s8:
     case MVE_VHADD_qr_u16:
     case MVE_VHADD_qr_u32:
     case MVE_VHADD_qr_u8:
     case MVE_VHADDs16:
     case MVE_VHADDs32:
auto MVEVecSize = [](unsigned Opcode) {
     case MVE_VMINs8:
     case MVE_VMINu8:
     case MVE_VMLADAVas8:
     case MVE_VMLADAVau8:
     case MVE_VMLADAVaxs8:
     case MVE_VMLADAVs8:
     case MVE_VMLADAVu8:
     case MVE_VMLADAVxs8:
-    case MVE_VMLAS_qr_s8:
-    case MVE_VMLAS_qr_u8:
-    case MVE_VMLA_qr_s8:
-    case MVE_VMLA_qr_u8:
+    case MVE_VMLAS_qr_i8:
+    case MVE_VMLA_qr_i8:
     case MVE_VMLSDAVas8:
     case MVE_VMLSDAVaxs8:
     case MVE_VMLSDAVs8:
     case MVE_VMLSDAVxs8:
     case MVE_VMOV_from_lane_s8:
     case MVE_VMOV_from_lane_u8:
     case MVE_VMOV_to_lane_8:
     case MVE_VMOVimmi8:
auto MVEVecSize = [](unsigned Opcode) {
     case MVE_VMLADAVu16:
     case MVE_VMLADAVxs16:
     case MVE_VMLALDAVas16:
     case MVE_VMLALDAVau16:
     case MVE_VMLALDAVaxs16:
     case MVE_VMLALDAVs16:
     case MVE_VMLALDAVu16:
     case MVE_VMLALDAVxs16:
-    case MVE_VMLAS_qr_s16:
-    case MVE_VMLAS_qr_u16:
-    case MVE_VMLA_qr_s16:
-    case MVE_VMLA_qr_u16:
+    case MVE_VMLAS_qr_i16:
+    case MVE_VMLA_qr_i16:
     case MVE_VMLSDAVas16:
     case MVE_VMLSDAVaxs16:
     case MVE_VMLSDAVs16:
     case MVE_VMLSDAVxs16:
     case MVE_VMLSLDAVas16:
     case MVE_VMLSLDAVaxs16:
     case MVE_VMLSLDAVs16:
     case MVE_VMLSLDAVxs16:
auto MVEVecSize = [](unsigned Opcode) {
     case MVE_VMLADAVu32:
     case MVE_VMLADAVxs32:
     case MVE_VMLALDAVas32:
     case MVE_VMLALDAVau32:
     case MVE_VMLALDAVaxs32:
     case MVE_VMLALDAVs32:
     case MVE_VMLALDAVu32:
     case MVE_VMLALDAVxs32:
-    case MVE_VMLAS_qr_s32:
-    case MVE_VMLAS_qr_u32:
-    case MVE_VMLA_qr_s32:
-    case MVE_VMLA_qr_u32:
+    case MVE_VMLAS_qr_i32:
+    case MVE_VMLA_qr_i32:
     case MVE_VMLSDAVas32:
     case MVE_VMLSDAVaxs32:
     case MVE_VMLSDAVs32:
     case MVE_VMLSDAVxs32:
     case MVE_VMLSLDAVas32:
     case MVE_VMLSLDAVaxs32:
     case MVE_VMLSLDAVs32:
     case MVE_VMLSLDAVxs32: