[AAch64] Don't treat SVE scalable extends as free widening instructions

[dmgreen]

Summary

The logic in isWideningInstruction handles instructions like uaddw and smull, where add(x, zext(y)) or mul(sext(x), sext(y)) can be converted to single instructions, making the extends free. This doesn't apply the same to SVE instructions though.
https://godbolt.org/z/695d3nhGd

(There are instructions like SMULLT/B, but they require top/bottom lane interleaving. That is similar to MVE instructions, which required a special pass to perform the lane interleaving).

This patch just bails out of the call to isWideningInstruction if the vector is scalable, getting a more accurate cost.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

1640

It seems that the implementation of isWideningInstruction is historically a bit NEON specific and although SVE2 adds similar instructions, they work a little bit different and LLVM doesn't currently make use of them.
It might make more sense to add this condition to isWideningInstruction instead and possibly add a FIXME to enable this in the future when LLVM does have support for it. What do you think?

[dmgreen]

Sounds OK to me. I've moved the check into isWideningInstruction and added a comment about SVE instruction variants.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

1570

It's probably better to use !useNeonVector(DstTy) for this, given that fixed-width SVE has the same issue.

You may want to add a similar test to llvm/test/Analysis/CostModel/AArch64/sve-fixed-length.ll for this as well.

[dmgreen]

Use useNeonVector instead of checking for scalable vectors. Fixed length SVE vectors is not something I ever remember about.

[sdesmalen]

Thanks @dmgreen, LGTM

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
   // A helper that returns a vector type from the given type. The number of
   // elements in type Ty determines the vector width.
   auto toVectorTy = [&](Type *ArgTy) {
     return VectorType::get(ArgTy->getScalarType(),
                            cast<VectorType>(DstTy)->getElementCount());
   };
 
   // Exit early if DstTy is not a vector type whose elements are at least
-  // 16-bits wide.
-  if (!DstTy->isVectorTy() || DstTy->getScalarSizeInBits() < 16)
+  // 16-bits wide. SVE doesn't generally have the same set of instructions to
+  // perform an extend with the add/sub/mul. There are SMULLB style
+  // instructions, but they operate on top/bottom, requiring some sort of lane
+  // interleaving to be used with zext/sext.
+  if (!useNeonVector(DstTy) || DstTy->getScalarSizeInBits() < 16)
     return false;
 
   // Determine if the operation has a widening variant. We consider both the
   // "long" (e.g., usubl) and "wide" (e.g., usubw) versions of the
   // instructions.
   //
   // TODO: Add additional widening operations (e.g., shl, etc.) once we
   //       verify that their extending operands are eliminated during code
InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
                                                  TTI::CastContextHint CCH,
                                                  TTI::TargetCostKind CostKind,
                                                  const Instruction *I) {
   int ISD = TLI->InstructionOpcodeToISD(Opcode);
   assert(ISD && "Invalid opcode");
 
   // If the cast is observable, and it is used by a widening instruction (e.g.,
   // uaddl, saddw, etc.), it may be free.
   if (I && I->hasOneUser()) {
     auto *SingleUser = cast<Instruction>(*I->user_begin());
     SmallVector<const Value *, 4> Operands(SingleUser->operand_values());
     if (isWideningInstruction(Dst, SingleUser->getOpcode(), Operands)) {
       // If the cast is the second operand, it is free. We will generate either
       // a "wide" or "long" version of the widening instruction.
       if (I == SingleUser->getOperand(1))
         return 0;
       // If the cast is not the second operand, it will be free if it looks the

llvm/test/Analysis/CostModel/AArch64/sve-widening-instruction.ll

;
   %in1.ext = zext <vscale x 4 x i16> %in2 to <vscale x 4 x i32>
   %in2.ext = zext <vscale x 4 x i16> %in2 to <vscale x 4 x i32>
   %in.add = add <vscale x 4 x i32> %in1.ext, %in2.ext
   ret <vscale x 4 x i32> %in.add
 }
 
 define <vscale x 8 x i32> @widening_nxv8i16(<vscale x 8 x i16> %in1, <vscale x 8 x i16> %in2) {
 ; CHECK-LABEL: 'widening_nxv8i16'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %in1.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %in2.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %in1.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %in2.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in.add = add <vscale x 8 x i32> %in1.ext, %in2.ext
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <vscale x 8 x i32> %in.add
 ;
   %in1.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
   %in2.ext = zext <vscale x 8 x i16> %in2 to <vscale x 8 x i32>
   %in.add = add <vscale x 8 x i32> %in1.ext, %in2.ext
   ret <vscale x 8 x i32> %in.add
 }
 
 define <8 x i32> @widening_v8i16_svevl2(<8 x i16> %in1, <8 x i16> %in2) vscale_range(2,16) {
 ; CHECK-LABEL: 'widening_v8i16_svevl2'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %in1.ext = zext <8 x i16> %in2 to <8 x i32>
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %in2.ext = zext <8 x i16> %in2 to <8 x i32>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in1.ext = zext <8 x i16> %in2 to <8 x i32>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %in2.ext = zext <8 x i16> %in2 to <8 x i32>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %in.add = add <8 x i32> %in1.ext, %in2.ext
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %in.add
 ;
   %in1.ext = zext <8 x i16> %in2 to <8 x i32>
   %in2.ext = zext <8 x i16> %in2 to <8 x i32>
   %in.add = add <8 x i32> %in1.ext, %in2.ext
   ret <8 x i32> %in.add
 }