[AArch64][SME]: Generate streaming-compatible code for int/fp select/vselect

[hassnaa-arm]

Summary

To generate code compatible to streaming mode:

• enable custom lowering for VSETCC, needed for (fp-vselect.ll, int-vselect.ll).

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

12918–12919

nit: This looks like it's breaking the 80-character line limit. Can you reformat this please?

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

114–115

Hmm, I don't think there is any value in adding tests for sizes > 256 bits, right? @select_v16f16 is already testing that we legalise larger types (> 128-bits) correctly. Perhaps you can just remove all tests >256 bits? For example, @select_v32f16, @select_v64f16, etc.

191–192

Same comment as above.

265–266

Same comment as above.

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll

104–105

Again, I think it's worth deleting all tests > 256 bits.

204–205

Same comment as above.

281–282

Same comment as above.

355–356

Same comment as above.

[hassnaa-arm]

Remove not needed test cases

[hassnaa-arm]

Add/remove test cases in the precursory patch.

[david-arm]

LGTM! Thanks for removing the tests. :)

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
   }
 }
 
 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
                                            SelectionDAG &DAG) const {
   if (Op.getValueType().isScalableVector())
     return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_MERGE_ZERO);
 
-  if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType()))
+  if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType(),
+                                   Subtarget->forceStreamingCompatibleSVE()))
     return LowerFixedLengthVectorSetccToSVE(Op, DAG);
 
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
   EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger();
   SDLoc dl(Op);
 

 }
 
 SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
     SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT InVT = Op.getOperand(0).getValueType();
   EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
 
-  assert(useSVEForFixedLengthVectorVT(InVT) &&
+  assert(InVT.isFixedLengthVector() && isTypeLegal(InVT) &&
          "Only expected to lower fixed length vector operation!");
   assert(Op.getValueType() == InVT.changeTypeToInteger() &&
          "Expected integer result of the same bit length as the inputs!");
 
   auto Op1 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(0));
   auto Op2 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(1));
   auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
 

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

; CHECK-NEXT:    ret
   ret <8 x half> %sel
 }
 
 define void @select_v16f16(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    fcmeq v5.8h, v3.8h, v0.8h
-; CHECK-NEXT:    fcmeq v4.8h, v2.8h, v1.8h
-; CHECK-NEXT:    ldr q6, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    eor z4.d, z4.d, z6.d
-; CHECK-NEXT:    eor z6.d, z5.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z6.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI3_0]
+; CHECK-NEXT:    fcmeq p1.h, p0/z, z2.h, z1.h
+; CHECK-NEXT:    fcmeq p0.h, p0/z, z3.h, z0.h
+; CHECK-NEXT:    mov z5.h, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.h, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    and z2.d, z2.d, z5.d
+; CHECK-NEXT:    eor z5.d, z5.d, z4.d
+; CHECK-NEXT:    eor z4.d, z6.d, z4.d
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z3.d, z0.d
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x half>, ptr %a
   %op2 = load <16 x half>, ptr %b
   %mask = fcmp oeq <16 x half> %op1, %op2
   %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2
   store <16 x half> %sel, ptr %a
   ret void
 }
 
 define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT:    ret
   ret <4 x float> %sel
 }
 
 define void @select_v8f32(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI6_0
+; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    fcmeq v5.4s, v3.4s, v0.4s
-; CHECK-NEXT:    fcmeq v4.4s, v2.4s, v1.4s
-; CHECK-NEXT:    ldr q6, [x8, :lo12:.LCPI6_0]
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    eor z4.d, z4.d, z6.d
-; CHECK-NEXT:    eor z6.d, z5.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z6.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT:    fcmeq p1.s, p0/z, z2.s, z1.s
+; CHECK-NEXT:    fcmeq p0.s, p0/z, z3.s, z0.s
+; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.s, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    and z2.d, z2.d, z5.d
+; CHECK-NEXT:    eor z5.d, z5.d, z4.d
+; CHECK-NEXT:    eor z4.d, z6.d, z4.d
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z3.d, z0.d
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x float>, ptr %a
   %op2 = load <8 x float>, ptr %b
   %mask = fcmp oeq <8 x float> %op1, %op2
   %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2
   store <8 x float> %sel, ptr %a
   ret void
 }
 
 define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    mov x9, #-1
 ; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fmov d3, x9
; CHECK-NEXT:    ret
   ret <2 x double> %sel
 }
 
 define void @select_v4f64(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v4f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldp q0, q1, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI9_0
+; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    fcmeq v5.2d, v3.2d, v0.2d
-; CHECK-NEXT:    fcmeq v4.2d, v2.2d, v1.2d
-; CHECK-NEXT:    ldr q6, [x8, :lo12:.LCPI9_0]
-; CHECK-NEXT:    and z3.d, z3.d, z5.d
-; CHECK-NEXT:    and z2.d, z2.d, z4.d
-; CHECK-NEXT:    eor z4.d, z4.d, z6.d
-; CHECK-NEXT:    eor z6.d, z5.d, z6.d
-; CHECK-NEXT:    and z1.d, z1.d, z4.d
-; CHECK-NEXT:    and z0.d, z0.d, z6.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
+; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI9_0]
+; CHECK-NEXT:    fcmeq p1.d, p0/z, z2.d, z1.d
+; CHECK-NEXT:    fcmeq p0.d, p0/z, z3.d, z0.d
+; CHECK-NEXT:    mov z5.d, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.d, p0/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    and z2.d, z2.d, z5.d
+; CHECK-NEXT:    eor z5.d, z5.d, z4.d
+; CHECK-NEXT:    eor z4.d, z6.d, z4.d
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z0.d, z0.d, z4.d
+; CHECK-NEXT:    and z1.d, z1.d, z5.d
 ; CHECK-NEXT:    orr z0.d, z3.d, z0.d
+; CHECK-NEXT:    orr z1.d, z2.d, z1.d
 ; CHECK-NEXT:    stp q0, q1, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x double>, ptr %a
   %op2 = load <4 x double>, ptr %b
   %mask = fcmp oeq <4 x double> %op1, %op2
   %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2
   store <4 x double> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll

 ; CHECK-NEXT:    ret
   %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2
   ret <16 x i8> %sel
 }
 
 define void @select_v32i8(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v32i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
+; CHECK-NEXT:    ldp q1, q0, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    ptrue p0.b, vl16
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    cmeq v6.16b, v3.16b, v0.16b
 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    cmeq v5.16b, v2.16b, v1.16b
+; CHECK-NEXT:    cmpeq p1.b, p0/z, z2.b, z0.b
+; CHECK-NEXT:    cmpeq p0.b, p0/z, z3.b, z1.b
+; CHECK-NEXT:    mov z5.b, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.b, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    eor z5.d, z5.d, z4.d
 ; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
+; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <32 x i8>, ptr %a
   %op2 = load <32 x i8>, ptr %b
   %mask = icmp eq <32 x i8> %op1, %op2
   %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2
   store <32 x i8> %sel, ptr %a
   ret void
 }
 
 define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI4_0
 ; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0

 ; CHECK-NEXT:    ret
   %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2
   ret <8 x i16> %sel
 }
 
 define void @select_v16i16(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v16i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
+; CHECK-NEXT:    ldp q1, q0, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI7_0
+; CHECK-NEXT:    ptrue p0.h, vl8
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    cmeq v6.8h, v3.8h, v0.8h
 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI7_0]
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    cmeq v5.8h, v2.8h, v1.8h
+; CHECK-NEXT:    cmpeq p1.h, p0/z, z2.h, z0.h
+; CHECK-NEXT:    cmpeq p0.h, p0/z, z3.h, z1.h
+; CHECK-NEXT:    mov z5.h, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.h, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    eor z5.d, z5.d, z4.d
 ; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
+; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <16 x i16>, ptr %a
   %op2 = load <16 x i16>, ptr %b
   %mask = icmp eq <16 x i16> %op1, %op2
   %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2
   store <16 x i16> %sel, ptr %a
   ret void
 }
 
 define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI8_0
 ; CHECK-NEXT:    adrp x9, .LCPI8_1
 ; CHECK-NEXT:    // kill: def $d2 killed $d2 def $z2
 ; CHECK-NEXT:    ptrue p0.s, vl2
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0

 ; CHECK-NEXT:    ret
   %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2
   ret <4 x i32> %sel
 }
 
 define void @select_v8i32(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
+; CHECK-NEXT:    ldp q1, q0, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI10_0
+; CHECK-NEXT:    ptrue p0.s, vl4
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    cmeq v6.4s, v3.4s, v0.4s
 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI10_0]
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    cmeq v5.4s, v2.4s, v1.4s
+; CHECK-NEXT:    cmpeq p1.s, p0/z, z2.s, z0.s
+; CHECK-NEXT:    cmpeq p0.s, p0/z, z3.s, z1.s
+; CHECK-NEXT:    mov z5.s, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.s, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    eor z5.d, z5.d, z4.d
 ; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
+; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <8 x i32>, ptr %a
   %op2 = load <8 x i32>, ptr %b
   %mask = icmp eq <8 x i32> %op1, %op2
   %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2
   store <8 x i32> %sel, ptr %a
   ret void
 }
 
 define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
 ; CHECK-LABEL: select_v1i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    mov x9, #-1
 ; CHECK-NEXT:    csetm x8, ne
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $z1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
 ; CHECK-NEXT:    fmov d3, x9

 ; CHECK-NEXT:    ret
   %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2
   ret <2 x i64> %sel
 }
 
 define void @select_v4i64(ptr %a, ptr %b) #0 {
 ; CHECK-LABEL: select_v4i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldp q0, q1, [x1]
+; CHECK-NEXT:    ldp q1, q0, [x1]
 ; CHECK-NEXT:    adrp x8, .LCPI13_0
+; CHECK-NEXT:    ptrue p0.d, vl2
 ; CHECK-NEXT:    ldp q3, q2, [x0]
-; CHECK-NEXT:    cmeq v6.2d, v3.2d, v0.2d
 ; CHECK-NEXT:    ldr q4, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT:    and z3.d, z3.d, z6.d
-; CHECK-NEXT:    cmeq v5.2d, v2.2d, v1.2d
+; CHECK-NEXT:    cmpeq p1.d, p0/z, z2.d, z0.d
+; CHECK-NEXT:    cmpeq p0.d, p0/z, z3.d, z1.d
+; CHECK-NEXT:    mov z5.d, p1/z, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov z6.d, p0/z, #-1 // =0xffffffffffffffff
 ; CHECK-NEXT:    and z2.d, z2.d, z5.d
 ; CHECK-NEXT:    eor z5.d, z5.d, z4.d
 ; CHECK-NEXT:    eor z4.d, z6.d, z4.d
-; CHECK-NEXT:    and z1.d, z1.d, z5.d
-; CHECK-NEXT:    and z0.d, z0.d, z4.d
-; CHECK-NEXT:    orr z1.d, z2.d, z1.d
-; CHECK-NEXT:    orr z0.d, z3.d, z0.d
-; CHECK-NEXT:    stp q0, q1, [x0]
+; CHECK-NEXT:    and z3.d, z3.d, z6.d
+; CHECK-NEXT:    and z1.d, z1.d, z4.d
+; CHECK-NEXT:    and z0.d, z0.d, z5.d
+; CHECK-NEXT:    orr z1.d, z3.d, z1.d
+; CHECK-NEXT:    orr z0.d, z2.d, z0.d
+; CHECK-NEXT:    stp q1, q0, [x0]
 ; CHECK-NEXT:    ret
   %op1 = load <4 x i64>, ptr %a
   %op2 = load <4 x i64>, ptr %b
   %mask = icmp eq <4 x i64> %op1, %op2
   %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2
   store <4 x i64> %sel, ptr %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" uwtable }