[WebAssembly] Update relaxed-simd instruction names

[tlively]

Summary

Including builtin and intrinsic names. These should be the final names for the
proposal.
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md

[maratyszcza]

clang/include/clang/Basic/BuiltinsWebAssembly.def

180

Typo?

[tlively]

clang/include/clang/Basic/BuiltinsWebAssembly.def

180

Yep, thanks.

[tlively]

• Fix type

[maratyszcza]

Intrinsic naming LGTM. Not qualified to review the rest.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4iV4i", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4, "V4iV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
 
 // Relaxed SIMD builtins (experimental)
-TARGET_BUILTIN(__builtin_wasm_fma_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_fms_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_fma_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_fms_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
-
-TARGET_BUILTIN(__builtin_wasm_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_madd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_nmadd_f64x2, "V2dV2dV2dV2d", "nc", "relaxed-simd")
+
+TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i16x8, "V8sV8sV8sV8s", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_laneselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_swizzle_i8x16, "V16ScV16ScV16Sc", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_max_f32x4, "V4fV4fV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_s_i32x4_f32x4, "V4iV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_i32x4_f32x4, "V4UiV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_s_zero_i32x4_f64x2, "V4iV2d", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2, "V4UiV2d", "nc", "relaxed-simd")
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_q15mulr_s_i16x8, "V8sV8sV8s", "nc", "relaxed-simd")
 
-TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f", "nc", "relaxed-simd")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

while (OpIdx < 18) {
       Optional<llvm::APSInt> LaneConst =
           E->getArg(OpIdx)->getIntegerConstantExpr(getContext());
       assert(LaneConst && "Constant arg isn't actually constant?");
       Ops[OpIdx++] = llvm::ConstantInt::get(getLLVMContext(), *LaneConst);
     }
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle);
     return Builder.CreateCall(Callee, Ops);
   }
-  case WebAssembly::BI__builtin_wasm_fma_f32x4:
-  case WebAssembly::BI__builtin_wasm_fms_f32x4:
-  case WebAssembly::BI__builtin_wasm_fma_f64x2:
-  case WebAssembly::BI__builtin_wasm_fms_f64x2: {
+  case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2:
+  case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f64x2: {
     Value *A = EmitScalarExpr(E->getArg(0));
     Value *B = EmitScalarExpr(E->getArg(1));
     Value *C = EmitScalarExpr(E->getArg(2));
     unsigned IntNo;
     switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_fma_f32x4:
-    case WebAssembly::BI__builtin_wasm_fma_f64x2:
-      IntNo = Intrinsic::wasm_fma;
-      break;
-    case WebAssembly::BI__builtin_wasm_fms_f32x4:
-    case WebAssembly::BI__builtin_wasm_fms_f64x2:
-      IntNo = Intrinsic::wasm_fms;
+    case WebAssembly::BI__builtin_wasm_relaxed_madd_f32x4:
+    case WebAssembly::BI__builtin_wasm_relaxed_madd_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_madd;
+      break;
+    case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f32x4:
+    case WebAssembly::BI__builtin_wasm_relaxed_nmadd_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_nmadd;
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
     }
     Function *Callee = CGM.getIntrinsic(IntNo, A->getType());
     return Builder.CreateCall(Callee, {A, B, C});
   }
-  case WebAssembly::BI__builtin_wasm_laneselect_i8x16:
-  case WebAssembly::BI__builtin_wasm_laneselect_i16x8:
-  case WebAssembly::BI__builtin_wasm_laneselect_i32x4:
-  case WebAssembly::BI__builtin_wasm_laneselect_i64x2: {
+  case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i8x16:
+  case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i16x8:
+  case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i32x4:
+  case WebAssembly::BI__builtin_wasm_relaxed_laneselect_i64x2: {
     Value *A = EmitScalarExpr(E->getArg(0));
     Value *B = EmitScalarExpr(E->getArg(1));
     Value *C = EmitScalarExpr(E->getArg(2));
     Function *Callee =
-        CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
+        CGM.getIntrinsic(Intrinsic::wasm_relaxed_laneselect, A->getType());
     return Builder.CreateCall(Callee, {A, B, C});
   }
   case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: {
     Value *Src = EmitScalarExpr(E->getArg(0));
     Value *Indices = EmitScalarExpr(E->getArg(1));
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_swizzle);
     return Builder.CreateCall(Callee, {Src, Indices});
   }
case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2: {
     return Builder.CreateCall(Callee, {Vec});
   }
   case WebAssembly::BI__builtin_wasm_relaxed_q15mulr_s_i16x8: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_q15mulr_signed);
     return Builder.CreateCall(Callee, {LHS, RHS});
   }
-  case WebAssembly::BI__builtin_wasm_dot_i8x16_i7x16_s_i16x8: {
+  case WebAssembly::BI__builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
-    Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_dot_i8x16_i7x16_signed);
+    Function *Callee =
+        CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_i8x16_i7x16_signed);
     return Builder.CreateCall(Callee, {LHS, RHS});
   }
-  case WebAssembly::BI__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4: {
+  case WebAssembly::BI__builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
     Value *Acc = EmitScalarExpr(E->getArg(2));
     Function *Callee =
-        CGM.getIntrinsic(Intrinsic::wasm_dot_i8x16_i7x16_add_signed);
+        CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_i8x16_i7x16_add_signed);
     return Builder.CreateCall(Callee, {LHS, RHS, Acc});
   }
   case WebAssembly::BI__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
     Value *Acc = EmitScalarExpr(E->getArg(2));
     Function *Callee =
         CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_bf16x8_add_f32);

clang/test/CodeGen/builtins-wasm.c

return __builtin_wasm_shuffle_i8x16(x, y, 0, 1, 2, 3, 4, 5, 6, 7,
                                       8, 9, 10, 11, 12, 13, 14, 15);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
   // WEBASSEMBLY-SAME: i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
   // WEBASSEMBLY-SAME: i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14,
   // WEBASSEMBLY-SAME: i32 15
   // WEBASSEMBLY-NEXT: ret
 }
 
-f32x4 fma_f32x4(f32x4 a, f32x4 b, f32x4 c) {
-  return __builtin_wasm_fma_f32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x float> @llvm.wasm.fma.v4f32(
+f32x4 madd_f32x4(f32x4 a, f32x4 b, f32x4 c) {
+  return __builtin_wasm_relaxed_madd_f32x4(a, b, c);
+  // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.madd.v4f32(
   // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
-f32x4 fms_f32x4(f32x4 a, f32x4 b, f32x4 c) {
-  return __builtin_wasm_fms_f32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x float> @llvm.wasm.fms.v4f32(
+f32x4 nmadd_f32x4(f32x4 a, f32x4 b, f32x4 c) {
+  return __builtin_wasm_relaxed_nmadd_f32x4(a, b, c);
+  // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(
   // WEBASSEMBLY-SAME: <4 x float> %a, <4 x float> %b, <4 x float> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
-f64x2 fma_f64x2(f64x2 a, f64x2 b, f64x2 c) {
-  return __builtin_wasm_fma_f64x2(a, b, c);
-  // WEBASSEMBLY: call <2 x double> @llvm.wasm.fma.v2f64(
+f64x2 madd_f64x2(f64x2 a, f64x2 b, f64x2 c) {
+  return __builtin_wasm_relaxed_madd_f64x2(a, b, c);
+  // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.madd.v2f64(
   // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
-f64x2 fms_f64x2(f64x2 a, f64x2 b, f64x2 c) {
-  return __builtin_wasm_fms_f64x2(a, b, c);
-  // WEBASSEMBLY: call <2 x double> @llvm.wasm.fms.v2f64(
+f64x2 nmadd_f64x2(f64x2 a, f64x2 b, f64x2 c) {
+  return __builtin_wasm_relaxed_nmadd_f64x2(a, b, c);
+  // WEBASSEMBLY: call <2 x double> @llvm.wasm.relaxed.nmadd.v2f64(
   // WEBASSEMBLY-SAME: <2 x double> %a, <2 x double> %b, <2 x double> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 laneselect_i8x16(i8x16 a, i8x16 b, i8x16 c) {
-  return __builtin_wasm_laneselect_i8x16(a, b, c);
-  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.laneselect.v16i8(
+  return __builtin_wasm_relaxed_laneselect_i8x16(a, b, c);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i16x8 laneselect_i16x8(i16x8 a, i16x8 b, i16x8 c) {
-  return __builtin_wasm_laneselect_i16x8(a, b, c);
-  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.laneselect.v8i16(
+  return __builtin_wasm_relaxed_laneselect_i16x8(a, b, c);
+  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i32x4 laneselect_i32x4(i32x4 a, i32x4 b, i32x4 c) {
-  return __builtin_wasm_laneselect_i32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.laneselect.v4i32(
+  return __builtin_wasm_relaxed_laneselect_i32x4(a, b, c);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(
   // WEBASSEMBLY-SAME: <4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i64x2 laneselect_i64x2(i64x2 a, i64x2 b, i64x2 c) {
-  return __builtin_wasm_laneselect_i64x2(a, b, c);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.laneselect.v2i64(
+  return __builtin_wasm_relaxed_laneselect_i64x2(a, b, c);
+  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
   return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
 }

 i16x8 relaxed_q15mulr_s_i16x8(i16x8 a, i16x8 b) {
   return __builtin_wasm_relaxed_q15mulr_s_i16x8(a, b);
   // WEBASSEMBLY: call <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(
   // WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i16x8 dot_i8x16_i7x16_s_i16x8(i8x16 a, i8x16 b) {
-  return __builtin_wasm_dot_i8x16_i7x16_s_i16x8(a, b);
-  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(
+  return __builtin_wasm_relaxed_dot_i8x16_i7x16_s_i16x8(a, b);
+  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(
   // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i32x4 dot_i8x16_i7x16_add_s_i32x4(i8x16 a, i8x16 b, i32x4 c) {
-  return __builtin_wasm_dot_i8x16_i7x16_add_s_i32x4(a, b, c);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(
+  return __builtin_wasm_relaxed_dot_i8x16_i7x16_add_s_i32x4(a, b, c);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(
   // WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <4 x i32> %c)
   // WEBASSEMBLY-NEXT: ret
 }
 
 f32x4 relaxed_dot_bf16x8_add_f32_f32x4(u16x8 a, u16x8 b, f32x4 c) {
   return __builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4(a, b, c);
   // WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32
   // WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b, <4 x float> %c)
   // WEBASSEMBLY-NEXT: ret
 }

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

def int_wasm_extadd_pairwise_unsigned :
   DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                         [LLVMSubdivide2VectorType<0>],
                         [IntrNoMem, IntrSpeculatable]>;
 
 //===----------------------------------------------------------------------===//
 // Relaxed SIMD intrinsics (experimental)
 //===----------------------------------------------------------------------===//
 
-def int_wasm_fma :
+def int_wasm_relaxed_madd :
   DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
                         [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_fms :
+def int_wasm_relaxed_nmadd :
   DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
                         [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_laneselect :
+def int_wasm_relaxed_laneselect :
   DefaultAttrsIntrinsic<[llvm_anyvector_ty],
                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
                         [IntrNoMem, IntrSpeculatable]>;
 
 def int_wasm_relaxed_swizzle :
   DefaultAttrsIntrinsic<[llvm_v16i8_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty],
                         [IntrNoMem, IntrSpeculatable]>;
DefaultAttrsIntrinsic<[llvm_v4i32_ty],
                         [llvm_v2f64_ty],
                         [IntrNoMem, IntrSpeculatable]>;
 
 def int_wasm_relaxed_q15mulr_signed:
   DefaultAttrsIntrinsic<[llvm_v8i16_ty],
                         [llvm_v8i16_ty, llvm_v8i16_ty],
                         [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_dot_i8x16_i7x16_signed:
+def int_wasm_relaxed_dot_i8x16_i7x16_signed:
   DefaultAttrsIntrinsic<[llvm_v8i16_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty],
                         [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_dot_i8x16_i7x16_add_signed:
+def int_wasm_relaxed_dot_i8x16_i7x16_add_signed:
   DefaultAttrsIntrinsic<[llvm_v4i32_ty],
                         [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
                         [IntrNoMem, IntrSpeculatable]>;
 
 def int_wasm_relaxed_dot_bf16x8_add_f32:
   DefaultAttrsIntrinsic<[llvm_v4f32_ty],
                         [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4f32_ty],
                         [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 defm "" : RelaxedConvert<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned,
                          "relaxed_trunc_f32x4_u", 0x102>;
 defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero,
                          "relaxed_trunc_f64x2_s_zero", 0x103>;
 defm "" : RelaxedConvert<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero,
                          "relaxed_trunc_f64x2_u_zero", 0x104>;
 
 //===----------------------------------------------------------------------===//
-// Relaxed Fused Multiply- Add and Subtract (FMA/FMS)
+// Relaxed (Negative) Multiply-Add  (madd/nmadd)
 //===----------------------------------------------------------------------===//
 
-multiclass SIMDFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
-  defm FMA_#vec :
+multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS> {
+  defm MADD_#vec :
     RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
-              [(set (vec.vt V128:$dst), (int_wasm_fma
+              [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd
                 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
-              vec.prefix#".relaxed_fma\t$dst, $a, $b, $c",
-              vec.prefix#".relaxed_fma", simdopA>;
-  defm FMS_#vec :
+              vec.prefix#".relaxed_madd\t$dst, $a, $b, $c",
+              vec.prefix#".relaxed_madd", simdopA>;
+  defm NMADD_#vec :
     RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
-              [(set (vec.vt V128:$dst), (int_wasm_fms
+              [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd
                 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
-              vec.prefix#".relaxed_fms\t$dst, $a, $b, $c",
-              vec.prefix#".relaxed_fms", simdopS>;
+              vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c",
+              vec.prefix#".relaxed_nmadd", simdopS>;
 }
 
-defm "" : SIMDFM<F32x4, 0x105, 0x106>;
-defm "" : SIMDFM<F64x2, 0x107, 0x108>;
+defm "" : SIMDMADD<F32x4, 0x105, 0x106>;
+defm "" : SIMDMADD<F64x2, 0x107, 0x108>;
 
 //===----------------------------------------------------------------------===//
 // Laneselect
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
   defm LANESELECT_#vec :
     RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), (outs), (ins),
-              [(set (vec.vt V128:$dst), (int_wasm_laneselect
+              [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect
                 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
               vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
               vec.prefix#".relaxed_laneselect", op>;
 }
 
 defm "" : SIMDLANESELECT<I8x16, 0x109>;
 defm "" : SIMDLANESELECT<I16x8, 0x10a>;
 defm "" : SIMDLANESELECT<I32x4, 0x10b>;
RelaxedBinary<I16x8, int_wasm_relaxed_q15mulr_signed, "relaxed_q15mulr_s",
                 0x111>;
 
 //===----------------------------------------------------------------------===//
 // Relaxed integer dot product
 //===----------------------------------------------------------------------===//
 
 defm RELAXED_DOT :
   RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
-            [(set (v8i16 V128:$dst), (int_wasm_dot_i8x16_i7x16_signed
+            [(set (v8i16 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_signed
                (v16i8 V128:$lhs), (v16i8 V128:$rhs)))],
-            "i16x8.dot_i8x16_i7x16_s\t$dst, $lhs, $rhs",
-            "i16x8.dot_i8x16_i7x16_s", 0x112>;
+            "i16x8.relaxed_dot_i8x16_i7x16_s\t$dst, $lhs, $rhs",
+            "i16x8.relaxed_dot_i8x16_i7x16_s", 0x112>;
 
 defm RELAXED_DOT_ADD :
   RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc),
             (outs), (ins),
-            [(set (v4i32 V128:$dst), (int_wasm_dot_i8x16_i7x16_add_signed
+            [(set (v4i32 V128:$dst), (int_wasm_relaxed_dot_i8x16_i7x16_add_signed
                (v16i8 V128:$lhs), (v16i8 V128:$rhs), (v4i32 V128:$acc)))],
-            "i32x4.dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc",
-            "i32x4.dot_i8x16_i7x16_add_s", 0x113>;
+            "i32x4.relaxed_dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc",
+            "i32x4.relaxed_dot_i8x16_i7x16_add_s", 0x113>;
 
 //===----------------------------------------------------------------------===//
 // Relaxed BFloat16 dot product
 //===----------------------------------------------------------------------===//
 
 defm RELAXED_DOT_BFLOAT :
   RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc),
             (outs), (ins),
             [(set (v4f32 V128:$dst), (int_wasm_relaxed_dot_bf16x8_add_f32
                (v8i16 V128:$lhs), (v8i16 V128:$rhs), (v4f32 V128:$acc)))],
             "f32x4.relaxed_dot_bf16x8_add_f32\t$dst, $lhs, $rhs, $acc",
             "f32x4.relaxed_dot_bf16x8_add_f32", 0x114>;

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

%res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
       i32 undef, i32 undef, i32 undef, i32 2)
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: laneselect_v16i8:
 ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
-  %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
+  %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(
     <16 x i8> %a, <16 x i8> %b, <16 x i8> %c
   )
   ret <16 x i8> %v
 }
 
 ; CHECK-LABEL: relaxed_swizzle_v16i8:
 ; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
define <8 x i16> @narrow_unsigned_v8i16(<4 x i32> %low, <4 x i32> %high) {
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: laneselect_v8i16:
 ; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
-  %v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
+  %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(
     <8 x i16> %a, <8 x i16> %b, <8 x i16> %c
   )
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: relaxed_q15mulr_s_i16x8:
 ; CHECK-NEXT: .functype relaxed_q15mulr_s_i16x8 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.relaxed_q15mulr_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(<8 x i16>, <8 x i16>)
 define <8 x i16> @relaxed_q15mulr_s_i16x8(<8 x i16> %a, <8 x i16> %b) {
   %v = call <8 x i16> @llvm.wasm.relaxed.q15mulr.signed(
     <8 x i16> %a, <8 x i16> %b
   )
   ret <8 x i16> %v
 }
 
 ; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8:
 ; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
 define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) {
-  %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(
+  %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(
     <16 x i8> %a, <16 x i8> %b
   )
   ret <8 x i16> %v
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) {
   %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: laneselect_v4i32:
 ; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-  %v = call <4 x i32> @llvm.wasm.laneselect.v4i32(
+  %v = call <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(
     <4 x i32> %a, <4 x i32> %b, <4 x i32> %c
   )
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: relaxed_trunc_s:
 ; NO-CHECK-NOT: f32x4
 ; CHECK-NEXT: .functype relaxed_trunc_s (v128) -> (v128){{$}}

 declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double>)
 define <4 x i32> @relaxed_trunc_u_zero(<2 x double> %x) {
   %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: dot_i8x16_i7x16_add_s_i32x4:
 ; CHECK-NEXT: .functype dot_i8x16_i7x16_add_s_i32x4 (v128, v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i32x4.dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: i32x4.relaxed_dot_i8x16_i7x16_add_s $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(<16 x i8>, <16 x i8>,
-                                                        <4 x i32>)
+declare <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(
+  <16 x i8>, <16 x i8>, <4 x i32>)
 define <4 x i32> @dot_i8x16_i7x16_add_s_i32x4(<16 x i8> %a, <16 x i8> %b,
                                               <4 x i32> %c) {
-  %v = call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(
+  %v = call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(
     <16 x i8> %a, <16 x i8> %b, <4 x i32> %c
   )
   ret <4 x i32> %v
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
   )
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: laneselect_v2i64:
 ; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64x2.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
 define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
-  %v = call <2 x i64> @llvm.wasm.laneselect.v2i64(
+  %v = call <2 x i64> @llvm.wasm.relaxed.laneselect.v2i64(
     <2 x i64> %a, <2 x i64> %b, <2 x i64> %c
   )
   ret <2 x i64> %v
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================

 ; CHECK-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>)
 define <4 x float> @nearest_v4f32(<4 x float> %a) {
   %v = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)
   ret <4 x float> %v
 }
 
-; CHECK-LABEL: fma_v4f32:
-; CHECK-NEXT: .functype fma_v4f32 (v128, v128, v128) -> (v128){{$}}
-; CHECK-NEXT: f32x4.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
-define <4 x float> @fma_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
-  %v = call <4 x float> @llvm.wasm.fma.v4f32(
+; CHECK-LABEL: madd_v4f32:
+; CHECK-NEXT: .functype madd_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.madd.v4f32(<4 x float>, <4 x float>, <4 x float>)
+define <4 x float> @madd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
+  %v = call <4 x float> @llvm.wasm.relaxed.madd.v4f32(
     <4 x float> %a, <4 x float> %b, <4 x float> %c
   )
   ret <4 x float> %v
 }
 
-; CHECK-LABEL: fms_v4f32:
-; CHECK-NEXT: .functype fms_v4f32 (v128, v128, v128) -> (v128){{$}}
-; CHECK-NEXT: f32x4.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>)
-define <4 x float> @fms_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
-  %v = call <4 x float> @llvm.wasm.fms.v4f32(
+; CHECK-LABEL: nmadd_v4f32:
+; CHECK-NEXT: .functype nmadd_v4f32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(<4 x float>, <4 x float>, <4 x float>)
+define <4 x float> @nmadd_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
+  %v = call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(
     <4 x float> %a, <4 x float> %b, <4 x float> %c
   )
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: relaxed_min_v4f32:
 ; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}

 ; CHECK-NEXT: f64x2.nearest $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)
 define <2 x double> @nearest_v2f64(<2 x double> %a) {
   %v = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a)
   ret <2 x double> %v
 }
 
-; CHECK-LABEL: fma_v2f64:
-; CHECK-NEXT: .functype fma_v2f64 (v128, v128, v128) -> (v128){{$}}
-; CHECK-NEXT: f64x2.relaxed_fma $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x double> @llvm.wasm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
-define <2 x double> @fma_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
-  %v = call <2 x double> @llvm.wasm.fma.v2f64(
+; CHECK-LABEL: madd_v2f64:
+; CHECK-NEXT: .functype madd_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_madd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.madd.v2f64(
+  <2 x double>, <2 x double>, <2 x double>)
+define <2 x double> @madd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
+  %v = call <2 x double> @llvm.wasm.relaxed.madd.v2f64(
     <2 x double> %a, <2 x double> %b, <2 x double> %c
   )
   ret <2 x double> %v
 }
 
-; CHECK-LABEL: fms_v2f64:
-; CHECK-NEXT: .functype fms_v2f64 (v128, v128, v128) -> (v128){{$}}
-; CHECK-NEXT: f64x2.relaxed_fms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x double> @llvm.wasm.fms.v2f64(<2 x double>, <2 x double>, <2 x double>)
-define <2 x double> @fms_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
-  %v = call <2 x double> @llvm.wasm.fms.v2f64(
+; CHECK-LABEL: nmadd_v2f64:
+; CHECK-NEXT: .functype nmadd_v2f64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_nmadd $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.nmadd.v2f64(
+  <2 x double>, <2 x double>, <2 x double>)
+define <2 x double> @nmadd_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
+  %v = call <2 x double> @llvm.wasm.relaxed.nmadd.v2f64(
     <2 x double> %a, <2 x double> %b, <2 x double> %c
   )
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: relaxed_min_v2f64:
 ; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i32x4.relaxed_trunc_f32x4_u
 
     # CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0x83,0x02]
     i32x4.relaxed_trunc_f64x2_s_zero
 
     # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02]
     i32x4.relaxed_trunc_f64x2_u_zero
 
-    # CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02]
-    f32x4.relaxed_fma
+    # CHECK: f32x4.relaxed_madd # encoding: [0xfd,0x85,0x02]
+    f32x4.relaxed_madd
 
-    # CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02]
-    f32x4.relaxed_fms
+    # CHECK: f32x4.relaxed_nmadd # encoding: [0xfd,0x86,0x02]
+    f32x4.relaxed_nmadd
 
-    # CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02]
-    f64x2.relaxed_fma
+    # CHECK: f64x2.relaxed_madd # encoding: [0xfd,0x87,0x02]
+    f64x2.relaxed_madd
 
-    # CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02]
-    f64x2.relaxed_fms
+    # CHECK: f64x2.relaxed_nmadd # encoding: [0xfd,0x88,0x02]
+    f64x2.relaxed_nmadd
 
     # CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02]
     i8x16.relaxed_laneselect
 
     # CHECK: i16x8.relaxed_laneselect # encoding: [0xfd,0x8a,0x02]
     i16x8.relaxed_laneselect
 
     # CHECK: i32x4.relaxed_laneselect # encoding: [0xfd,0x8b,0x02]
main:
     f64x2.relaxed_min
 
     # CHECK: f64x2.relaxed_max # encoding: [0xfd,0x90,0x02]
     f64x2.relaxed_max
 
     # CHECK: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02]
     i16x8.relaxed_q15mulr_s
 
-    # CHECK: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
-    i16x8.dot_i8x16_i7x16_s
+    # CHECK: i16x8.relaxed_dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
+    i16x8.relaxed_dot_i8x16_i7x16_s
 
-    # CHECK: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
-    i32x4.dot_i8x16_i7x16_add_s
+    # CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
+    i32x4.relaxed_dot_i8x16_i7x16_add_s
 
     end_function