[RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval.

[craig.topper]

Summary

After D137970, we do the fixable instruction conversion in place
so we don't need to worry about iterator invalidation. This lets
us to conversion and updates in a single loop.

[reames]

LGTM once dependent patch is ready.

llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   const RISCVInstrInfo &TII = *ST.getInstrInfo();
 
   if (!ST.is64Bit())
     return false;
 
-  SmallPtrSet<MachineInstr *, 4> SExtWRemovalCands;
+  bool MadeChange = false;
 
-  // Replacing instructions invalidates the MI iterator
-  // we collect the candidates, then iterate over them separately.
   for (MachineBasicBlock &MBB : MF) {
     for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
       MachineInstr *MI = &*I++;
 
       // We're looking for the sext.w pattern ADDIW rd, rs1, 0.
       if (!RISCV::isSEXT_W(*MI))
         continue;
 
       // Input should be a virtual register.
       Register SrcReg = MI->getOperand(1).getReg();
       if (!SrcReg.isVirtual())
         continue;
 
-      SExtWRemovalCands.insert(MI);
-    }
-  }
-
-  bool MadeChange = false;
-  for (auto *MI : SExtWRemovalCands) {
       SmallPtrSet<MachineInstr *, 4> FixableDef;
-    Register SrcReg = MI->getOperand(1).getReg();
       MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
 
       // If all definitions reaching MI sign-extend their output,
       // then sext.w is redundant
       if (!isSignExtendedW(SrcMI, MRI, FixableDef))
         continue;
 
       Register DstReg = MI->getOperand(0).getReg();
       if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
         continue;
+
       // Convert Fixable instructions to their W versions.
       for (MachineInstr *Fixable : FixableDef) {
         LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
         Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
         Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
         Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
         Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
         LLVM_DEBUG(dbgs() << "     with " << *Fixable);
         ++NumTransformedToWInstrs;
       }
 
       LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
       MRI.replaceRegWith(DstReg, SrcReg);
       MRI.clearKillFlags(SrcReg);
       MI->eraseFromParent();
       ++NumRemovedSExtW;
       MadeChange = true;
     }
+  }
 
   return MadeChange;
 }