[RISCV] Transform fixable instruction in place in RISCVSExtWRemoval. NFC

[craig.topper]

Summary

Instead of creating a new instruction and copying operands, we can
use setDesc to convert in place.

[reames]

I'm not sure this is right. The problem is that the original instruction can have flags that indicate e.g. no-wrap or no-inf. Previously, those were implicitly dropped. After the transform, we have a different instruction semantic, are you sure those flags are always preserved? That seems like a non-obvious claim.

[craig.topper]

Clear the poison generating flags

[reames]

Under the assumption that only integer operations can reach this bit of code, LGTM

llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

 }
 
 bool RISCVSExtWRemoval::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()) || DisableSExtWRemoval)
     return false;
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
+  const RISCVInstrInfo &TII = *ST.getInstrInfo();
 
   if (!ST.is64Bit())
     return false;
 
   SmallPtrSet<MachineInstr *, 4> SExtWRemovalCands;
 
   // Replacing instructions invalidates the MI iterator
   // we collect the candidates, then iterate over them separately.
for (auto *MI : SExtWRemovalCands) {
     // If all definitions reaching MI sign-extend their output,
     // then sext.w is redundant
     if (!isSignExtendedW(SrcMI, MRI, FixableDef))
       continue;
 
     Register DstReg = MI->getOperand(0).getReg();
     if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
       continue;
-    // Replace Fixable instructions with their W versions.
+    // Convert Fixable instructions to their W versions.
     for (MachineInstr *Fixable : FixableDef) {
-      MachineBasicBlock &MBB = *Fixable->getParent();
-      const DebugLoc &DL = Fixable->getDebugLoc();
-      unsigned Code = getWOp(Fixable->getOpcode());
-      MachineInstrBuilder Replacement =
-          BuildMI(MBB, Fixable, DL, ST.getInstrInfo()->get(Code));
-      for (auto Op : Fixable->operands())
-        Replacement.add(Op);
-      for (auto *Op : Fixable->memoperands())
-        Replacement.addMemOperand(Op);
-
       LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
-      LLVM_DEBUG(dbgs() << "     with " << *Replacement);
-
-      Fixable->eraseFromParent();
+      Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
+      Fixable->clearFlag(MachineInstr::MIFlag::NoSWrap);
+      Fixable->clearFlag(MachineInstr::MIFlag::NoUWrap);
+      Fixable->clearFlag(MachineInstr::MIFlag::IsExact);
+      LLVM_DEBUG(dbgs() << "     with " << *Fixable);
       ++NumTransformedToWInstrs;
     }
 
     LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
     MRI.replaceRegWith(DstReg, SrcReg);
     MRI.clearKillFlags(SrcReg);
     MI->eraseFromParent();
     ++NumRemovedSExtW;
     MadeChange = true;
   }
 
   return MadeChange;
 }