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Differential D138024

[RISCV] Pre-commit test.
ClosedPublic

Authored by HanKuanChen on Nov 15 2022, 4:28 AM.

Details

Reviewers
craig.topper
reames
frasercrmck
Commits
rG2e58d4bc4b3f: [RISCV] Pre-commit test.

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Event Timeline

HanKuanChen created this revision.Nov 15 2022, 4:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 15 2022, 4:28 AM
Herald added subscribers: sunshaoce, VincentWu, vkmr and 27 others. · View Herald Transcript
HanKuanChen requested review of this revision.Nov 15 2022, 4:28 AM
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HanKuanChen updated this revision to Diff 475424.Nov 15 2022, 4:30 AM

Add reviewers.

HanKuanChen edited the summary of this revision. (Show Details)Nov 15 2022, 4:30 AM
HanKuanChen added reviewers: craig.topper, reames, frasercrmck.
Herald added a subscriber: StephenFan. · View Herald TranscriptNov 15 2022, 4:30 AM
HanKuanChen added a child revision: D138025: [RISCV] Make lowerVECTOR_SHUFFLEAsVSlidedown follow source until not EXTRACT_SUBVECTOR..Nov 15 2022, 4:32 AM
Harbormaster completed remote builds in B197734: Diff 475424.Nov 15 2022, 5:20 AM
craig.topper accepted this revision.Nov 16 2022, 8:54 PM

LGTM

This revision is now accepted and ready to land.Nov 16 2022, 8:54 PM
This revision was landed with ongoing or failed builds.Nov 17 2022, 10:33 PM
Closed by commit rG2e58d4bc4b3f: [RISCV] Pre-commit test. (authored by HanKuanChen). · Explain Why
This revision was automatically updated to reflect the committed changes.
HanKuanChen added a commit: rG2e58d4bc4b3f: [RISCV] Pre-commit test..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
21 lines

Diff 476338

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 633 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 5 ; CHECK-NEXT: vslidedown.vi v8, v8, 5
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, ma
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12> %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
ret <8 x i32> %s ret <8 x i32> %s
} }
define <4 x i16> @shuffle_shuffle_vslidedown(<16 x i16> %0) {
; CHECK-LABEL: shuffle_shuffle_vslidedown:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret
entry:
%1 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = shufflevector <16 x i16> %0, <16 x i16> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%3 = shufflevector <8 x i16> %1, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%4 = shufflevector <8 x i16> %2, <8 x i16> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%5 = shufflevector <4 x i16> %3, <4 x i16> %4, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
ret <4 x i16> %5
}