[mlir] Initial MLIR VP intrinsic integration test on host and RVV emulator.

[zhanghb97]

Summary

This patch adds the initial VP intrinsic integration test on the host backend and RVV emulator. Please see more detailed discussion on the discourse.

• Run the test cases on the host by configuring the CMake option: -DMLIR_INCLUDE_INTEGRATION_TESTS=ON
• Build the RVV environment and run the test cases on RVV QEMU by this doc.

[dcaballe]

Hey @aartbik, could you please help with the review? I think this should be similar to the integration tests for AMX.

[aartbik]

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

8

If you want to follow the previous taken convention, I would put this test (and the lit extension)
in a new directory

e.g we have

test/Integration/Dialect/Vector/CPU/ all vector tests
test/Integration/Dialect/Vector/CPU/AMX AMX specific tests
test/Integration/Dialect/Vector/CPU/ArmSVE ARM SVE specific tests

so it feels like you should move this really into

test/Integration/Dialect/Vector/CPU/RISCV

or at very best

test/Integration/Dialect/LLVMIR/CPU/RISCV

(but I fail to see why you would want it under LLVMIR?)

mlir/test/lit.site.cfg.py.in

40

move one up, this is closer under X86VECTOR than CUDA is

[zhanghb97]

Place MLIR_RUN_RISCV_VECTOR_TESTS option under X86VECTOR.

[zhanghb97]

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

8

Thanks for the suggestion!

it feels like you should move this really into test/Integration/Dialect/Vector/CPU/RISCV

The VP intrinsic operations are cross-platform, which means that we should test them on different SIMD/Vector backends (Intel AVX series, Arm Neon, RISC-V Vector, etc.), so I don't think we should move the cases into a backend-specific directory. This case can pass on the Intel AVX series and Arm Neon machine (I use Intel Xeon and AppleM1 for the test). As for the RVV side, there are no widely available RVV products now, so we should use an RVV emulator here.

I fail to see why you would want it under LLVMIR?

The VP intrinsic operations are defined in the LLVM dialect, so I write the test under LLVMIR.

In summary, I think the test/Integration/Dialect/LLVMIR/CPU/ is a suitable directory for the VP integration test. WDYT?

mlir/test/lit.site.cfg.py.in

40

Done.

[aartbik]

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

8

Many ops in the vector dialect lower to LLVM IR intrinsics (e.g. llvm.intr.vector.reduce.fadd), so by that reasoning, everything should be put under LLVM IR. I still feel this is really a test that belongs under Vector.

[aartbik]

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

8

On the other hand, I seem to have written tests like test-vector-reductions-int.mlir myself, so I can see you reasoning ;-)

[zhanghb97]

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

8

Yes, this is very similar to the vector reduction cases. It seems that there is no rule to explain where the test of vector-like LLVMOps should be placed. The current integration tests here are only for the VP intrinsic ops themselves. They do not extend to the lowering part from the Vector dialect. So I will land this patch first to place the cases under LLVMIR, and I am open to modifying the directory if the relevant rules are confirmed in future discussions.

mlir/test/Integration/Dialect/LLVMIR/CPU/lit.local.cfg

 import sys
 
 # No JIT on win32.
 if sys.platform == 'win32':
     config.unsupported = True
+
+lli_cmd = 'lli'
+if config.riscv_emulator_lli_executable:
+    lli_cmd = config.riscv_emulator_lli_executable
+
+config.substitutions.append(('%mlir_native_utils_lib_dir',
+    config.riscv_emulator_utils_lib_dir or config.mlir_lib_dir))
+
+if config.riscv_vector_emulator_executable:
+    # Run test in qemu emulator.
+    emulation_cmd = config.riscv_vector_emulator_executable
+    if config.riscv_vector_emulator_options:
+        emulation_cmd = emulation_cmd + ' ' + config.riscv_vector_emulator_options
+    emulation_cmd = emulation_cmd + ' ' + lli_cmd + ' --march=riscv64 -mattr=+v '
+    config.substitutions.append(('%lli', emulation_cmd))
+else:
+    config.substitutions.append(('%lli', lli_cmd))

mlir/test/Integration/Dialect/LLVMIR/CPU/test-vp-intrinsic.mlir

+// RUN: mlir-opt %s -convert-vector-to-llvm -convert-memref-to-llvm \
+// RUN:             -convert-func-to-llvm -reconcile-unrealized-casts | \
+// RUN: mlir-translate -mlir-to-llvmir | \
+// RUN: %lli --entry-function=entry \
+// RUN:      --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \
+// RUN: FileCheck %s
+
+memref.global "private" @gv_i32 : memref<20xi32> =
+    dense<[0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+           10, 11, 12, 13, 14, 15, 16, 17, 18, 19]>
+
+func.func @entry() -> i32 {
+  %c0 = arith.constant 0 : index
+  %c10 = arith.constant 10 : index
+  %mem_i32 = memref.get_global @gv_i32 : memref<20xi32>
+  // When the vectors are defined as dense constant vector,
+  // the vp intrinsic will be optimized/eliminated on some backend (e.g. X86).
+  // So this test case loads the vector from a memref to test the vp intrinsic
+  // backend support.
+  %vec1 = vector.load %mem_i32[%c0] : memref<20xi32>, vector<8xi32>
+  %vec2 = vector.load %mem_i32[%c10] : memref<20xi32>, vector<8xi32>
+  %mask = arith.constant dense<[1, 0, 1, 0, 1, 0, 1, 0]> : vector<8xi1>
+  %evl = arith.constant 4 : i32
+
+  %res = "llvm.intr.vp.add" (%vec1, %vec2, %mask, %evl) :
+         (vector<8xi32>, vector<8xi32>, vector<8xi1>, i32) -> vector<8xi32>
+  vector.print %res : vector<8xi32>
+  // CHECK: ( 10, {{.*}}, 14, {{.*}}, {{.*}}, {{.*}}, {{.*}}, {{.*}} )
+
+  %ret = arith.constant 0 : i32
+  return %ret : i32
+}

mlir/test/lit.site.cfg.py.in

 config.enable_spirv_cpu_runner = @MLIR_ENABLE_SPIRV_CPU_RUNNER@
 config.enable_vulkan_runner = @MLIR_ENABLE_VULKAN_RUNNER@
 config.enable_bindings_python = @MLIR_ENABLE_BINDINGS_PYTHON@
 config.intel_sde_executable = "@INTEL_SDE_EXECUTABLE@"
 config.mlir_run_amx_tests = @MLIR_RUN_AMX_TESTS@
 config.mlir_run_arm_sve_tests = @MLIR_RUN_ARM_SVE_TESTS@
 config.mlir_run_x86vector_tests = @MLIR_RUN_X86VECTOR_TESTS@
 config.mlir_run_cuda_tensor_core_tests = @MLIR_RUN_CUDA_TENSOR_CORE_TESTS@
+config.mlir_run_riscv_vector_tests = "@MLIR_RUN_RISCV_VECTOR_TESTS@"
 config.mlir_include_integration_tests = @MLIR_INCLUDE_INTEGRATION_TESTS@
 config.arm_emulator_executable = "@ARM_EMULATOR_EXECUTABLE@"
 config.arm_emulator_options = "@ARM_EMULATOR_OPTIONS@"
 config.arm_emulator_lli_executable = "@ARM_EMULATOR_LLI_EXECUTABLE@"
 config.arm_emulator_utils_lib_dir = "@ARM_EMULATOR_UTILS_LIB_DIR@"
+config.riscv_vector_emulator_executable = "@RISCV_VECTOR_EMULATOR_EXECUTABLE@"
+config.riscv_vector_emulator_options = "@RISCV_VECTOR_EMULATOR_OPTIONS@"
+config.riscv_emulator_lli_executable = "@RISCV_EMULATOR_LLI_EXECUTABLE@"
+config.riscv_emulator_utils_lib_dir = "@RISCV_EMULATOR_UTILS_LIB_DIR@"
 
 import lit.llvm
 lit.llvm.initialize(lit_config, config)
 
 # Let the main config do the real work.
 lit_config.load_config(config, "@MLIR_SOURCE_DIR@/test/lit.cfg.py")