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Differential D137734

[SME] Store buffer to the correct pointer when setting up lazy-save.
ClosedPublic

Authored by sdesmalen on Nov 9 2022, 1:05 PM.

Details

Reviewers
david-arm
kmclaughlin
aemerson
Commits
rG6f48e68d398d: [SME] Store buffer to the correct pointer when setting up lazy-save.
Summary

This fixes a bug in 'allocateLazySaveBuffer' that led to the
buffer pointer being stored to the wrong address.

Diff Detail

Unit TestsFailed

TimeTest
60,020 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test

Event Timeline

sdesmalen created this revision.Nov 9 2022, 1:05 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 9 2022, 1:05 PM
Herald added a subscriber: hiraditya. · View Herald Transcript
sdesmalen requested review of this revision.Nov 9 2022, 1:05 PM
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Harbormaster completed remote builds in B196943: Diff 474333.Nov 9 2022, 1:54 PM
david-arm accepted this revision.Nov 16 2022, 1:32 AM

LGTM!

This revision is now accepted and ready to land.Nov 16 2022, 1:32 AM
This revision was landed with ongoing or failed builds.Nov 16 2022, 8:38 AM
Closed by commit rG6f48e68d398d: [SME] Store buffer to the correct pointer when setting up lazy-save. (authored by sdesmalen). · Explain Why
This revision was automatically updated to reflect the committed changes.
sdesmalen added a commit: rG6f48e68d398d: [SME] Store buffer to the correct pointer when setting up lazy-save..

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
10 lines
test/
CodeGen/
AArch64/
6 lines
8 lines
4 lines

Diff 474333

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,003 Lines • ▼ Show 20 LinesAArch64TargetLowering::allocateLazySaveBuffer(SDValue &Chain, const SDLoc &DL,
// Allocate a lazy-save buffer object of size SVL.B * SVL.B (worst-case) // Allocate a lazy-save buffer object of size SVL.B * SVL.B (worst-case)
SDValue N = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64, SDValue N = DAG.getNode(AArch64ISD::RDSVL, DL, MVT::i64,
DAG.getConstant(1, DL, MVT::i32)); DAG.getConstant(1, DL, MVT::i32));
SDValue NN = DAG.getNode(ISD::MUL, DL, MVT::i64, N, N); SDValue NN = DAG.getNode(ISD::MUL, DL, MVT::i64, N, N);
SDValue Ops[] = {Chain, NN, DAG.getConstant(1, DL, MVT::i64)}; SDValue Ops[] = {Chain, NN, DAG.getConstant(1, DL, MVT::i64)};
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other); SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
SDValue Buffer = DAG.getNode(ISD::DYNAMIC_STACKALLOC, DL, VTs, Ops); SDValue Buffer = DAG.getNode(ISD::DYNAMIC_STACKALLOC, DL, VTs, Ops);
unsigned FI = MFI.CreateVariableSizedObject(Align(1), nullptr); Chain = Buffer.getValue(1);
Register Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); MFI.CreateVariableSizedObject(Align(1), nullptr);
Chain = DAG.getCopyToReg(Buffer.getValue(1), DL, Reg, Buffer.getValue(0));
// Allocate an additional TPIDR2 object on the stack (16 bytes) // Allocate an additional TPIDR2 object on the stack (16 bytes)
unsigned TPIDR2Obj = MFI.CreateStackObject(16, Align(16), false); unsigned TPIDR2Obj = MFI.CreateStackObject(16, Align(16), false);
// Store the buffer pointer to the TPIDR2 stack object. // Store the buffer pointer to the TPIDR2 stack object.
MachinePointerInfo MPI = MachinePointerInfo::getStack(MF, FI); MachinePointerInfo MPI = MachinePointerInfo::getStack(MF, TPIDR2Obj);
SDValue Ptr = DAG.getFrameIndex( SDValue Ptr = DAG.getFrameIndex(
FI, DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout())); TPIDR2Obj,
DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
Chain = DAG.getStore(Chain, DL, Buffer, Ptr, MPI); Chain = DAG.getStore(Chain, DL, Buffer, Ptr, MPI);
return TPIDR2Obj; return TPIDR2Obj;
} }
SDValue AArch64TargetLowering::LowerFormalArguments( SDValue AArch64TargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool isVarArg, SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
▲ Show 20 Lines • Show All 17,133 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
; CHECK-COMMON: // %bb.0: // %prelude ; CHECK-COMMON: // %bb.0: // %prelude
; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-COMMON-NEXT: mov x29, sp ; CHECK-COMMON-NEXT: mov x29, sp
; CHECK-COMMON-NEXT: sub sp, sp, #16 ; CHECK-COMMON-NEXT: sub sp, sp, #16
; CHECK-COMMON-NEXT: rdsvl x8, #1 ; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: mov x9, sp ; CHECK-COMMON-NEXT: mov x9, sp
; CHECK-COMMON-NEXT: msub x8, x8, x8, x9 ; CHECK-COMMON-NEXT: msub x8, x8, x8, x9
; CHECK-COMMON-NEXT: mov sp, x8 ; CHECK-COMMON-NEXT: mov sp, x8
; CHECK-COMMON-NEXT: str x8, [x29] ; CHECK-COMMON-NEXT: stur x8, [x29, #-16]
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
; CHECK-COMMON-NEXT: cbz x8, .LBB6_2 ; CHECK-COMMON-NEXT: cbz x8, .LBB6_2
; CHECK-COMMON-NEXT: b .LBB6_1 ; CHECK-COMMON-NEXT: b .LBB6_1
; CHECK-COMMON-NEXT: .LBB6_1: // %save.za ; CHECK-COMMON-NEXT: .LBB6_1: // %save.za
; CHECK-COMMON-NEXT: bl __arm_tpidr2_save ; CHECK-COMMON-NEXT: bl __arm_tpidr2_save
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr ; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr
; CHECK-COMMON-NEXT: b .LBB6_2 ; CHECK-COMMON-NEXT: b .LBB6_2
; CHECK-COMMON-NEXT: .LBB6_2: // %entry ; CHECK-COMMON-NEXT: .LBB6_2: // %entry
Show All 18 Lines
; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-COMMON-NEXT: mov x29, sp ; CHECK-COMMON-NEXT: mov x29, sp
; CHECK-COMMON-NEXT: sub sp, sp, #16 ; CHECK-COMMON-NEXT: sub sp, sp, #16
; CHECK-COMMON-NEXT: rdsvl x8, #1 ; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: mul x8, x8, x8 ; CHECK-COMMON-NEXT: mul x8, x8, x8
; CHECK-COMMON-NEXT: mov x9, sp ; CHECK-COMMON-NEXT: mov x9, sp
; CHECK-COMMON-NEXT: subs x9, x9, x8 ; CHECK-COMMON-NEXT: subs x9, x9, x8
; CHECK-COMMON-NEXT: mov sp, x9 ; CHECK-COMMON-NEXT: mov sp, x9
; CHECK-COMMON-NEXT: str x9, [x29] ; CHECK-COMMON-NEXT: stur x9, [x29, #-16]
; CHECK-COMMON-NEXT: sturh w8, [x29, #-8] ; CHECK-COMMON-NEXT: sturh w8, [x29, #-8]
; CHECK-COMMON-NEXT: sub x8, x29, #16 ; CHECK-COMMON-NEXT: sub x8, x29, #16
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8 ; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8
; CHECK-COMMON-NEXT: bl normal_callee ; CHECK-COMMON-NEXT: bl normal_callee
; CHECK-COMMON-NEXT: smstart za ; CHECK-COMMON-NEXT: smstart za
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
; CHECK-COMMON-NEXT: sub x0, x29, #16 ; CHECK-COMMON-NEXT: sub x0, x29, #16
; CHECK-COMMON-NEXT: cbz x8, .LBB7_1 ; CHECK-COMMON-NEXT: cbz x8, .LBB7_1
Show All 24 Lines
; CHECK-COMMON-NEXT: sub sp, sp, #16 ; CHECK-COMMON-NEXT: sub sp, sp, #16
; CHECK-COMMON-NEXT: rdsvl x8, #1 ; CHECK-COMMON-NEXT: rdsvl x8, #1
; CHECK-COMMON-NEXT: mov x9, sp ; CHECK-COMMON-NEXT: mov x9, sp
; CHECK-COMMON-NEXT: mul x8, x8, x8 ; CHECK-COMMON-NEXT: mul x8, x8, x8
; CHECK-COMMON-NEXT: sub x9, x9, x8 ; CHECK-COMMON-NEXT: sub x9, x9, x8
; CHECK-COMMON-NEXT: mov sp, x9 ; CHECK-COMMON-NEXT: mov sp, x9
; CHECK-COMMON-NEXT: sub x10, x29, #16 ; CHECK-COMMON-NEXT: sub x10, x29, #16
; CHECK-COMMON-NEXT: sturh w8, [x29, #-8] ; CHECK-COMMON-NEXT: sturh w8, [x29, #-8]
; CHECK-COMMON-NEXT: str x9, [x29] ; CHECK-COMMON-NEXT: stur x9, [x29, #-16]
; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10 ; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x10
; CHECK-COMMON-NEXT: bl __addtf3 ; CHECK-COMMON-NEXT: bl __addtf3
; CHECK-COMMON-NEXT: smstart za ; CHECK-COMMON-NEXT: smstart za
; CHECK-COMMON-NEXT: add x0, x29, #0 ; CHECK-COMMON-NEXT: add x0, x29, #0
; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0
; CHECK-COMMON-NEXT: cbnz x8, .LBB8_2 ; CHECK-COMMON-NEXT: cbnz x8, .LBB8_2
; CHECK-COMMON-NEXT: // %bb.1: ; CHECK-COMMON-NEXT: // %bb.1:
; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore ; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore
Show All 37 Lines

llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll

Show All 11 Lines
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mul x8, x8, x8 ; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x9, x9, x8 ; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: mov sp, x9 ; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: str x9, [x29] ; CHECK-NEXT: stur x9, [x29, #-16]
; CHECK-NEXT: sturh w8, [x29, #-8] ; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl private_za_callee ; CHECK-NEXT: bl private_za_callee
; CHECK-NEXT: smstart za ; CHECK-NEXT: smstart za
; CHECK-NEXT: sub x0, x29, #16 ; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbnz x8, .LBB0_2 ; CHECK-NEXT: cbnz x8, .LBB0_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
Show All 16 Lines
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mul x19, x8, x8 ; CHECK-NEXT: mul x19, x8, x8
; CHECK-NEXT: mov x8, sp ; CHECK-NEXT: mov x8, sp
; CHECK-NEXT: sub x8, x8, x19 ; CHECK-NEXT: sub x8, x8, x19
; CHECK-NEXT: mov sp, x8 ; CHECK-NEXT: mov sp, x8
; CHECK-NEXT: sub x20, x29, #16 ; CHECK-NEXT: sub x20, x29, #16
; CHECK-NEXT: str x8, [x29] ; CHECK-NEXT: stur x8, [x29, #-16]
; CHECK-NEXT: sturh w19, [x29, #-8] ; CHECK-NEXT: sturh w19, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x20 ; CHECK-NEXT: msr TPIDR2_EL0, x20
; CHECK-NEXT: bl private_za_callee ; CHECK-NEXT: bl private_za_callee
; CHECK-NEXT: smstart za ; CHECK-NEXT: smstart za
; CHECK-NEXT: sub x0, x29, #16 ; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbnz x8, .LBB1_2 ; CHECK-NEXT: cbnz x8, .LBB1_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
Show All 28 Lines
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mul x8, x8, x8 ; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x9, x9, x8 ; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: mov sp, x9 ; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: str x9, [x29] ; CHECK-NEXT: stur x9, [x29, #-16]
; CHECK-NEXT: sturh w8, [x29, #-8] ; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: smstart za ; CHECK-NEXT: smstart za
; CHECK-NEXT: sub x0, x29, #16 ; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbnz x8, .LBB2_2 ; CHECK-NEXT: cbnz x8, .LBB2_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
Show All 20 Lines
; CHECK-NEXT: str x19, [sp, #80] // 8-byte Folded Spill ; CHECK-NEXT: str x19, [sp, #80] // 8-byte Folded Spill
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mul x8, x8, x8 ; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x9, x9, x8 ; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: mov sp, x9 ; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: sub x10, x29, #80 ; CHECK-NEXT: sub x10, x29, #80
; CHECK-NEXT: stur x9, [x29, #-64] ; CHECK-NEXT: stur x9, [x29, #-80]
; CHECK-NEXT: sturh w8, [x29, #-72] ; CHECK-NEXT: sturh w8, [x29, #-72]
; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl __arm_sme_state ; CHECK-NEXT: bl __arm_sme_state
; CHECK-NEXT: and x19, x0, #0x1 ; CHECK-NEXT: and x19, x0, #0x1
; CHECK-NEXT: tbz x19, #0, .LBB3_2 ; CHECK-NEXT: tbz x19, #0, .LBB3_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: smstop sm ; CHECK-NEXT: smstop sm
; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: .LBB3_2:
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llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll

Show All 10 Lines
; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mul x8, x8, x8 ; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x9, x9, x8 ; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: mov sp, x9 ; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: str x9, [x29] ; CHECK-NEXT: stur x9, [x29, #-16]
; CHECK-NEXT: sturh w8, [x29, #-8] ; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl private_za_callee ; CHECK-NEXT: bl private_za_callee
; CHECK-NEXT: smstart za ; CHECK-NEXT: smstart za
; CHECK-NEXT: sub x0, x29, #16 ; CHECK-NEXT: sub x0, x29, #16
; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbnz x8, .LBB0_2 ; CHECK-NEXT: cbnz x8, .LBB0_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
Show All 16 Lines
; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: rdsvl x8, #1
; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: mul x8, x8, x8 ; CHECK-NEXT: mul x8, x8, x8
; CHECK-NEXT: sub x9, x9, x8 ; CHECK-NEXT: sub x9, x9, x8
; CHECK-NEXT: mov sp, x9 ; CHECK-NEXT: mov sp, x9
; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: sub x10, x29, #16
; CHECK-NEXT: sturh w8, [x29, #-8] ; CHECK-NEXT: sturh w8, [x29, #-8]
; CHECK-NEXT: str x9, [x29] ; CHECK-NEXT: stur x9, [x29, #-16]
; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: msr TPIDR2_EL0, x10
; CHECK-NEXT: bl __addtf3 ; CHECK-NEXT: bl __addtf3
; CHECK-NEXT: smstart za ; CHECK-NEXT: smstart za
; CHECK-NEXT: add x0, x29, #0 ; CHECK-NEXT: add x0, x29, #0
; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: mrs x8, TPIDR2_EL0
; CHECK-NEXT: cbnz x8, .LBB1_2 ; CHECK-NEXT: cbnz x8, .LBB1_2
; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: bl __arm_tpidr2_restore ; CHECK-NEXT: bl __arm_tpidr2_restore
; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: msr TPIDR2_EL0, xzr ; CHECK-NEXT: msr TPIDR2_EL0, xzr
; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = fadd fp128 %a, %b %res = fadd fp128 %a, %b
ret fp128 %res ret fp128 %res
} }