[AArch64][SVE2] Add the SVE2.1 tbxq instruction

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instruction:

tbxq : Programmable table lookup within each quadword vector segment (merging)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[CarolineConcatto]

llvm/lib/Target/AArch64/SVEInstrFormats.td

9430

I don't know how much should we re-use the old classes.
but with some changes you could re-use class sve2_int_perm_tbx, no?
let Inst{15-13} = 0b001;
let Inst{12-10} = op

[paulwalker-arm]

llvm/lib/Target/AArch64/SVEInstrFormats.td

9430

I agree, and by reusing the sve2_int_perm_tbx multiclass we can also easily add the code generation support once the intrinsic exists.

[david-arm]

• Changed tbxq to reuse the existing sve2_int_perm_tbx class.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3788

Is there a reason not to reuse the multiclass as well? You can pass in null_frag as the pattern and then once the intrinsic exists it'll be a one word change.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE2] in {
   defm STNT1H_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b010, "stnt1h", AArch64stnt1_scatter, nxv2i16>;
   defm STNT1W_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b100, "stnt1w", AArch64stnt1_scatter, nxv2i32>;
   defm STNT1D_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b110, "stnt1d", AArch64stnt1_scatter, nxv2i64>;
 } // End HasSVE2
 
 let Predicates = [HasSVE2orSME] in {
   // SVE2 table lookup (three sources)
   defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl", int_aarch64_sve_tbl2>;
-  defm TBX_ZZZ  : sve2_int_perm_tbx<"tbx", int_aarch64_sve_tbx>;
+  defm TBX_ZZZ  : sve2_int_perm_tbx<"tbx", 0b01, int_aarch64_sve_tbx>;
 
   // SVE2 integer compare scalar count and limit
   defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege>;
   defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt>;
   defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs>;
   defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi>;
 
   defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege>;

 defm FMINQV   : sve2p1_fp_reduction_q<0b111, "fminqv">;
 
 defm DUPQ_ZZI : sve2p1_dupq<"dupq">;
 def EXTQ_ZZI : sve2p1_extq<"extq">;
 
 defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">;
 defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">;
 
 defm ORQV_VPZ   : sve2p1_int_reduce_q<0b1100, "orqv">;
 defm EORQV_VPZ  : sve2p1_int_reduce_q<0b1101, "eorqv">;
 defm ANDQV_VPZ  : sve2p1_int_reduce_q<0b1110, "andqv">;
 defm ADDQV_VPZ  : sve2p1_int_reduce_q<0b0001, "addqv">;
 defm SMAXQV_VPZ : sve2p1_int_reduce_q<0b0100, "smaxqv">;
 defm UMAXQV_VPZ : sve2p1_int_reduce_q<0b0101, "umaxqv">;
 defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv">;
 defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv">;
+
+defm TBXQ_ZZZ : sve2_int_perm_tbx<"tbxq", 0b10, null_frag>;
 } // End HasSVE2p1_or_HasSME2p1

llvm/lib/Target/AArch64/SVEInstrFormats.td

def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2i64:$Op3)),
                                                      nxv2i64:$Op3))>;
 
   def : Pat<(nxv8bf16 (op nxv8bf16:$Op1, nxv8bf16:$Op2, nxv8i16:$Op3)),
             (nxv8bf16 (!cast<Instruction>(NAME # _H) (REG_SEQUENCE ZPR2, nxv8bf16:$Op1, zsub0,
                                                                          nxv8bf16:$Op2, zsub1),
                                                       nxv8i16:$Op3))>;
 }
 
-class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty>
+class sve2_int_perm_tbx<bits<2> sz8_64, bits<2> opc, string asm, ZPRRegOp zprty>
 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zd, $Zn, $Zm",
   "",
   []>, Sched<[]> {
   bits<5> Zd;
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = sz8_64;
   let Inst{21}    = 0b1;
   let Inst{20-16} = Zm;
-  let Inst{15-10} = 0b001011;
+  let Inst{15-13} = 0b001;
+  let Inst{12-11} = opc;
+  let Inst{10}    = 0b1;
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
 
   let Constraints = "$Zd = $_Zd";
 }
 
-multiclass sve2_int_perm_tbx<string asm, SDPatternOperator op> {
-  def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>;
-  def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>;
-  def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>;
-  def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>;
+multiclass sve2_int_perm_tbx<string asm, bits<2> opc, SDPatternOperator op> {
+  def _B : sve2_int_perm_tbx<0b00, opc, asm, ZPR8>;
+  def _H : sve2_int_perm_tbx<0b01, opc, asm, ZPR16>;
+  def _S : sve2_int_perm_tbx<0b10, opc, asm, ZPR32>;
+  def _D : sve2_int_perm_tbx<0b11, opc, asm, ZPR64>;
 
   def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
   def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
 
   def : SVE_3_Op_Pat<nxv8f16, op, nxv8f16, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
class sve2p1_extq<string mnemonic>
 
   let Constraints = "$Zdn = $_Zdn";
   let DestructiveInstType = DestructiveOther;
   let ElementSize = ZPR8.ElementSize;
 }
 
 
 // SVE move predicate from vector
 class sve2p1_vector_to_pred<bits<4> opc, string mnemonic,
                             PPRRegOp ppr_ty, Operand itype>
     : I<(outs ppr_ty:$Pd), (ins ZPRAny:$Zn, itype:$index),
         mnemonic, "\t$Pd, $Zn$index",
         "", []>, Sched<[]> {
   bits<4> Pd;
   bits<5> Zn;
   let Inst{31-24} = 0b00000101;
   let Inst{23-22} = opc{3-2};

llvm/test/MC/AArch64/SVE2p1/tbxq-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+tbxq z0.b, z0.h, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid
+// CHECK-NEXT: tbxq z0.b, z0.h, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+tbxq z23.d, z23.s, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: tbxq z23.d, z23.s, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/tbxq.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+tbxq    z0.h, z0.h, z0.h  // 00000101-01100000-00110100-00000000
+// CHECK-INST: tbxq    z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x34,0x60,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05603400 <unknown>
+
+tbxq    z21.h, z10.h, z21.h  // 00000101-01110101-00110101-01010101
+// CHECK-INST: tbxq    z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0x35,0x75,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05753555 <unknown>
+
+tbxq    z23.h, z13.h, z8.h  // 00000101-01101000-00110101-10110111
+// CHECK-INST: tbxq    z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0x35,0x68,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 056835b7 <unknown>
+
+tbxq    z31.h, z31.h, z31.h  // 00000101-01111111-00110111-11111111
+// CHECK-INST: tbxq    z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x37,0x7f,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 057f37ff <unknown>
+
+
+tbxq    z0.s, z0.s, z0.s  // 00000101-10100000-00110100-00000000
+// CHECK-INST: tbxq    z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x34,0xa0,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a03400 <unknown>
+
+tbxq    z21.s, z10.s, z21.s  // 00000101-10110101-00110101-01010101
+// CHECK-INST: tbxq    z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0x35,0xb5,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05b53555 <unknown>
+
+tbxq    z23.s, z13.s, z8.s  // 00000101-10101000-00110101-10110111
+// CHECK-INST: tbxq    z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0x35,0xa8,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a835b7 <unknown>
+
+tbxq    z31.s, z31.s, z31.s  // 00000101-10111111-00110111-11111111
+// CHECK-INST: tbxq    z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x37,0xbf,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05bf37ff <unknown>
+
+
+tbxq    z0.d, z0.d, z0.d  // 00000101-11100000-00110100-00000000
+// CHECK-INST: tbxq    z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x34,0xe0,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05e03400 <unknown>
+
+tbxq    z21.d, z10.d, z21.d  // 00000101-11110101-00110101-01010101
+// CHECK-INST: tbxq    z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0x35,0xf5,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05f53555 <unknown>
+
+tbxq    z23.d, z13.d, z8.d  // 00000101-11101000-00110101-10110111
+// CHECK-INST: tbxq    z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x35,0xe8,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05e835b7 <unknown>
+
+tbxq    z31.d, z31.d, z31.d  // 00000101-11111111-00110111-11111111
+// CHECK-INST: tbxq    z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x37,0xff,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05ff37ff <unknown>
+
+
+tbxq    z0.b, z0.b, z0.b  // 00000101-00100000-00110100-00000000
+// CHECK-INST: tbxq    z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x34,0x20,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05203400 <unknown>
+
+tbxq    z21.b, z10.b, z21.b  // 00000101-00110101-00110101-01010101
+// CHECK-INST: tbxq    z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0x35,0x35,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05353555 <unknown>
+
+tbxq    z23.b, z13.b, z8.b  // 00000101-00101000-00110101-10110111
+// CHECK-INST: tbxq    z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0x35,0x28,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052835b7 <unknown>
+
+tbxq    z31.b, z31.b, z31.b  // 00000101-00111111-00110111-11111111
+// CHECK-INST: tbxq    z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x37,0x3f,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 053f37ff <unknown>
+