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Differential D137355

[RISCV] Define custom-N opcodes
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Authored by reames on Nov 3 2022, 1:35 PM.

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craig.topper
asb
frasercrmck
kito-cheng
Commits
rG254bf678d491: [RISCV] Define custom-N opcodes

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reames created this revision.Nov 3 2022, 1:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2022, 1:35 PM
Herald added subscribers: sunshaoce, VincentWu, StephenFan and 28 others. · View Herald Transcript
reames requested review of this revision.Nov 3 2022, 1:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2022, 1:35 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
reames mentioned this in D137350: [RISCV] Implement assembler support for XVentanaCondOps.Nov 3 2022, 1:39 PM
Harbormaster completed remote builds in B195990: Diff 473018.Nov 3 2022, 2:27 PM
kito-cheng accepted this revision.Nov 4 2022, 9:55 AM

LGTM, checked with spec.

This revision is now accepted and ready to land.Nov 4 2022, 9:55 AM
craig.topper accepted this revision.Nov 4 2022, 9:55 AM

LGTM

Closed by commit rG254bf678d491: [RISCV] Define custom-N opcodes (authored by reames). · Explain WhyNov 4 2022, 10:05 AM
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG254bf678d491: [RISCV] Define custom-N opcodes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines

Diff 473018

llvm/lib/Target/RISCV/RISCVInstrFormats.td

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Linesdef RISCVOpcodesList : GenericTable {
let PrimaryKeyName = "lookupRISCVOpcodeByValue"; let PrimaryKeyName = "lookupRISCVOpcodeByValue";
} }
def lookupRISCVOpcodeByName : SearchIndex { def lookupRISCVOpcodeByName : SearchIndex {
let Table = RISCVOpcodesList; let Table = RISCVOpcodesList;
let Key = [ "Name" ]; let Key = [ "Name" ];
} }
def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>; def OPC_LOAD : RISCVOpcode<"LOAD", 0b0000011>;
def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>; def OPC_LOAD_FP : RISCVOpcode<"LOAD_FP", 0b0000111>;
def OPC_CUSTOM_0 : RISCVOpcode<"CUSTOM_0", 0b0001011>;
def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>; def OPC_MISC_MEM : RISCVOpcode<"MISC_MEM", 0b0001111>;
def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>; def OPC_OP_IMM : RISCVOpcode<"OP_IMM", 0b0010011>;
def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>; def OPC_AUIPC : RISCVOpcode<"AUIPC", 0b0010111>;
def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>; def OPC_OP_IMM_32 : RISCVOpcode<"OP_IMM_32", 0b0011011>;
def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>; def OPC_STORE : RISCVOpcode<"STORE", 0b0100011>;
def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>; def OPC_STORE_FP : RISCVOpcode<"STORE_FP", 0b0100111>;
def OPC_CUSTOM_1 : RISCVOpcode<"CUSTOM_1", 0b0101011>;
def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>; def OPC_AMO : RISCVOpcode<"AMO", 0b0101111>;
def OPC_OP : RISCVOpcode<"OP", 0b0110011>; def OPC_OP : RISCVOpcode<"OP", 0b0110011>;
def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>; def OPC_LUI : RISCVOpcode<"LUI", 0b0110111>;
def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>; def OPC_OP_32 : RISCVOpcode<"OP_32", 0b0111011>;
def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>; def OPC_MADD : RISCVOpcode<"MADD", 0b1000011>;
def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>; def OPC_MSUB : RISCVOpcode<"MSUB", 0b1000111>;
def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>; def OPC_NMSUB : RISCVOpcode<"NMSUB", 0b1001011>;
def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>; def OPC_NMADD : RISCVOpcode<"NMADD", 0b1001111>;
def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>; def OPC_OP_FP : RISCVOpcode<"OP_FP", 0b1010011>;
def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>; def OPC_OP_V : RISCVOpcode<"OP_V", 0b1010111>;
def OPC_CUSTOM_2 : RISCVOpcode<"CUSTOM_2", 0b1011011>;
def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>; def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>;
def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>;
def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>;
def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
class RVInst<dag outs, dag ins, string opcodestr, string argstr, class RVInst<dag outs, dag ins, string opcodestr, string argstr,
list<dag> pattern, InstFormat format> list<dag> pattern, InstFormat format>
: Instruction { : Instruction {
field bits<32> Inst; field bits<32> Inst;
// SoftFail is a field the disassembler can use to provide a way for // SoftFail is a field the disassembler can use to provide a way for
// instructions to not match without killing the whole decode process. It is // instructions to not match without killing the whole decode process. It is
// mainly used for ARM, but Tablegen expects this field to exist or it fails // mainly used for ARM, but Tablegen expects this field to exist or it fails
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