[AMDGPU] Refactor debug printing routines for GCNRPTracker

[vpykhtin]

Summary

Use Printable to enhance syntax, remove duplication, unify.

[rampitec]

llvm/lib/Target/AMDGPU/GCNRegPressure.h

89

Can we retain/reimplement dump() for use from the debugger?

[vpykhtin]

restored dump() method

[rampitec]

LGTM

[vpykhtin]

rebase

llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp

 static void printLivenessInfo(raw_ostream &OS,
                               MachineBasicBlock::iterator Begin,
                               MachineBasicBlock::iterator End,
                               const LiveIntervals *LIS) {
   const auto BB = Begin->getParent();
   const auto &MRI = BB->getParent()->getRegInfo();
 
   const auto LiveIns = getLiveRegsBefore(*Begin, *LIS);
-  OS << "LIn RP: ";
-  getRegPressure(MRI, LiveIns).print(OS);
+  OS << "LIn RP: " << print(getRegPressure(MRI, LiveIns));
 
   const auto BottomMI = End == BB->end() ? std::prev(End) : End;
   const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS);
-  OS << "LOt RP: ";
-  getRegPressure(MRI, LiveOuts).print(OS);
+  OS << "LOt RP: " << print(getRegPressure(MRI, LiveOuts));
 }
 
 LLVM_DUMP_METHOD
 void GCNIterativeScheduler::printRegions(raw_ostream &OS) const {
   const auto &ST = MF.getSubtarget<GCNSubtarget>();
   for (const auto R : Regions) {
     OS << "Region to schedule ";
     printRegion(OS, R->Begin, R->End, LIS, 1);
     printLivenessInfo(OS, R->Begin, R->End, LIS);
-    OS << "Max RP: ";
-    R->MaxPressure.print(OS, &ST);
+    OS << "Max RP: " << print(R->MaxPressure, &ST);
   }
 }
 
 LLVM_DUMP_METHOD
 void GCNIterativeScheduler::printSchedResult(raw_ostream &OS,
                                              const Region *R,
                                              const GCNRegPressure &RP) const {
   OS << "\nAfter scheduling ";
   printRegion(OS, R->Begin, R->End, LIS);
   printSchedRP(OS, R->MaxPressure, RP);
   OS << '\n';
 }
 
 LLVM_DUMP_METHOD
 void GCNIterativeScheduler::printSchedRP(raw_ostream &OS,
                                          const GCNRegPressure &Before,
                                          const GCNRegPressure &After) const {
   const auto &ST = MF.getSubtarget<GCNSubtarget>();
-  OS << "RP before: ";
-  Before.print(OS, &ST);
-  OS << "RP after:  ";
-  After.print(OS, &ST);
+  OS << "RP before: " << print(Before, &ST)
+     << "RP after:  " << print(After, &ST);
 }
 #endif
 
 // DAG builder helper
 class GCNIterativeScheduler::BuildDAG {
   GCNIterativeScheduler &Sch;
   SmallVector<SUnit *, 8> TopRoots;
 
Regions.push_back(
                getRegionPressure(Begin, End), nullptr });
   }
 }
 
 void GCNIterativeScheduler::schedule() { // overridden
   // do nothing
   LLVM_DEBUG(printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS);
              if (!Regions.empty() && Regions.back()->Begin == RegionBegin) {
-               dbgs() << "Max RP: ";
-               Regions.back()->MaxPressure.print(
-                   dbgs(), &MF.getSubtarget<GCNSubtarget>());
+               dbgs() << "Max RP: "
+                      << print(Regions.back()->MaxPressure,
+                               &MF.getSubtarget<GCNSubtarget>());
              } dbgs()
              << '\n';);
 }
 
 void GCNIterativeScheduler::finalizeSchedule() { // overridden
   if (Regions.empty())
     return;
   switch (Strategy) {
#endif
 
   R.Begin = RegionBegin;
   R.MaxPressure = MaxRP;
 
 #ifndef NDEBUG
   const auto RegionMaxRP = getRegionPressure(R);
   const auto &ST = MF.getSubtarget<GCNSubtarget>();
 #endif
-  assert((SchedMaxRP == RegionMaxRP && (MaxRP.empty() || SchedMaxRP == MaxRP))
-  || (dbgs() << "Max RP mismatch!!!\n"
-                "RP for schedule (calculated): ",
-      SchedMaxRP.print(dbgs(), &ST),
-      dbgs() << "RP for schedule (reported): ",
-      MaxRP.print(dbgs(), &ST),
-      dbgs() << "RP after scheduling: ",
-      RegionMaxRP.print(dbgs(), &ST),
+  assert(
+      (SchedMaxRP == RegionMaxRP && (MaxRP.empty() || SchedMaxRP == MaxRP)) ||
+      (dbgs() << "Max RP mismatch!!!\n"
+                 "RP for schedule (calculated): "
+              << print(SchedMaxRP, &ST)
+              << "RP for schedule (reported): " << print(MaxRP, &ST)
+              << "RP after scheduling: " << print(RegionMaxRP, &ST),
        false));
 }
 
 // Sort recorded regions by pressure - highest at the front
 void GCNIterativeScheduler::sortRegionsByPressure(unsigned TargetOcc) {
   const auto &ST = MF.getSubtarget<GCNSubtarget>();
   llvm::sort(Regions, [&ST, TargetOcc](const Region *R1, const Region *R2) {
     return R2->MaxPressure.less(ST, R1->MaxPressure, TargetOcc);
   });

llvm/lib/Target/AMDGPU/GCNRegPressure.h

struct GCNRegPressure {
   bool operator==(const GCNRegPressure &O) const {
     return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
   }
 
   bool operator!=(const GCNRegPressure &O) const {
     return !(*this == O);
   }
 
-  void print(raw_ostream &OS, const GCNSubtarget *ST = nullptr) const;
-  void dump() const { print(dbgs()); }
+  void dump() const;
 
 private:
   unsigned Value[TOTAL_KINDS];
 
   static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
 
   friend GCNRegPressure max(const GCNRegPressure &P1,
                             const GCNRegPressure &P2);
+
+  friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
 };
 
 inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
   GCNRegPressure Res;
   for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
     Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
   return Res;
 }
decltype(MaxPressure) moveMaxPressure() {
     auto Res = MaxPressure;
     MaxPressure.clear();
     return Res;
   }
 
   decltype(LiveRegs) moveLiveRegs() {
     return std::move(LiveRegs);
   }
-
-  static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
-                            const MachineRegisterInfo &MRI);
 };
 
 class GCNUpwardRPTracker : public GCNRPTracker {
 public:
   GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
 
   // reset tracker to the point just below MI
   // filling live regs upon this point using LIS
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
   for (const auto &RM : LiveRegs)
     Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
   return Res;
 }
 
 bool isEqual(const GCNRPTracker::LiveRegSet &S1,
              const GCNRPTracker::LiveRegSet &S2);
 
-void printLivesAt(SlotIndex SI,
-                  const LiveIntervals &LIS,
-                  const MachineRegisterInfo &MRI);
+Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
+
+Printable print(const GCNRPTracker::LiveRegSet &LiveRegs,
 
+Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
+                         const GCNRPTracker::LiveRegSet &TrackedL,
+                         const TargetRegisterInfo *TRI);
+
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

 
 #include "GCNRegPressure.h"
 #include "llvm/CodeGen/RegisterPressure.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "machine-scheduler"
 
-#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-LLVM_DUMP_METHOD
-void llvm::printLivesAt(SlotIndex SI,
-                        const LiveIntervals &LIS,
-                        const MachineRegisterInfo &MRI) {
-  dbgs() << "Live regs at " << SI << ": "
-         << *LIS.getInstructionFromIndex(SI);
-  unsigned Num = 0;
-  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
-    const Register Reg = Register::index2VirtReg(I);
-    if (!LIS.hasInterval(Reg))
-      continue;
-    const auto &LI = LIS.getInterval(Reg);
-    if (LI.hasSubRanges()) {
-      bool firstTime = true;
-      for (const auto &S : LI.subranges()) {
-        if (!S.liveAt(SI)) continue;
-        if (firstTime) {
-          dbgs() << "  " << printReg(Reg, MRI.getTargetRegisterInfo())
-                 << '\n';
-          firstTime = false;
-        }
-        dbgs() << "  " << S << '\n';
-        ++Num;
-      }
-    } else if (LI.liveAt(SI)) {
-      dbgs() << "  " << LI << '\n';
-      ++Num;
-    }
-  }
-  if (!Num) dbgs() << "  <none>\n";
-}
-#endif
-
 bool llvm::isEqual(const GCNRPTracker::LiveRegSet &S1,
                    const GCNRPTracker::LiveRegSet &S2) {
   if (S1.size() != S2.size())
     return false;
 
   for (const auto &P : S1) {
     auto I = S2.find(P.first);
     if (I == S2.end() || I->second != P.second)
bool GCNRegPressure::less(const GCNSubtarget &ST,
   }
   return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
                          (getVGPRNum(ST.hasGFX90AInsts()) <
                           O.getVGPRNum(ST.hasGFX90AInsts()));
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
-void GCNRegPressure::print(raw_ostream &OS, const GCNSubtarget *ST) const {
-  OS << "VGPRs: " << Value[VGPR32] << ' ';
-  OS << "AGPRs: " << Value[AGPR32];
-  if (ST) OS << "(O"
-             << ST->getOccupancyWithNumVGPRs(getVGPRNum(ST->hasGFX90AInsts()))
-             << ')';
-  OS << ", SGPRs: " << getSGPRNum();
-  if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGPRNum()) << ')';
-  OS << ", LVGPR WT: " << getVGPRTuplesWeight()
-     << ", LSGPR WT: " << getSGPRTuplesWeight();
-  if (ST) OS << " -> Occ: " << getOccupancy(*ST);
+Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST) {
+  return Printable([&RP, ST](raw_ostream &OS) {
+    OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' '
+       << "AGPRs: " << RP.getAGPRNum();
+    if (ST)
+      OS << "(O"
+         << ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()))
+    OS << ", SGPRs: " << RP.getSGPRNum();
+    if (ST)
+      OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
+    OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
+       << ", LSGPR WT: " << RP.getSGPRTuplesWeight();
+    if (ST)
+      OS << " -> Occ: " << RP.getOccupancy(*ST);
     OS << '\n';
+  });
 }
 #endif
 
 static LaneBitmask getDefRegMask(const MachineOperand &MO,
                                  const MachineRegisterInfo &MRI) {
   assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
 
   // We don't rely on read-undef flag because in case of tentative schedule
bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator Begin,
                                    MachineBasicBlock::const_iterator End,
                                    const LiveRegSet *LiveRegsCopy) {
   reset(*Begin, LiveRegsCopy);
   return advance(End);
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
-static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
+Printable llvm::reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
                                const GCNRPTracker::LiveRegSet &TrackedLR,
                                const TargetRegisterInfo *TRI) {
+  return Printable([&LISLR, &TrackedLR, TRI](raw_ostream &OS) {
     for (auto const &P : TrackedLR) {
       auto I = LISLR.find(P.first);
       if (I == LISLR.end()) {
-      dbgs() << "  " << printReg(P.first, TRI)
-             << ":L" << PrintLaneMask(P.second)
-             << " isn't found in LIS reported set\n";
-    }
-    else if (I->second != P.second) {
-      dbgs() << "  " << printReg(P.first, TRI)
-        << " masks doesn't match: LIS reported "
-        << PrintLaneMask(I->second)
-        << ", tracked "
-        << PrintLaneMask(P.second)
-        << '\n';
+        OS << "  " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
+      } else if (I->second != P.second) {
+        OS << "  " << printReg(P.first, TRI)
+           << " masks doesn't match: LIS reported " << PrintLaneMask(I->second)
+           << ", tracked " << PrintLaneMask(P.second) << '\n';
       }
     }
     for (auto const &P : LISLR) {
       auto I = TrackedLR.find(P.first);
       if (I == TrackedLR.end()) {
-      dbgs() << "  " << printReg(P.first, TRI)
-             << ":L" << PrintLaneMask(P.second)
-             << " isn't found in tracked set\n";
+        OS << "  " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
       }
     }
+  });
 }
 
 bool GCNUpwardRPTracker::isValid() const {
   const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
   const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
   const auto &TrackedLR = LiveRegs;
 
   if (!isEqual(LISLR, TrackedLR)) {
     dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
-              " LIS reported livesets mismatch:\n";
-    printLivesAt(SI, LIS, *MRI);
+              " LIS reported livesets mismatch:\n"
+           << print(LISLR, *MRI);
     reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
     return false;
   }
 
   auto LISPressure = getRegPressure(*MRI, LISLR);
   if (LISPressure != CurPressure) {
-    dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
-    CurPressure.print(dbgs());
-    dbgs() << "LIS rpt: ";
-    LISPressure.print(dbgs());
+    dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
+           << print(CurPressure) << "LIS rpt: " << print(LISPressure);
     return false;
   }
   return true;
 }
 
-void GCNRPTracker::printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
-                                 const MachineRegisterInfo &MRI) {
+LLVM_DUMP_METHOD
+Printable llvm::print(const GCNRPTracker::LiveRegSet &LiveRegs,
+  return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
     const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
     for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
       Register Reg = Register::index2VirtReg(I);
       auto It = LiveRegs.find(Reg);
       if (It != LiveRegs.end() && It->second.any())
         OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
            << PrintLaneMask(It->second);
     }
     OS << '\n';
+  });
 }
+
+LLVM_DUMP_METHOD
+void GCNRegPressure::dump() const { dbgs() << print(*this); }
+
 #endif

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

bool GCNSchedStage::initGCNRegion() {
   } else {
     for (auto &I : DAG)
       Unsched.push_back(&I);
   }
 
   PressureBefore = DAG.Pressure[RegionIdx];
 
   LLVM_DEBUG(
-      dbgs() << "Pressure before scheduling:\nRegion live-ins:";
-      GCNRPTracker::printLiveRegs(dbgs(), DAG.LiveIns[RegionIdx], DAG.MRI);
-      dbgs() << "Region live-in pressure:  ";
-      llvm::getRegPressure(DAG.MRI, DAG.LiveIns[RegionIdx]).print(dbgs());
-      dbgs() << "Region register pressure: "; PressureBefore.print(dbgs()));
+      dbgs() << "Pressure before scheduling:\nRegion live-ins:"
+             << print(DAG.LiveIns[RegionIdx], DAG.MRI)
+             << "Region live-in pressure:  "
+             << print(llvm::getRegPressure(DAG.MRI, DAG.LiveIns[RegionIdx]))
+             << "Region register pressure: " << print(PressureBefore));
 
   S.HasHighPressure = false;
 
   if (DAG.RegionsWithIGLPInstrs[RegionIdx] &&
       StageID != GCNSchedStageID::UnclusteredHighRPReschedule) {
     SavedMutations.clear();
     SavedMutations.swap(DAG.Mutations);
     DAG.addMutation(createIGroupLPDAGMutation());
void GCNSchedStage::finalizeGCNRegion() {
 
   DAG.exitRegion();
   RegionIdx++;
 }
 
 void GCNSchedStage::checkScheduling() {
   // Check the results of scheduling.
   PressureAfter = DAG.getRealRegPressure(RegionIdx);
-  LLVM_DEBUG(dbgs() << "Pressure after scheduling: ";
-             PressureAfter.print(dbgs()));
+  LLVM_DEBUG(dbgs() << "Pressure after scheduling: " << print(PressureAfter));
 
   if (PressureAfter.getSGPRNum() <= S.SGPRCriticalLimit &&
       PressureAfter.getVGPRNum(ST.hasGFX90AInsts()) <= S.VGPRCriticalLimit) {
     DAG.Pressure[RegionIdx] = PressureAfter;
     DAG.RegionsWithMinOcc[RegionIdx] =
         PressureAfter.getOccupancy(ST) == DAG.MinOccupancy;
 
     // Early out if we have achieve the occupancy target.