[mlir][llvm] Use tablegen to import atomic ops from LLVM IR.

[gysit]

Summary

The revision imports the atomic operations using
tablegen generated builders. Additionally, it moves their tests to
the instructions.ll test file.

Depends on D135880

mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td

 
 // FIXME: Need to add alignment and syncscope attribute to MLIR atomicrmw
 // operation.
 def LLVM_AtomicRMWOp : LLVM_Op<"atomicrmw"> {
   let arguments = (ins AtomicBinOp:$bin_op,
                    LLVM_PointerTo<LLVM_AtomicRMWType>:$ptr,
                    LLVM_AtomicRMWType:$val, AtomicOrdering:$ordering);
   let results = (outs LLVM_AtomicRMWType:$res);
-  let llvmBuilder = [{
+  let hasCustomAssemblyFormat = 1;
+  let hasVerifier = 1;
+  string llvmInstName = "AtomicRMW";
+  string llvmBuilder = [{
     $res = builder.CreateAtomicRMW(getLLVMAtomicBinOp($bin_op), $ptr, $val,
                                    llvm::MaybeAlign(),
                                    getLLVMAtomicOrdering($ordering));
   }];
-  let hasCustomAssemblyFormat = 1;
-  let hasVerifier = 1;
+  string mlirBuilder = [{
+    auto *atomicInst = cast<llvm::AtomicRMWInst>(inst);
+    $res = $_builder.create<LLVM::AtomicRMWOp>($_location, $_resultType,
+        getLLVMAtomicBinOp(atomicInst->getOperation()), $ptr, $val,
+        getLLVMAtomicOrdering(atomicInst->getOrdering()));
+  }];
+  // Only $ptr and $val are llvm instruction operands.
+  list<int> llvmArgIndices = [-1, 0, 1, -1];
 }
 
 def LLVM_AtomicCmpXchgType : AnyTypeOf<[AnyInteger, LLVM_AnyPointer]>;
 def LLVM_AtomicCmpXchgResultType : Type<And<[
   LLVM_AnyStruct.predicate,
   CPred<"$_self.cast<::mlir::LLVM::LLVMStructType>().getBody().size() == 2">,
   SubstLeaves<"$_self",
               "$_self.cast<::mlir::LLVM::LLVMStructType>().getBody()[0]",
               LLVM_AtomicCmpXchgType.predicate>,
   SubstLeaves<"$_self",
               "$_self.cast<::mlir::LLVM::LLVMStructType>().getBody()[1]",
               I1.predicate>]>,
  "an LLVM struct type with any integer or pointer followed by a single-bit "
  "integer">;
 
 // FIXME: Need to add alignment attribute to MLIR cmpxchg operation.
 def LLVM_AtomicCmpXchgOp : LLVM_Op<"cmpxchg"> {
   let arguments = (ins LLVM_PointerTo<LLVM_AtomicCmpXchgType>:$ptr,
                    LLVM_AtomicCmpXchgType:$cmp, LLVM_AtomicCmpXchgType:$val,
                    AtomicOrdering:$success_ordering,
                    AtomicOrdering:$failure_ordering);
   let results = (outs LLVM_AtomicCmpXchgResultType:$res);
-  let llvmBuilder = [{
+  let hasCustomAssemblyFormat = 1;
+  let hasVerifier = 1;
+  string llvmInstName = "AtomicCmpXchg";
+  string llvmBuilder = [{
     $res = builder.CreateAtomicCmpXchg($ptr, $cmp, $val, llvm::MaybeAlign(),
                    getLLVMAtomicOrdering($success_ordering),
                    getLLVMAtomicOrdering($failure_ordering));
   }];
-  let hasCustomAssemblyFormat = 1;
-  let hasVerifier = 1;
+  string mlirBuilder = [{
+    auto *cmpXchgInst = cast<llvm::AtomicCmpXchgInst>(inst);
+    $res = $_builder.create<LLVM::AtomicCmpXchgOp>(
+      $_location, $_resultType, $ptr, $cmp, $val,
+      getLLVMAtomicOrdering(cmpXchgInst->getSuccessOrdering()),
+      getLLVMAtomicOrdering(cmpXchgInst->getFailureOrdering()));
+  }];
 }
 
 def LLVM_FenceOp : LLVM_Op<"fence"> {
   let arguments = (ins AtomicOrdering:$ordering, StrAttr:$syncscope);
   let builders = [LLVM_VoidResultTypeOpBuilder, LLVM_ZeroResultOpBuilder];
   string llvmInstName = "Fence";
   let llvmBuilder = [{
     llvm::LLVMContext &llvmContext = builder.getContext();

mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

if (llvm::Function *callee = ii->getCalledFunction()) {
                               normalArgs, blocks[ii->getUnwindDest()],
                               unwindArgs);
     }
 
     if (!ii->getType()->isVoidTy())
       mapValue(inst, op->getResult(0));
     return success();
   }
-  if (inst->getOpcode() == llvm::Instruction::AtomicRMW) {
-    auto *atomicInst = cast<llvm::AtomicRMWInst>(inst);
-    Value ptr = processValue(atomicInst->getPointerOperand());
-    Value val = processValue(atomicInst->getValOperand());
-
-    LLVM::AtomicBinOp binOp = getLLVMAtomicBinOp(atomicInst->getOperation());
-    LLVM::AtomicOrdering ordering =
-        getLLVMAtomicOrdering(atomicInst->getOrdering());
-
-    Type type = convertType(inst->getType());
-    Value res = b.create<AtomicRMWOp>(loc, type, binOp, ptr, val, ordering);
-    mapValue(inst, res);
-    return success();
-  }
-  if (inst->getOpcode() == llvm::Instruction::AtomicCmpXchg) {
-    auto *cmpXchgInst = cast<llvm::AtomicCmpXchgInst>(inst);
-    Value ptr = processValue(cmpXchgInst->getPointerOperand());
-    Value cmpVal = processValue(cmpXchgInst->getCompareOperand());
-    Value newVal = processValue(cmpXchgInst->getNewValOperand());
-
-    LLVM::AtomicOrdering ordering =
-        getLLVMAtomicOrdering(cmpXchgInst->getSuccessOrdering());
-    LLVM::AtomicOrdering failOrdering =
-        getLLVMAtomicOrdering(cmpXchgInst->getFailureOrdering());
-
-    Type type = convertType(inst->getType());
-    Value res = b.create<AtomicCmpXchgOp>(loc, type, ptr, cmpVal, newVal,
-                                          ordering, failOrdering);
-    mapValue(inst, res);
-    return success();
-  }
   if (inst->getOpcode() == llvm::Instruction::GetElementPtr) {
     // FIXME: Support inbounds GEPs.
     llvm::GetElementPtrInst *gep = cast<llvm::GetElementPtrInst>(inst);
     Value basePtr = processValue(gep->getOperand(0));
     Type sourceElementType = convertType(gep->getSourceElementType());
 
     // Treat every indices as dynamic since GEPOp::build will refine those
     // indices into static attributes later. One small downside of this

mlir/test/Target/LLVMIR/Import/basic.ll

define void @variadic_function(i32 %X, ...) {
   ; CHECK: llvm.intr.vaend %[[CAST1]]
   call void @llvm.va_end(i8* %aq2)
 
   ; CHECK: llvm.intr.vaend %[[CAST0]]
   call void @llvm.va_end(i8* %ap2)
   ; CHECK: llvm.return
   ret void
 }
-
-; CHECK-LABEL: llvm.func @atomic_rmw
-define void @atomic_rmw(i32* %ptr0, i32 %v, float* %ptr1, float %f) {
-  ; CHECK: llvm.atomicrmw add %arg0, %arg1 acquire  : i32
-  %1 = atomicrmw add i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw add %arg0, %arg1 release  : i32
-  %2 = atomicrmw add i32* %ptr0, i32 %v release
-
-  ; CHECK: llvm.atomicrmw sub %arg0, %arg1 acquire  : i32
-  %3 = atomicrmw sub i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw xchg %arg0, %arg1 acquire  : i32
-  %4 = atomicrmw xchg i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw _and %arg0, %arg1 acquire  : i32
-  %5 = atomicrmw and i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw nand %arg0, %arg1 acquire  : i32
-  %6 = atomicrmw nand i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw _or %arg0, %arg1 acquire  : i32
-  %7 = atomicrmw or i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw _xor %arg0, %arg1 acquire  : i32
-  %8 = atomicrmw xor i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw max %arg0, %arg1 acquire  : i32
-  %9 = atomicrmw max i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw min %arg0, %arg1 acquire  : i32
-  %10 = atomicrmw min i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw umax %arg0, %arg1 acquire  : i32
-  %11 = atomicrmw umax i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw umin %arg0, %arg1 acquire  : i32
-  %12 = atomicrmw umin i32* %ptr0, i32 %v acquire
-  ; CHECK: llvm.atomicrmw fadd %arg2, %arg3 acquire  : f32
-  %13 = atomicrmw fadd float* %ptr1, float %f acquire
-  ; CHECK: llvm.atomicrmw fsub %arg2, %arg3 acquire  : f32
-  %14 = atomicrmw fsub float* %ptr1, float %f acquire
-  ret void
-}
-
-; CHECK-LABEL: llvm.func @atomic_cmpxchg
-define void @atomic_cmpxchg(i32* %ptr0, i32 %v, i32 %c) {
-  ; CHECK: llvm.cmpxchg %arg0, %arg2, %arg1 seq_cst seq_cst : i32
-  %1 = cmpxchg i32* %ptr0, i32 %c, i32 %v seq_cst seq_cst
-  ; CHECK: llvm.cmpxchg %arg0, %arg2, %arg1 monotonic seq_cst : i32
-  %2 = cmpxchg i32* %ptr0, i32 %c, i32 %v monotonic seq_cst
-  ret void
-}

mlir/test/Target/LLVMIR/Import/instructions.ll

define void @load_store(double* %ptr) {
   ; CHECK:  llvm.store %[[V1]], %[[PTR]] : !llvm.ptr<f64>
   %1 = load double, double* %ptr
   store double %1, double* %ptr
   ret void
 }
 
 ; // -----
 
+; CHECK-LABEL: @atomic_rmw
+; CHECK-SAME:  %[[PTR1:[a-zA-Z0-9]+]]
+; CHECK-SAME:  %[[VAL1:[a-zA-Z0-9]+]]
+; CHECK-SAME:  %[[PTR2:[a-zA-Z0-9]+]]
+; CHECK-SAME:  %[[VAL2:[a-zA-Z0-9]+]]
+define void @atomic_rmw(i32* %ptr1, i32 %val1, float* %ptr2, float %val2) {
+  ; CHECK:  llvm.atomicrmw xchg %[[PTR1]], %[[VAL1]] acquire  : i32
+  %1 = atomicrmw xchg i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw add %[[PTR1]], %[[VAL1]] release  : i32
+  %2 = atomicrmw add i32* %ptr1, i32 %val1 release
+  ; CHECK:  llvm.atomicrmw sub %[[PTR1]], %[[VAL1]] acq_rel  : i32
+  %3 = atomicrmw sub i32* %ptr1, i32 %val1 acq_rel
+  ; CHECK:  llvm.atomicrmw _and %[[PTR1]], %[[VAL1]] seq_cst  : i32
+  %4 = atomicrmw and i32* %ptr1, i32 %val1 seq_cst
+  ; CHECK:  llvm.atomicrmw nand %[[PTR1]], %[[VAL1]] acquire  : i32
+  %5 = atomicrmw nand i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw _or %[[PTR1]], %[[VAL1]] acquire  : i32
+  %6 = atomicrmw or i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw _xor %[[PTR1]], %[[VAL1]] acquire  : i32
+  %7 = atomicrmw xor i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw max %[[PTR1]], %[[VAL1]] acquire  : i32
+  %8 = atomicrmw max i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw min %[[PTR1]], %[[VAL1]] acquire  : i32
+  %9 = atomicrmw min i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw umax %[[PTR1]], %[[VAL1]] acquire  : i32
+  %10 = atomicrmw umax i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw umin %[[PTR1]], %[[VAL1]] acquire  : i32
+  %11 = atomicrmw umin i32* %ptr1, i32 %val1 acquire
+  ; CHECK:  llvm.atomicrmw fadd %[[PTR2]], %[[VAL2]] acquire  : f32
+  %12 = atomicrmw fadd float* %ptr2, float %val2 acquire
+  ; CHECK:  llvm.atomicrmw fsub %[[PTR2]], %[[VAL2]] acquire  : f32
+  %13 = atomicrmw fsub float* %ptr2, float %val2 acquire
+  ret void
+}
+
+; // -----
+
+; CHECK-LABEL: @atomic_cmpxchg
+; CHECK-SAME:  %[[PTR1:[a-zA-Z0-9]+]]
+; CHECK-SAME:  %[[VAL1:[a-zA-Z0-9]+]]
+; CHECK-SAME:  %[[VAL2:[a-zA-Z0-9]+]]
+define void @atomic_cmpxchg(i32* %ptr1, i32 %val1, i32 %val2) {
+  ; CHECK:  llvm.cmpxchg %[[PTR1]], %[[VAL1]], %[[VAL2]] seq_cst seq_cst : i32
+  %1 = cmpxchg i32* %ptr1, i32 %val1, i32 %val2 seq_cst seq_cst
+  ; CHECK:  llvm.cmpxchg %[[PTR1]], %[[VAL1]], %[[VAL2]] monotonic seq_cst : i32
+  %2 = cmpxchg i32* %ptr1, i32 %val1, i32 %val2 monotonic seq_cst
+  ret void
+}
+
+; // -----
+
 ; CHECK-LABEL: @freeze
 ; CHECK-SAME:  %[[ARG1:[a-zA-Z0-9]+]]
 define void @freeze(i32 %arg1) {
   ; CHECK:  %[[UNDEF:[0-9]+]] = llvm.mlir.undef : i64
   ; CHECK:  llvm.freeze %[[ARG1]] : i32
   ; CHECK:  llvm.freeze %[[UNDEF]] : i64
   %1 = freeze i32 %arg1
   %2 = freeze i64 undef