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[RISCV] Use hasAllWUsers to recover XORI/ORI
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Authored by liaolucy on Oct 9 2022, 6:53 AM.

Details

Summary

reference 0fbe71e91f44.

Also add testcase for addi.

Diff Detail

Event Timeline

liaolucy created this revision.Oct 9 2022, 6:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 9 2022, 6:53 AM
liaolucy requested review of this revision.Oct 9 2022, 6:53 AM
liaolucy added inline comments.Oct 9 2022, 6:54 AM
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
125

looks good, no need to optimize.

craig.topper added inline comments.Oct 9 2022, 10:08 AM
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
125

The ADDI being before the SUBW probably means this didn’t test what it was supposed to.

159

Add blank line

craig.topper accepted this revision.Oct 9 2022, 10:51 PM

LGTM if you add the blank line to the test as I noted previously.

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
125

I attempted to make ADDI file but I haven't been able to.

This revision is now accepted and ready to land.Oct 9 2022, 10:51 PM
liaolucy added inline comments.Oct 9 2022, 10:54 PM
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
125

https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L2597 add and sub use SimplifyDemandedBits.

Step4 of ISel: Optimized type-legalized selection DAG use SimplifyDemandedBits.

For addi:
Step2 of ISel: Optimized lowered selection DAG put the ADD before the SUB. So it doesn't trigger

Actually, I was just thinking about deleting the test

liaolucy updated this revision to Diff 466426.Oct 9 2022, 11:00 PM

Add blank line

This revision was landed with ongoing or failed builds.Oct 9 2022, 11:16 PM
This revision was automatically updated to reflect the committed changes.