[RISCV] Use hasAllWUsers to recover XORI/ORI

[liaolucy]

Summary

reference 0fbe71e91f44.

Also add testcase for addi.

[liaolucy]

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

125

looks good, no need to optimize.

[craig.topper]

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

125

The ADDI being before the SUBW probably means this didn’t test what it was supposed to.

159

Add blank line

[craig.topper]

LGTM if you add the blank line to the test as I noted previously.

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

125

I attempted to make ADDI file but I haven't been able to.

[liaolucy]

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

125

https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L2597 add and sub use SimplifyDemandedBits.

Step4 of ISel: Optimized type-legalized selection DAG use SimplifyDemandedBits.

For addi:
Step2 of ISel: Optimized lowered selection DAG put the ADD before the SUB. So it doesn't trigger

Actually, I was just thinking about deleting the test

[liaolucy]

Add blank line

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 // this has happened. We could try to detect that the CSE opportunity exists
 // before doing this, but that would be more complicated.
 // TODO: Does this need to look through AND/OR/XOR to their users to find more
 // opportunities.
 bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
   assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB ||
           Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
           Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::AND ||
+          Node->getOpcode() == ISD::OR || Node->getOpcode() == ISD::XOR ||
           Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
           isa<ConstantSDNode>(Node)) &&
          "Unexpected opcode");
 
   for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {
     SDNode *User = *UI;
     // Users of this node should have already been instruction selected
     if (!User->isMachineOpcode())

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // If this is a shr of a value sign extended from i32, and all the users only
 // use the lower 32 bits, we can use an sraiw to remove the sext_inreg. This
 // occurs because SimplifyDemandedBits prefers srl over sra.
 def : Pat<(binop_allwusers<srl> (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
           (SRAIW GPR:$rs1, uimm5:$shamt)>;
 
 // Use binop_allwusers to recover immediates that may have been broken by
 // SimplifyDemandedBits.
-// TODO: This is valid for ADDI/ORI/XORI.
 def : Pat<(binop_allwusers<and> GPR:$rs1, u32simm12:$imm),
           (ANDI GPR:$rs1, u32simm12:$imm)>;
 
+def : Pat<(binop_allwusers<or> GPR:$rs1, u32simm12:$imm),
+          (ORI GPR:$rs1, u32simm12:$imm)>;
+
+def : Pat<(binop_allwusers<xor> GPR:$rs1, u32simm12:$imm),
+          (XORI GPR:$rs1, u32simm12:$imm)>;
 /// Loads
 
 defm : LdPat<sextloadi32, LW, i64>;
 defm : LdPat<extloadi32, LW, i64>;
 defm : LdPat<zextloadi32, LWU, i64>;
 defm : LdPat<load, LD, i64>;
 
 /// Stores

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

 ; CHECK-NEXT:    sw a0, 0(a2)
 ; CHECK-NEXT:    ret
   %4 = and i32 %0, -8
   %5 = sub i32 %4, %1
   store i32 %5, ptr %2, align 4
   ret i32 %5
 }
 
+define signext i32 @addi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: addi_sub_cse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    addiw a0, a0, -8
+; CHECK-NEXT:    sw a0, 0(a2)
+; CHECK-NEXT:    ret
+  %4 = add i32 %0, -8
+  %5 = sub i32 %4, %1
+  store i32 %5, ptr %2, align 4
+  ret i32 %5
+}
+
+define signext i32 @xori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: xori_sub_cse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xori a0, a0, -8
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    sw a0, 0(a2)
+; CHECK-NEXT:    ret
+  %4 = xor i32 %0, -8
+  %5 = sub i32 %4, %1
+  store i32 %5, ptr %2, align 4
+  ret i32 %5
+}
+
+define signext i32 @ori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {
+; CHECK-LABEL: ori_sub_cse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ori a0, a0, -8
+; CHECK-NEXT:    subw a0, a0, a1
+; CHECK-NEXT:    sw a0, 0(a2)
+; CHECK-NEXT:    ret
+  %4 = or i32 %0, -8
+  %5 = sub i32 %4, %1
+  store i32 %5, ptr %2, align 4
+  ret i32 %5
+}
 ; SimplifyDemandedBits breaks the ANDI by turning -8 into 0xfffffff8. This
 ; gets CSEd with the AND needed for type legalizing the lshr. This increases
 ; the use count of the AND with 0xfffffff8 making TargetShrinkDemandedConstant
 ; unable to restore it to 0xffffffff for the lshr and -8 for the AND to use
 ; ANDI.
 ; Instead we rely on ISel to form srliw even though the AND has multiple uses
 ; and the mask has missing 1s where bits will be shifted out. This reduces the
 ; use count of the AND and we can use hasAllWUsers to form ANDI.
 define signext i32 @andi_srliw(i32 signext %0, ptr %1, i32 signext %2) {