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[RISCV] Remove some vsetvli intrinsics under Zve32*.
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Authored by craig.topper on Oct 8 2022, 1:02 PM.

Details

Summary

Zve32* does not support SEW=64. Or any LMUL smaller than 32/SEW.

Diff Detail

Event Timeline

craig.topper created this revision.Oct 8 2022, 1:02 PM
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craig.topper requested review of this revision.Oct 8 2022, 1:02 PM
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eopXD accepted this revision.Oct 8 2022, 1:41 PM

Looks good to me. I think this should solve https://github.com/riscv/riscv-v-spec/issues/832.

This revision is now accepted and ready to land.Oct 8 2022, 1:41 PM
This revision was automatically updated to reflect the committed changes.