[AArch64] Support SETCCCARRY lowering

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Summary

Support SETCCCARRY lowering to SBCS instruction.

Related issue: https://github.com/llvm/llvm-project/issues/44629

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Updated tests

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llvm/test/CodeGen/AArch64/i128-cmp.ll

24

Also checking if it's possible to use setcccarry to lower setcc eq/ne. It seems like it may improve code on x86, ARM and AArch64, but I'd prefer fixing it separately.

[efriedma]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

Do we ever actually use SETCCCARRY for i32 on targets where i64 is legal?

llvm/test/CodeGen/AArch64/i128-cmp.ll

24

Not sure how you could use setcccarry for equality; the carry bit doesn't contain enough information. You need something more like the AArch64 ccmp.

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

SelectionDAGLegalize::LegalizeOp uses default case to handle SETCCCARRY and calls TLI.getOperationAction with SETCCCARRY's type (which is i32). I guess that this question never arose previously because for other targets there were either no 64-bit registers (ARM), or because various value types were supported (X86, M86k).

Not sure if it should be fixed along with this change or via separate commit.

llvm/test/CodeGen/AArch64/i128-cmp.ll

24

Correct me if I'm wrong, but SETCCCARRY is like a regular SETCC which takes carry flag into account when comparing values. So we can generate the carry flag by comparing/subtracting registers holding least significant bits of i128 and then use SETCCCARRY to compare registers holding most significant bits (exactly how it works for other CCs).

It would be something like:

cmp x2, x0
sbcs xzr, x3, x1
cset w0, eq

Of course, on AArch64 sbcs in this case could be replaced with ccmp, but by using SETCCCARRY we can also improve code generated for other targets (X86 in particular). For targets supporting conditional comparisons (ARM, AArch64) SETCCARRY could then be replaced with more appropriate instruction.

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

Oh, I see what you mean. The current way is fine; just wasn't really thinking about the output type.

llvm/test/CodeGen/AArch64/i128-cmp.ll

24

cmp x2, x0
sbcs xzr, x3, x1
cset w0, eq

Equality would generally mean x2 equals x0 and x3 equals x1. This throws away the equality bit of the first comparison, and adding the carry bit to the second comparison just means it returns "equal" in some cases where x3 and x1 aren't equal.

If you try to run some actual examples, I'm sure you'll see what I mean.

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

I'm not sure that it supposed to work this way, because while SelectionDAGLegalize::LegalizeOp looks at SETCCCARRY's output type, DAGTypeLegalizer::IntegerExpandSetCCOperands uses operand's type.

llvm/test/CodeGen/AArch64/i128-cmp.ll

24

Got it, thanks!

[efriedma]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

Oh, hmm. They should use the same type; that's probably worth fixing. (I don't think it causes a practical problem here, but it could in other cases.)

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

Sure, I'll fix it first then, thanks!

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Use operand's type to query SETCCCARRY legalize action

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

417

Added fix to this change as there were no other way to test its correctness.

[efriedma]

LGTM