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fzhinkin (Filipp Zhinkin)
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Aug 18 2021, 3:11 PM (66 w, 3 d)

Recent Activity

Oct 14 2022

fzhinkin committed rGef774bec63b7: [AArch64] Support SETCCCARRY lowering (authored by fzhinkin).
[AArch64] Support SETCCCARRY lowering
Oct 14 2022, 12:30 PM · Restricted Project, Restricted Project
fzhinkin closed D135302: [AArch64] Support SETCCCARRY lowering.
Oct 14 2022, 12:29 PM · Restricted Project, Restricted Project

Oct 8 2022

fzhinkin added inline comments to D135302: [AArch64] Support SETCCCARRY lowering.
Oct 8 2022, 3:10 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D135302: [AArch64] Support SETCCCARRY lowering.

Use operand's type to query SETCCCARRY legalize action

Oct 8 2022, 3:09 AM · Restricted Project, Restricted Project

Oct 7 2022

fzhinkin added inline comments to D135302: [AArch64] Support SETCCCARRY lowering.
Oct 7 2022, 11:13 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D135302: [AArch64] Support SETCCCARRY lowering.
Oct 7 2022, 10:44 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D135302: [AArch64] Support SETCCCARRY lowering.
Oct 7 2022, 9:39 AM · Restricted Project, Restricted Project

Oct 6 2022

fzhinkin published D135302: [AArch64] Support SETCCCARRY lowering for review.
Oct 6 2022, 12:28 AM · Restricted Project, Restricted Project

Oct 5 2022

fzhinkin committed rG1888dc91ac87: [AArch64] Add tests for i128 comparison; NFC (authored by fzhinkin).
[AArch64] Add tests for i128 comparison; NFC
Oct 5 2022, 1:12 PM · Restricted Project, Restricted Project

Oct 1 2022

fzhinkin committed rG945a1468c922: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr (authored by fzhinkin).
[ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr
Oct 1 2022, 2:42 AM · Restricted Project, Restricted Project
fzhinkin closed D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.
Oct 1 2022, 2:41 AM · Restricted Project, Restricted Project

Sep 26 2022

fzhinkin added a comment to D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.

Looks pretty good to me, but maybe give the other reviewers some time for another look.

Sep 26 2022, 2:55 AM · Restricted Project, Restricted Project

Sep 17 2022

fzhinkin updated the diff for D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.

Introduced additional patterns to allow handing of shift+cmp by the peephole

Sep 17 2022, 1:51 AM · Restricted Project, Restricted Project
fzhinkin committed rGfa67e281b2f0: [ARM] Add more tests on instructions fusion with comparison with zero; NFC (authored by fzhinkin).
[ARM] Add more tests on instructions fusion with comparison with zero; NFC
Sep 17 2022, 1:50 AM · Restricted Project, Restricted Project

Sep 9 2022

fzhinkin added inline comments to D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.
Sep 9 2022, 4:35 AM · Restricted Project, Restricted Project

Sep 8 2022

fzhinkin added inline comments to D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.
Sep 8 2022, 12:47 PM · Restricted Project, Restricted Project
fzhinkin added inline comments to D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.
Sep 8 2022, 10:26 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr.

Rebase

Sep 8 2022, 10:25 AM · Restricted Project, Restricted Project
fzhinkin committed rGc4d0509e3b32: [ARM] Add tests on instructions fusion with comparison with zero; NFC (authored by fzhinkin).
[ARM] Add tests on instructions fusion with comparison with zero; NFC
Sep 8 2022, 10:25 AM · Restricted Project, Restricted Project

Sep 6 2022

fzhinkin published D131786: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr for review.
Sep 6 2022, 11:29 AM · Restricted Project, Restricted Project

Aug 12 2022

fzhinkin committed rG1626ee6a9581: [DAGCombine] Hoist shifts out of a logic operations tree. (authored by fzhinkin).
[DAGCombine] Hoist shifts out of a logic operations tree.
Aug 12 2022, 2:42 AM · Restricted Project, Restricted Project
fzhinkin closed D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 12 2022, 2:42 AM · Restricted Project, Restricted Project

Aug 9 2022

fzhinkin added inline comments to D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 9 2022, 11:34 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D131189: [DAGCombine] Hoist shifts out of a logic operations tree..

Rebase

Aug 9 2022, 11:33 AM · Restricted Project, Restricted Project
fzhinkin committed rGea323a4bd514: [X86][ARM] Update tests for bitwise logic trees of shifts; NFC (authored by fzhinkin).
[X86][ARM] Update tests for bitwise logic trees of shifts; NFC
Aug 9 2022, 10:58 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D131189: [DAGCombine] Hoist shifts out of a logic operations tree..

Updated x86 tests

Aug 9 2022, 1:49 AM · Restricted Project, Restricted Project

Aug 8 2022

fzhinkin updated the diff for D131189: [DAGCombine] Hoist shifts out of a logic operations tree..

Rebase

Aug 8 2022, 12:43 PM · Restricted Project, Restricted Project
fzhinkin committed rG6c52f82d77a1: [X86][ARM] Add tests for bitwise logic trees of shifts; NFC (authored by fzhinkin).
[X86][ARM] Add tests for bitwise logic trees of shifts; NFC
Aug 8 2022, 11:09 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 8 2022, 2:26 AM · Restricted Project, Restricted Project
fzhinkin updated the summary of D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 8 2022, 2:24 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D131189: [DAGCombine] Hoist shifts out of a logic operations tree..

Rebase

Aug 8 2022, 2:24 AM · Restricted Project, Restricted Project

Aug 6 2022

fzhinkin added a comment to D130994: [DAGCombiner] Hoist funnel shifts from logic operation..

LGTM
I'll push this for you if there are no other comments.
You could request commit access now (given your patch history, I don't think there would be a problem):
https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access

Aug 6 2022, 2:28 AM · Restricted Project, Restricted Project

Aug 5 2022

fzhinkin added a comment to D130994: [DAGCombiner] Hoist funnel shifts from logic operation..

Please pre-commit the new tests with baseline results, so we'll just show the diffs in this patch.

Unfortunately, I don't have a permission to commit. Here's a patch adding tests with checks generated using llc build from the main branch:

.

I'll appreciate if you can help me with committing it.

Sure: 249a7ed75072

Aug 5 2022, 10:38 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D130994: [DAGCombiner] Hoist funnel shifts from logic operation..

Rebase

Aug 5 2022, 10:37 AM · Restricted Project, Restricted Project
fzhinkin added a comment to D130994: [DAGCombiner] Hoist funnel shifts from logic operation..

Please pre-commit the new tests with baseline results, so we'll just show the diffs in this patch.

Aug 5 2022, 5:06 AM · Restricted Project, Restricted Project
fzhinkin updated the summary of D130994: [DAGCombiner] Hoist funnel shifts from logic operation..
Aug 5 2022, 4:58 AM · Restricted Project, Restricted Project

Aug 4 2022

fzhinkin updated the summary of D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 4 2022, 11:37 AM · Restricted Project, Restricted Project
fzhinkin requested review of D131189: [DAGCombine] Hoist shifts out of a logic operations tree..
Aug 4 2022, 11:35 AM · Restricted Project, Restricted Project

Aug 2 2022

fzhinkin updated the summary of D130994: [DAGCombiner] Hoist funnel shifts from logic operation..
Aug 2 2022, 9:21 AM · Restricted Project, Restricted Project
fzhinkin requested review of D130994: [DAGCombiner] Hoist funnel shifts from logic operation..
Aug 2 2022, 9:19 AM · Restricted Project, Restricted Project

May 2 2022

fzhinkin abandoned D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
May 2 2022, 1:58 AM · Restricted Project, Restricted Project
fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

@fzhinkin @spatel Is this patch still relevant?

May 2 2022, 1:57 AM · Restricted Project, Restricted Project

Mar 9 2022

fzhinkin accepted D120933: [SDAG] match rotate pattern with extra 'or' operation.
Mar 9 2022, 6:19 AM · Restricted Project, Restricted Project

Feb 23 2022

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

@spatel I remembered why I didn't add a transformation into DAGCombiner and decided to perform specific transformation in TargetLowering::SimplifySetCC:

  • to remove unnecessary shifts we have to know that legalized shift was an input of setcc eq/ne 0 and expanded shifts are not yet combined when DAGCombiner is visiting setcc;
  • and it's actually better to apply the optimization before shifts combining because for some targets shifts could be combined to some target-specific node instead of a funnel shift (for example, for AArch64 shifts implemening funnel shift will be combined into EXTR node instead of FSHL/FSHR).
Feb 23 2022, 9:21 AM · Restricted Project, Restricted Project
fzhinkin accepted D120253: [InstSimplify] remove shift that is redundant with part of funnel shift.
Feb 23 2022, 5:42 AM · Restricted Project

Feb 18 2022

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

I didn't step through everything here, so I may not be seeing the entire problem.

There are 2 or more relatively simple folds that are missing both in IR and DAG, and adding those might solve this more generally and more easily than the proposed patch.

Here are examples in Alive2:
https://alive2.llvm.org/ce/z/KNQuYm
https://alive2.llvm.org/ce/z/LKLpo3

So it might be possible to solve the motivating bug without starting from icmp/setcc -- it's really a problem of combining shifts and funnel shifts in a way that is better for analysis/codegen.

Transformation from this change is not only about shifts recombination but (and mostly) about removal of shifts that will rotate bits of a value compared with zero. In that particular case such shifts could be safely eliminated, but in any other case it's not possible as it will change the result.

By combining shifts differently (by replacing shift + funnel shift with rotate + shift, for example) we can improve performance on some platforms, but the case with icmp eq/ne 0 would still have to be handled separately as it allow transformation that is illegal otherwise.

Feb 18 2022, 10:15 AM · Restricted Project, Restricted Project
fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

I didn't step through everything here, so I may not be seeing the entire problem.

There are 2 or more relatively simple folds that are missing both in IR and DAG, and adding those might solve this more generally and more easily than the proposed patch.

Here are examples in Alive2:
https://alive2.llvm.org/ce/z/KNQuYm
https://alive2.llvm.org/ce/z/LKLpo3

So it might be possible to solve the motivating bug without starting from icmp/setcc -- it's really a problem of combining shifts and funnel shifts in a way that is better for analysis/codegen.

Feb 18 2022, 9:50 AM · Restricted Project, Restricted Project

Feb 16 2022

fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Pass SDValue by value.

Feb 16 2022, 1:18 PM · Restricted Project, Restricted Project

Feb 8 2022

fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Move most of optimization's code into helper class.

Feb 8 2022, 12:04 PM · Restricted Project, Restricted Project

Feb 7 2022

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Feb 7 2022, 11:08 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Rebase

Feb 7 2022, 12:53 AM · Restricted Project, Restricted Project

Jan 17 2022

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Jan 17 2022, 9:53 AM · Restricted Project, Restricted Project

Jan 14 2022

fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Cleanup

Jan 14 2022, 9:48 AM · Restricted Project, Restricted Project

Jan 12 2022

fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Reordered MergeConcat and optimizeSetCCOfExpandedShift optimizations.

Jan 12 2022, 9:50 AM · Restricted Project, Restricted Project

Dec 7 2021

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Dec 7 2021, 11:11 AM · Restricted Project, Restricted Project

Nov 22 2021

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 22 2021, 10:11 AM · Restricted Project, Restricted Project

Nov 17 2021

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 17 2021, 12:32 PM · Restricted Project, Restricted Project

Nov 8 2021

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 8 2021, 8:47 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Rebase

Nov 8 2021, 8:28 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Rebase

Nov 8 2021, 7:10 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 8 2021, 6:55 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 8 2021, 1:06 AM · Restricted Project, Restricted Project

Nov 3 2021

fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Simplified expression in assertion.

Nov 3 2021, 12:28 PM · Restricted Project, Restricted Project
fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 3 2021, 7:31 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Cleanup

Nov 3 2021, 7:28 AM · Restricted Project, Restricted Project
fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Nov 3 2021, 4:26 AM · Restricted Project, Restricted Project
fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

X86 changes look good. Are AArch64 changes actually a regressions, or are they just changes?

Thanks!
There is no regression for AArch64: better code sequence is generated for legalized i128 shifts, but there is no improvement for wider types (like i256).

A change that only triggers for some (common?) cases and causes no regressions is a better step forward
than a change that indiscriminately triggers on everything and causes widespread regressions i would think :)

Nov 3 2021, 12:47 AM · Restricted Project, Restricted Project

Nov 2 2021

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

X86 changes look good. Are AArch64 changes actually a regressions, or are they just changes?

Nov 2 2021, 2:07 PM · Restricted Project, Restricted Project
fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Instead I supported funnel shifts TargetLowering::optimizeSetCCOfExpandedShift (did not support rotations and bit/byte swaps because such nodes should not be created during expanded shift's combining).

While optimization works fine for i686 now there is an issue with AArch64: shifts expanded from types wider than i128 won't be optimized (see @opt_setcc_shl_ne_zero_i256) because for AArch64 funnel shift alike patterns combined into AArch64ISD::EXTR instead of FSHL/FSHR. I attempted to fix it by implementing (2), but the solution was fragile and didn't work in some cases.

I'm hoping D112443 will help with this

D112443 has been committed - please can you see if it helps?

Nov 2 2021, 1:31 PM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Rebase

Nov 2 2021, 1:28 PM · Restricted Project, Restricted Project

Nov 1 2021

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Handling of trees generated during legalization of i128/i256/etc to i32 is relatively simple, but in case of i686 some of these expressions are folded into funnel shifts before SimplifySetCC is applied to setcc.
I see two options here (but I'm far from being an expert, so correct me if I'm wrong and there are simpler alternatives):

  1. support various instructions (funnel shifts, rotations, bit/byte swaps) in TargetLowering::optimizeSetCCOfExpandedShift in addition to SHL/SRL;
  2. support only SHL/SRL in TargetLowering::optimizeSetCCOfExpandedShift and apply it in DAGTypeLegalizer::IntegerExpandSetCCOperands right after setcc's operands expansion.

Personally I'm leaning towards second option as it should be less fragile and easier to maintain.

Makes sense to try (2) first - although I expect at least partial support for (1) might end up being required - you are handling a pattern that is almost a funnel shift much of the time.

Nov 1 2021, 12:26 PM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Reimplemented expanded shift matching to handle funnel shifts.

Nov 1 2021, 12:12 PM · Restricted Project, Restricted Project

Oct 25 2021

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

please can you pre-commit these new tests to trunk with current codegen and then rebase to show the diff?

I don't have a permission to commit changes, so I'll appreciate if you can help me with it. Here's the patch adding new tests with checks generated for current trunk:

Done (sorry for the delay) - please can you rebase?

Thank you! Rebase done.

Also, thanks for adding i686 to X86's test, it revealed that my optimization does not work when we're legalizing i128 to i32. I'll check if that case could be easily supported.

Oct 25 2021, 1:59 AM · Restricted Project, Restricted Project

Oct 22 2021

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

please can you pre-commit these new tests to trunk with current codegen and then rebase to show the diff?

I don't have a permission to commit changes, so I'll appreciate if you can help me with it. Here's the patch adding new tests with checks generated for current trunk:

Done (sorry for the delay) - please can you rebase?

Oct 22 2021, 8:17 AM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Rebased to current trunk

Oct 22 2021, 8:12 AM · Restricted Project, Restricted Project

Oct 20 2021

fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

please can you pre-commit these new tests to trunk with current codegen and then rebase to show the diff?

Oct 20 2021, 1:38 PM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Fixed typos in ARM tests.

Oct 20 2021, 1:38 PM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Renamed test files, added nounwind attribute.

Oct 20 2021, 12:09 PM · Restricted Project, Restricted Project
fzhinkin added a comment to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Ping

Oct 20 2021, 12:52 AM · Restricted Project, Restricted Project

Oct 11 2021

fzhinkin added inline comments to D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Oct 11 2021, 2:18 PM · Restricted Project, Restricted Project
fzhinkin updated the diff for D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.

Fixed typos, cleaned up the code.

Oct 11 2021, 2:17 PM · Restricted Project, Restricted Project
fzhinkin retitled D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0 from [TargetLowering] Optimize expanded SRL/SHL feeded into SETCC ne/eq 0 to [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Oct 11 2021, 3:15 AM · Restricted Project, Restricted Project
fzhinkin requested review of D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0.
Oct 11 2021, 3:12 AM · Restricted Project, Restricted Project

Sep 12 2021

fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Sep 12 2021, 2:48 AM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Fixed the test w/ icmp ne by preventing icmp's transformation.

Sep 12 2021, 2:37 AM · Restricted Project

Sep 11 2021

fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Sep 11 2021, 1:53 AM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Updated comments, fixed few bugs.

Sep 11 2021, 1:52 AM · Restricted Project

Sep 10 2021

fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Sep 10 2021, 11:42 AM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Rebased changes.

Sep 10 2021, 11:42 AM · Restricted Project

Sep 9 2021

fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Sep 9 2021, 1:15 PM · Restricted Project
fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Sep 9 2021, 11:48 AM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Added comments to both transformation and tests, made multi-user test more readable.

Sep 9 2021, 11:44 AM · Restricted Project

Sep 5 2021

fzhinkin added a comment to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

ping

Sep 5 2021, 10:42 AM · Restricted Project

Aug 28 2021

fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Cleaned up the code, updated tests.

Aug 28 2021, 6:26 AM · Restricted Project
fzhinkin added inline comments to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Aug 28 2021, 4:05 AM · Restricted Project

Aug 25 2021

fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Replace original mul with mul using frozen input.

Aug 25 2021, 2:17 PM · Restricted Project
fzhinkin updated the summary of D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
Aug 25 2021, 11:45 AM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Supproted undef values in both condition's and select's arguments.

Aug 25 2021, 11:45 AM · Restricted Project

Aug 24 2021

fzhinkin added a comment to D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..
  1. what's wrong with vectors?

There's nothing wrong, I'll support it, thanks!

  1. can't we preserve no-wrap flags?

Definitely.

  1. for vectors, what if some element is not zero but undef? (see Constant::mergeUndefsWith())

Not sure that I fully understand the issue.
If %a in the snippet below contains some undefs then the select may choose either 0 or %m depending on particular value of a (which could be 0 for undef elements).
Probably %a should be frozen to ensure that both icmp and mul will see the same a's value, but (if I understood it correctly) absence of freeze does not compromise the correctness.

define <2 x i4> @src(<2 x i4> %a, <2 x i4> %b) {
  %c = icmp eq <2 x i4> %a, zeroinitializer
  %m = mul <2 x i4> %a, %b
  %r = select <2 x i1> %c, <2 x i4> zeroinitializer, <2 x i4> %m
  ret <2 x i4> %r
}

Or you meant that the code could be folded even if icmp's RHS is not only the all-zeros vector, but a constant-vector containing some undefs?

I mean that if in either zero constant vector, a particular element is undef, then in the other constant vector, the same element can be anything:
https://alive2.llvm.org/ce/z/-gt253
https://alive2.llvm.org/ce/z/3PAU3E

So i think you want if(!match(Constant::mergeUndefsWith(TrueVal, CondVal.getOperand(1)), m_Zero)) return;

Aug 24 2021, 12:12 PM · Restricted Project
fzhinkin updated the diff for D108408: [InstCombine] Transform X == 0 ? 0 : X * Y --> X * freeze(Y)..

Enabled folding for vectors, copied flags for mul, renamed tests.

Aug 24 2021, 10:44 AM · Restricted Project