[AMDGPU][GISel] Update `isCanonicalized`

[Pierre-vh]

Summary

Recognize more opcodes in the function.
Fixes some regressions introduced in D134857 for fdiv.f16 too.

Depends on D134857

[foad]

Fixes some regressions introduced in D134857 for fdiv.f16 too.

I don't see any real regressions in D134857, just cases where we optimize the "ieee" cases but not the "flush" cases.

[foad]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10202

It seems wrong for FNEG to fall into the "supportsMinMaxDenormModes" check below.

[Pierre-vh]

Fix unary ops
Also fixes the foldable-fneg test (no longer needs pre/post check lines)

[Pierre-vh]

In D134862#3823116, @foad wrote:

Fixes some regressions introduced in D134857 for fdiv.f16 too.

I don't see any real regressions in D134857, just cases where we optimize the "ieee" cases but not the "flush" cases.

Yes, that's what I meant - we had a split in the ieee/flush codegen but this fixes it :p

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10202

Indeed it was. Fixed it and also added the remaining unary operations while I was at it.

[foad]

LGTM. (I'm not 100% sure about G_FREM but I assume it expands to something that will flush denormals if appropriate?)

[Pierre-vh]

In D134862#3823194, @foad wrote:

LGTM. (I'm not 100% sure about G_FREM but I assume it expands to something that will flush denormals if appropriate?)

I think it's fine as this mimics the DAG's implementation. I can still remove FREM if you're not sure about it as I don't really need it added right now (I just added it for completeness).

[foad]

In D134862#3823304, @Pierre-vh wrote:

In D134862#3823194, @foad wrote:

LGTM. (I'm not 100% sure about G_FREM but I assume it expands to something that will flush denormals if appropriate?)

I think it's fine as this mimics the DAG's implementation. I can still remove FREM if you're not sure about it as I don't really need it added right now (I just added it for completeness).

I agree it's fine. It looks like it normally expands to some combination of div/mul/trunc/fma, i.e. normal fp instructions which will canonicalize.

[Pierre-vh]

Rebase on top of D134857

[arsenm]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10217–10218

I just realized this is broken since it was copied from the DAG with FP value types. In another patch can you explicitly handle the custom intrinsics?

Plus this isn't handling some of the less common generic opcodes, like all the different rounding functions

[Pierre-vh]

I'm not sure I understand, which intrinsics need to be handled? The ones in INTRINSIC_WO_CHAIN in the DAG version?
And what are the opcodes you're talking about? Things like CVT_F32?

[arsenm]

In D134862#3823579, @Pierre-vh wrote:

I'm not sure I understand, which intrinsics need to be handled? The ones in INTRINSIC_WO_CHAIN in the DAG version?
And what are the opcodes you're talking about? Things like CVT_F32?

Some of them are obscured by custom nodes in the DAG. Some examples are AMDGPUISD::FMAD_FTZ, AMDGPUISD::RCP (corresponding to llvm.amdgcn.rcp), and the cases in INTRINSIC_WO_CHAIN. Plus this is missing a number of the generic opcodes like G_FSQRT and G_FFLOOR

[Pierre-vh]

Handle more opcode/intrinsics

[arsenm]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10195

G_FRINT, G_NEARBYINT, G_INTRINSIC_FPTRUNC_ROUND, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN,

10223

amdgcn_sqrt, fmed3, fmad_ftz, sin, cos, log, log_clamp

10231

cubema, cubesc, cubetc?

10238

Should do separately and also introduce for the DAG path, but we're missing some of the newer operations like _amdgcn_cvt_f32_bf8

[Pierre-vh]

Add more missing instructions/intrinsics

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10223

fmad_ftz was already there, log doesn't seem to exit as an intrinsic but it's an instruction so I it + the variants:

case AMDGPU::G_FLOG:
case AMDGPU::G_FLOG2:
case AMDGPU::G_FLOG10:

[arsenm]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10206–10207

Also should handle G_FMINNUM/G_FMAXNUM. Also, we should really stop ascribing target instruction behavior to the generic opcodes. This is a separate patch though since this is a big mess

10217

Should default to return false

[Pierre-vh]

Comments

[Pierre-vh]

need a few more items

[Pierre-vh]

Add BUILD_VECTOR

[arsenm]

LGTM

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if (mi_match(Reg, MRI, MIPatternMatch::m_GFCstOrSplat(FCR))) {
     return !FCR->Value.isDenormal() ||
            denormalsEnabledForType(MRI.getType(FCR->VReg), MF);
   }
 
   if (MaxDepth == 0)
     return false;
 
   switch (Opcode) {
+  case AMDGPU::G_FADD:
+  case AMDGPU::G_FSUB:
+  case AMDGPU::G_FMUL:
+  case AMDGPU::G_FMA:
+  case AMDGPU::G_FMAD:
+  case AMDGPU::G_FDIV:
+  case AMDGPU::G_FREM:
+  case AMDGPU::G_FPOW:
+  case AMDGPU::G_FPEXT:
+  case AMDGPU::G_FPTRUNC:
+    return true;
+  case AMDGPU::G_FNEG:
+  case AMDGPU::G_FABS:
+  case AMDGPU::G_FCOPYSIGN:
+    return isCanonicalized(MI->getOperand(1).getReg(), MF, MaxDepth - 1);
   case AMDGPU::G_FMINNUM_IEEE:
   case AMDGPU::G_FMAXNUM_IEEE: {
     if (Subtarget->supportsMinMaxDenormModes() ||
         denormalsEnabledForType(MRI.getType(Reg), MF))
       return true;
     for (const MachineOperand &MO : llvm::drop_begin(MI->operands()))
       if (!isCanonicalized(MO.getReg(), MF, MaxDepth - 1))
         return false;
     return true;
   }
   default:
     return denormalsEnabledForType(MRI.getType(Reg), MF) &&
            isKnownNeverSNaN(Reg, MRI);
   }
 
   llvm_unreachable("invalid operation");
 }
 
 // Constant fold canonicalize.
 SDValue SITargetLowering::getCanonicalConstantFP(
   SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const {
   // Flush denormals to 0 if not enabled.
   if (C.isDenormal() && !denormalsEnabledForType(DAG, VT))
     return DAG.getConstantFP(0.0, SL, VT);
 
   if (C.isNaN()) {
     APFloat CanonicalQNaN = APFloat::getQNaN(C.getSemantics());
     if (C.isSignaling()) {
       // Quiet a signaling NaN.
       // FIXME: Is this supposed to preserve payload bits?
       return DAG.getConstantFP(CanonicalQNaN, SL, VT);
     }
 
     // Make sure it is the canonical NaN bitpattern.
     //
     // TODO: Can we use -1 as the canonical NaN value since it's an inline
     // immediate?
     if (C.bitcastToAPInt() != CanonicalQNaN.bitcastToAPInt())
       return DAG.getConstantFP(CanonicalQNaN, SL, VT);
   }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll

 ; GFX9-DENORM:       ; %bb.0: ; %.entry
 ; GFX9-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v2, v0, v4
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX9-DENORM-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_v4f16_sub_mul:
 ; GFX10:       ; %bb.0: ; %.entry
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-NEXT:    v_pk_mul_f16 v1, v1, v3

 ;
 ; GFX10-DENORM-LABEL: test_v4f16_sub_mul:
 ; GFX10-DENORM:       ; %bb.0: ; %.entry
 ; GFX10-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
 ; GFX10-DENORM-NEXT:    v_sub_f16_e32 v2, v0, v4
-; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX10-DENORM-NEXT:    s_setpc_b64 s[30:31]
 .entry:
   %a = fmul <4 x half> %x, %y
   %b = fsub <4 x half> %a, %z
   ret <4 x half> %b
 }
 
 define <4 x half> @test_v4f16_sub_mul_rhs(<4 x half> %x, <4 x half> %y, <4 x half> %z) {

 ; GFX9-DENORM:       ; %bb.0: ; %.entry
 ; GFX9-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v2, v4, v0
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v3, v5, v1
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX9-DENORM-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_v4f16_sub_mul_rhs:
 ; GFX10:       ; %bb.0: ; %.entry
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-NEXT:    v_pk_mul_f16 v1, v1, v3

 ;
 ; GFX10-DENORM-LABEL: test_v4f16_sub_mul_rhs:
 ; GFX10-DENORM:       ; %bb.0: ; %.entry
 ; GFX10-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3
 ; GFX10-DENORM-NEXT:    v_sub_f16_e32 v2, v4, v0
-; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v5, v1
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v5, v1
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX10-DENORM-NEXT:    s_setpc_b64 s[30:31]
 .entry:
   %a = fmul <4 x half> %x, %y
   %b = fsub <4 x half> %z, %a
   ret <4 x half> %b
 }
 
 define <4 x double> @test_v4f64_sub_mul(<4 x double> %x, <4 x double> %y, <4 x double> %z) {

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll

 ; GFX9-DENORM:       ; %bb.0: ; %entry
 ; GFX9-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
 ; GFX9-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v2, v0, v4
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; GFX9-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX9-DENORM-NEXT:    v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX9-DENORM-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_v4f16_sub_ext_neg_mul:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
 ; GFX10-NEXT:    v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]

 ;
 ; GFX10-DENORM-LABEL: test_v4f16_sub_ext_neg_mul:
 ; GFX10-DENORM:       ; %bb.0: ; %entry
 ; GFX10-DENORM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-DENORM-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
 ; GFX10-DENORM-NEXT:    v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
 ; GFX10-DENORM-NEXT:    v_sub_f16_e32 v2, v0, v4
-; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX10-DENORM-NEXT:    v_sub_f16_e32 v3, v1, v5
 ; GFX10-DENORM-NEXT:    v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-DENORM-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX10-DENORM-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-DENORM-NEXT:    v_pack_b32_f16 v1, v3, v1
 ; GFX10-DENORM-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %a = fmul <4 x half> %x, %y
   %b = fneg <4 x half> %a
   %c = fsub <4 x half> %b, %z
   ret <4 x half> %c
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK
 
 ---
 name:            test_fminnum
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: test_fminnum

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Denormal mode shouldn't matter for f16, check with and without flushing.
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-IEEE %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX6,GFX6-FLUSH %s
 
 ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s
 
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-IEEE %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-FLUSH %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s
 
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-IEEE %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-FLUSH %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
 
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-IEEE %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FLUSH %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
 
 define half @v_fdiv_f16(half %a, half %b) {
 ; GFX6-IEEE-LABEL: v_fdiv_f16:
 ; GFX6-IEEE:       ; %bb.0:
 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v1, v1, v0

 ; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GFX8-NEXT:    v_mul_f16_e32 v2, v0, v2
 ; GFX8-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 16
 ; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
 ; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-IEEE-LABEL: v_fdiv_v2f16_afn:
-; GFX9-IEEE:       ; %bb.0:
-; GFX9-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX9-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-FLUSH-LABEL: v_fdiv_v2f16_afn:
-; GFX9-FLUSH:       ; %bb.0:
-; GFX9-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-IEEE-LABEL: v_fdiv_v2f16_afn:
-; GFX10-IEEE:       ; %bb.0:
-; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-FLUSH-LABEL: v_fdiv_v2f16_afn:
-; GFX10-FLUSH:       ; %bb.0:
-; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-FLUSH-NEXT:    v_and_b32_e32 v1, 0xffff, v2
-; GFX10-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
-; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-IEEE-LABEL: v_fdiv_v2f16_afn:
-; GFX11-IEEE:       ; %bb.0:
-; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-IEEE-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-FLUSH-LABEL: v_fdiv_v2f16_afn:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-FLUSH-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FLUSH-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fdiv_v2f16_afn:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX9-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX9-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_v2f16_afn:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX10-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_v2f16_afn:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-NEXT:    v_rcp_f16_e32 v1, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_rcp_f16_e32 v2, v2
+; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_mul_f16_e32 v1, v3, v2
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv afn <2 x half> %a, %b
   ret <2 x half> %fdiv
 }
 
 define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
 ; GFX6-IEEE-LABEL: v_fdiv_v2f16_ulp25:
 ; GFX6-IEEE:       ; %bb.0:
 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GFX8-NEXT:    v_mul_f16_e32 v2, v0, v2
 ; GFX8-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 16
 ; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
 ; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX9-IEEE:       ; %bb.0:
-; GFX9-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX9-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX9-FLUSH:       ; %bb.0:
-; GFX9-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX10-IEEE:       ; %bb.0:
-; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX10-FLUSH:       ; %bb.0:
-; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-FLUSH-NEXT:    v_and_b32_e32 v1, 0xffff, v2
-; GFX10-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
-; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX11-IEEE:       ; %bb.0:
-; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-IEEE-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-FLUSH-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FLUSH-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX9-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX9-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX10-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_v2f16_afn_ulp25:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-NEXT:    v_rcp_f16_e32 v1, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_rcp_f16_e32 v2, v2
+; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_mul_f16_e32 v1, v3, v2
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0
   ret <2 x half> %fdiv
 }
 
 define <2 x half> @v_fdiv_v2f16_arcp_ulp25(<2 x half> %a, <2 x half> %b) {
 ; GFX6-IEEE-LABEL: v_fdiv_v2f16_arcp_ulp25:
 ; GFX6-IEEE:       ; %bb.0:
 ; GFX6-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX8-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
 ; GFX8-NEXT:    v_mul_f16_e32 v2, v0, v2
 ; GFX8-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v1, 16
 ; GFX8-NEXT:    v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
 ; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX9-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX9-IEEE:       ; %bb.0:
-; GFX9-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX9-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX9-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX9-FLUSH:       ; %bb.0:
-; GFX9-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX9-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX9-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
-; GFX9-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX10-IEEE:       ; %bb.0:
-; GFX10-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-IEEE-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-IEEE-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-IEEE-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-IEEE-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-IEEE-NEXT:    v_pack_b32_f16 v0, v2, v0
-; GFX10-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX10-FLUSH:       ; %bb.0:
-; GFX10-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-FLUSH-NEXT:    v_rcp_f16_e32 v2, v1
-; GFX10-FLUSH-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-FLUSH-NEXT:    v_mul_f16_e32 v2, v0, v2
-; GFX10-FLUSH-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-FLUSH-NEXT:    v_and_b32_e32 v1, 0xffff, v2
-; GFX10-FLUSH-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
-; GFX10-FLUSH-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX11-IEEE:       ; %bb.0:
-; GFX11-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-IEEE-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-IEEE-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-IEEE-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-IEEE-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-IEEE-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-IEEE-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-IEEE-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
-; GFX11-FLUSH:       ; %bb.0:
-; GFX11-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FLUSH-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v1, v1
-; GFX11-FLUSH-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-FLUSH-NEXT:    v_rcp_f16_e32 v2, v2
-; GFX11-FLUSH-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v0, v0, v1
-; GFX11-FLUSH-NEXT:    v_mul_f16_e32 v1, v3, v2
-; GFX11-FLUSH-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FLUSH-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FLUSH-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX9-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX9-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_rcp_f16_e32 v2, v1
+; GFX10-NEXT:    v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_mul_f16_e32 v2, v0, v2
+; GFX10-NEXT:    v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    v_pack_b32_f16 v0, v2, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_v2f16_arcp_afn_ulp25:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX11-NEXT:    v_rcp_f16_e32 v1, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-NEXT:    v_rcp_f16_e32 v2, v2
+; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_mul_f16_e32 v0, v0, v1
+; GFX11-NEXT:    v_mul_f16_e32 v1, v3, v2
+; GFX11-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv afn arcp <2 x half> %a, %b, !fpmath !0
   ret <2 x half> %fdiv
 }
 
 !0 = !{float 2.500000e+00}

llvm/test/CodeGen/AMDGPU/v_pack.ll

 ; GISEL-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GISEL-NEXT:    global_load_ushort v1, v0, s[0:1] glc dlc
 ; GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GISEL-NEXT:    global_load_ushort v2, v0, s[2:3] glc dlc
 ; GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GISEL-NEXT:    v_add_f16_e32 v0, 2.0, v1
 ; GISEL-NEXT:    v_add_f16_e32 v1, 2.0, v2
-; GISEL-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
-; GISEL-NEXT:    v_and_b32_e32 v1, 0x7fff, v1
-; GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GISEL-NEXT:    v_pack_b32_f16 v0, |v0|, |v1|
 ; GISEL-NEXT:    ;;#ASMSTART
 ; GISEL-NEXT:    ; use v0
 ; GISEL-NEXT:    ;;#ASMEND
 ; GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %in0.gep = getelementptr inbounds half, half addrspace(1)* %in0, i64 %tid.ext
   %in1.gep = getelementptr inbounds half, half addrspace(1)* %in1, i64 %tid.ext