[AMDGPU][GISel] Allow VReg srcs in (build_vector undef, i16) pattern

[Pierre-vh]

Summary

Fixes a regression in v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt.

Depends on D134354

[foad]

llvm/lib/Target/AMDGPU/SIInstructions.td

2740–2741

Why does this pattern use SReg_32? That doesn't make any sense to me.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstructions.td

2740–2741

The output should change to match.

It makes sense for the old DAG select everything to scalar and hack up to vector later approach

[foad]

llvm/lib/Target/AMDGPU/SIInstructions.td

2740–2741

Well I still don't get why it ever made sense. I know we used to select SALU instructions by default, but this is a VALU instruction with an SGPR operand. I thought we always used VGPR operands by default for VALU instructions, to avoid having to think about constant bus restrictions until SIFoldOperands.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstructions.td

2740–2741

The register class in the pattern used to mean less and was practically an alias for the type. There was a finalize ISel hook to fixup constant bus violations

[Pierre-vh]

Done as part of D136459 - results on codegen in D134354 are identical.

llvm/lib/Target/AMDGPU/SIInstructions.td

 >;
 
 def : GCNPat <
   (v2i16 (UniformBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
   (S_LSHL_B32 SReg_32:$src1, (i32 16))
 >;
 
 def : GCNPat <
-  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
+  (v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VS_32:$src1))),
   (v2i16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
 
 
 def : GCNPat <
   (v2f16 (UniformBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))),
   (S_LSHL_B32 SReg_32:$src1, (i32 16))
 >;
 
 def : GCNPat <
-  (v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))),
+  (v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 VS_32:$src1))),
   (v2f16 (V_LSHLREV_B32_e64 (i32 16), SReg_32:$src1))
 >;
 }
 
 let SubtargetPredicate = HasVOP3PInsts in {
 def : GCNPat <
   (v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
   (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)

llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll

; GISEL-CI-NEXT:    s_setpc_b64 s[30:31]
   %cvt.result = fptrunc float %result to half
   %bc = bitcast half %cvt.result to i16
   %ext = sext i16 %bc to i32
   %shr = shl i32 %ext, 16
   ret i32 %shr
 }
 
 define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
-; DAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; DAG-GFX9:       ; %bb.0:
-; DAG-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; DAG-GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; DAG-GFX9-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; DAG-GFX9-NEXT:    s_setpc_b64 s[30:31]
+; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; DAG-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
 ; DAG-VI:       ; %bb.0:
 ; DAG-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; DAG-VI-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; DAG-VI-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; DAG-VI-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; DAG-VI-NEXT:    v_mad_f32 v0, v0, v1, v2 clamp
 ; DAG-VI-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
 ; DAG-VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; DAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
 ; DAG-CI:       ; %bb.0:
 ; DAG-CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; DAG-CI-NEXT:    v_mad_f32 v0, v0, v1, v2 clamp
 ; DAG-CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; DAG-CI-NEXT:    v_cvt_f32_f16_e32 v1, v0
 ; DAG-CI-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GISEL-GFX9:       ; %bb.0:
-; GISEL-GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-GFX9-NEXT:    v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp
-; GISEL-GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GISEL-GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v0
-; GISEL-GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
-; GISEL-GFX9-NEXT:    s_setpc_b64 s[30:31]
-;
 ; GISEL-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
 ; GISEL-VI:       ; %bb.0:
 ; GISEL-VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GISEL-VI-NEXT:    v_cvt_f32_f16_e32 v2, v2
 ; GISEL-VI-NEXT:    v_mad_f32 v0, v0, v1, v2 clamp
 ; GISEL-VI-NEXT:    v_cvt_f16_f32_e32 v0, v0