[AArch64] Add a target feature for AArch64StorePairSuppress

[dmgreen]

Summary

The AArch64StorePairSuppress pass prevents the creation of STP under some heuristics. Unfortunately it often prevents the creation of STP in cases where it is obviously beneficial, and it doesn't match my understanding of scheduling/cpu pipelining to prevent the creation of STP. From some benchmarking, even on an in-order cpu where the scheduling is most important I don't see it giving better results. In general the lower instruction count for STP would be expected to give a slightly better cycle count.

As the pass specifically mentions the cyclone cpu, this patch adds a target feature for FeatureStorePairSuppress, enabled for all the non-Arm cpus. This has the effect of disabling it for all Arm cpus.

[Allen]

llvm/lib/Target/AArch64/AArch64.td

1031

TSV110 target is also expected to suppress pair stores

[dmgreen]

llvm/lib/Target/AArch64/AArch64.td

1031

OK good to know, I can change it. I am a little surprised it expected to be beneficial though. Do you have an example where it helped? Perhaps I am just running the wrong code to show where it is useful..

[Allen]

llvm/lib/Target/AArch64/AArch64.td

1031

I don't have small case, but according the history record, this will benefical to 649.fotonik3d_s in spec2006.

[dmgreen]

llvm/lib/Target/AArch64/AArch64.td

1031

Hmm. 649.fotonik3d_s seems to be a fortran benchmark in spec2017. I would not usually measure those. I will see if I can measure some numbers.

[dmgreen]

OK - I've managed to run the fortran benchmarks on a range of micro-architectures, and only saw the same behaviour as before. The STP being less instructions gives slightly less time for the benchmark overall, and I don't see a reason to keep the store-pair-suppress option for the cpus I tried.

I've changed this to keep the feature for non-Arm cpus. I would be surprised if any of them really benefit from it, but this makes it Arm-only (and cpu=generic).

[Allen]

In D134646#3832896, @dmgreen wrote:

OK - I've managed to run the fortran benchmarks on a range of micro-architectures, and only saw the same behaviour as before. The STP being less instructions gives slightly less time for the benchmark overall, and I don't see a reason to keep the store-pair-suppress option for the cpus I tried.

I've changed this to keep the feature for non-Arm cpus. I would be surprised if any of them really benefit from it, but this makes it Arm-only (and cpu=generic).

Thanks for the check. I also recheck the performance and find this change doesn't affect performance in our newest downstream branch, so LGTM for tsv110 now.

[samtebbs]

Nice, LGTM

llvm/lib/Target/AArch64/AArch64.td

 def FeatureFuseLiterals : SubtargetFeature<
     "fuse-literals", "HasFuseLiterals", "true",
     "CPU fuses literal generation operations">;
 
 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
     "Disable latency scheduling heuristic">;
 
+def FeatureStorePairSuppress : SubtargetFeature<
+    "store-pair-suppress", "EnableStorePairSuppress", "true",
+    "Enable Store Pair Suppression heuristics">;
+
 def FeatureForce32BitJumpTables
    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
                       "Force jump table entries to be 32-bits wide except at MinSize">;
 
 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
                                    "Enable support for RCPC extension (FEAT_LRCPC)">;
 
 def FeatureUseRSqrt : SubtargetFeature<

 // perform the fusion and cyclone is used by default when targetting apple OSes.
 def TuneAppleA7  : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
                                     "Apple A7 (the CPU formerly known as Cyclone)", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAES, FeatureFuseCryptoEOR,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing,
                                     FeatureZCZeroingFPWorkaround]
                                     >;
 
 def TuneAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
                                     "Apple A10", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAES,
                                     FeatureFuseCryptoEOR,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing]
                                     >;
 
 def TuneAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
                                     "Apple A11", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAES,
                                     FeatureFuseCryptoEOR,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing]
                                     >;
 
 def TuneAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
                                     "Apple A12", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAES,
                                     FeatureFuseCryptoEOR,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing]
                                     >;
 
 def TuneAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
                                     "Apple A13", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAES,
                                     FeatureFuseCryptoEOR,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing]
                                     >;
 
 def TuneAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
                                     "Apple A14", [
                                     FeatureAggressiveFMA,
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAddress,
                                     FeatureFuseAES,
                                     FeatureFuseArithmeticLogic,
                                     FeatureFuseCCSelect,
                                     FeatureFuseCryptoEOR,
                                     FeatureFuseAdrpAdd,
                                     FeatureFuseLiterals,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing]>;
 
 def TuneAppleA15 : SubtargetFeature<"apple-a15", "ARMProcFamily", "AppleA15",
                                     "Apple A15", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAddress,
                                     FeatureFuseAES,
                                     FeatureFuseArithmeticLogic,
                                     FeatureFuseCCSelect,
                                     FeatureFuseCryptoEOR,
                                     FeatureFuseLiterals,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing
                                     ]>;
 
 def TuneAppleA16 : SubtargetFeature<"apple-a16", "ARMProcFamily", "AppleA16",
                                     "Apple A16", [
                                     FeatureAlternateSExtLoadCVTF32Pattern,
                                     FeatureArithmeticBccFusion,
                                     FeatureArithmeticCbzFusion,
                                     FeatureDisableLatencySchedHeuristic,
                                     FeatureFuseAddress,
                                     FeatureFuseAES,
                                     FeatureFuseArithmeticLogic,
                                     FeatureFuseCCSelect,
                                     FeatureFuseCryptoEOR,
                                     FeatureFuseLiterals,
+                                    FeatureStorePairSuppress,
                                     FeatureZCRegMove,
                                     FeatureZCZeroing
                                     ]>;
 
 def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
                                     "Samsung Exynos-M3 processors",
                                     [FeatureExynosCheapAsMoveHandling,
                                      FeatureForce32BitJumpTables,
def TuneThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
                                        FeaturePredictableSelectIsExpensive]>;
 
 def TuneThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
                                        "ThunderXT83",
                                        "Cavium ThunderX processors", [
                                        FeaturePostRAScheduler,
                                        FeaturePredictableSelectIsExpensive]>;
 
 def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
                                   "HiSilicon TS-V110 processors", [
                                   FeatureCustomCheapAsMoveHandling,
                                   FeatureFuseAES,
                                   FeaturePostRAScheduler]>;
 
 def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
                                    "Ampere Computing Ampere-1 processors", [
                                    FeaturePostRAScheduler,

llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp

 //===--- AArch64StorePairSuppress.cpp --- Suppress store pair formation ---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass identifies floating point stores that should not be combined into
 // store pairs. Later we may do the same for floating point loads.
 // ===---------------------------------------------------------------------===//
 
 #include "AArch64InstrInfo.h"
+#include "AArch64Subtarget.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineTraceMetrics.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
case AArch64::STURDi:
     return true;
   }
 }
 
 bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()) || MF.getFunction().hasOptSize())
     return false;
 
-  const TargetSubtargetInfo &ST = MF.getSubtarget();
+  const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
+  if (!ST.enableStorePairSuppress())
+    return false;
+
   TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
   TRI = ST.getRegisterInfo();
   MRI = &MF.getRegInfo();
   SchedModel.init(&ST);
   Traces = &getAnalysis<MachineTraceMetrics>();
   MinInstr = nullptr;
 
   LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n');

llvm/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll

-; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-EVEN
-; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-ODD
-; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN
-; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD
+; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN
+; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD
+; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN
+; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD
 
 ; The following tests use the balance-fp-ops feature, and should be independent of
 ; the target cpu.
 
-; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN --check-prefix CHECK-BALFP
-; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops  -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD --check-prefix CHECK-BALFP
+; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN
+; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops  -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD
 
 ; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so
 ; our test strategy is to:
 ;   * Force the pass to always perform register swapping even if the dest register is of the
 ;     correct color already (-force-all)
 ;   * Force the pass to ignore all hints it obtained from regalloc (-deterministic-balance),
 ;     and run it twice, once where it always hints odd, and once where it always hints even.
 ;

 ; CHECK-EVEN: fmul [[y:d[0-9]*[13579]]]
 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
 ; CHECK-ODD: fmul [[y:d[0-9]*[02468]]]
 ; CHECK: fmadd [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmsub [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmadd [[x]]
-; CHECK-BALFP: stp [[x]], [[y]]
-; CHECK-A53-DAG: str [[x]]
-; CHECK-A53-DAG: str [[y]]
+; CHECK: stp [[x]], [[y]]
 
 define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 {
 entry:
   %0 = load double, double* %p, align 8
   %arrayidx1 = getelementptr inbounds double, double* %p, i64 1
   %1 = load double, double* %arrayidx1, align 8
   %arrayidx2 = getelementptr inbounds double, double* %p, i64 2
   %2 = load double, double* %arrayidx2, align 8

 ; CHECK-EVEN: fmul [[y:s[0-9]*[13579]]]
 ; CHECK-ODD: fmadd [[x:s[0-9]*[13579]]]
 ; CHECK-ODD: fmul [[y:s[0-9]*[02468]]]
 ; CHECK: fmadd [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmsub [[x]]
 ; CHECK: fmadd [[y]]
 ; CHECK: fmadd [[x]]
-; CHECK-BALFP: stp [[x]], [[y]]
-; CHECK-A53-DAG: str [[x]]
-; CHECK-A53-DAG: str [[y]]
+; CHECK: stp [[x]], [[y]]
 
 define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 {
 entry:
   %0 = load float, float* %p, align 4
   %arrayidx1 = getelementptr inbounds float, float* %p, i64 1
   %1 = load float, float* %arrayidx1, align 4
   %arrayidx2 = getelementptr inbounds float, float* %p, i64 2
   %2 = load float, float* %arrayidx2, align 4

llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll

 ; CHECK-LABEL: caller_in_block:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    bl return_in_block
 ; CHECK-NEXT:    adrp x8, in_block_store
 ; CHECK-NEXT:    add x8, x8, :lo12:in_block_store
-; CHECK-NEXT:    str d0, [x8]
-; CHECK-NEXT:    str d1, [x8, #8]
-; CHECK-NEXT:    str d2, [x8, #16]
-; CHECK-NEXT:    str d3, [x8, #24]
-; CHECK-NEXT:    str d4, [x8, #32]
-; CHECK-NEXT:    str d5, [x8, #40]
+; CHECK-NEXT:    stp d0, d1, [x8]
+; CHECK-NEXT:    stp d2, d3, [x8, #16]
+; CHECK-NEXT:    stp d4, d5, [x8, #32]
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %1 = call %T_IN_BLOCK @return_in_block()
   store %T_IN_BLOCK %1, %T_IN_BLOCK* @in_block_store
   ret void
 }
 
 define void @callee_in_block(%T_IN_BLOCK %a) {
 ; CHECK-LABEL: callee_in_block:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, in_block_store
 ; CHECK-NEXT:    add x8, x8, :lo12:in_block_store
-; CHECK-NEXT:    str d5, [x8, #40]
-; CHECK-NEXT:    str d4, [x8, #32]
-; CHECK-NEXT:    str d3, [x8, #24]
-; CHECK-NEXT:    str d2, [x8, #16]
-; CHECK-NEXT:    str d1, [x8, #8]
-; CHECK-NEXT:    str d0, [x8]
+; CHECK-NEXT:    stp d4, d5, [x8, #32]
+; CHECK-NEXT:    stp d2, d3, [x8, #16]
+; CHECK-NEXT:    stp d0, d1, [x8]
 ; CHECK-NEXT:    ret
   store %T_IN_BLOCK %a, %T_IN_BLOCK* @in_block_store
   ret void
 }
 
 define void @argument_in_block() {
 ; CHECK-LABEL: argument_in_block:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/arm64-windows-calls.ll

 @Pod = external global %struct.Pod
 
 ; CHECK-LABEL: call_copy_pod:
 define void @call_copy_pod() {
   %x = call %struct.Pod @copy_pod(%struct.Pod* @Pod)
   store %struct.Pod %x, %struct.Pod* @Pod
   ret void
   ; CHECK: bl copy_pod
-  ; CHECK-NEXT: str d0, [{{.*}}]
-  ; CHECK-NEXT: str d1, [{{.*}}]
+  ; CHECK-NEXT: stp d0, d1, [{{.*}}]
 }
 
 @NotCXX14Aggregate = external global %struct.NotCXX14Aggregate
 
 ; CHECK-LABEL: call_copy_notcxx14aggregate:
 define void @call_copy_notcxx14aggregate() {
   %x = alloca %struct.NotCXX14Aggregate
   call void @copy_notcxx14aggregate(%struct.NotCXX14Aggregate* %x, %struct.NotCXX14Aggregate* @NotCXX14Aggregate)

llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir

machineFunctionInfo:
   hasRedZone:      false
 body:             |
   bb.0:
     liveins: $s0, $s1, $x1
     ; CHECK-LABEL: name: 3-ldrspre-ldrsui-merge
     ; CHECK: liveins: $s0, $s1, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber $x1, renamable $s0, renamable $s1 = LDPSpre renamable $x1, 3 :: (load (s32))
-    ; CHECK-NEXT: STRSui renamable $s0, renamable $x1, 0 :: (store (s32))
-    ; CHECK-NEXT: STRSui renamable $s1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s32))
+    ; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $s0 = LDRSpre killed renamable $x1, 12 :: (load (s32))
     renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
 ...
 
machineFunctionInfo:
   hasRedZone:      false
 body:             |
   bb.0:
     liveins: $d0, $d1, $x1
     ; CHECK-LABEL: name: 4-ldrqdre-ldrdui-merge
     ; CHECK: liveins: $d0, $d1, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber $x1, renamable $d0, renamable $d1 = LDPDpre renamable $x1, 16 :: (load (s64))
-    ; CHECK-NEXT: STRDui renamable $d0, renamable $x1, 0 :: (store (s64))
-    ; CHECK-NEXT: STRDui renamable $d1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s64))
+    ; CHECK-NEXT: STPDi renamable $d0, renamable $d1, renamable $x1, 0 :: (store (s64))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $d0 = LDRDpre killed renamable $x1, 128 :: (load (s64))
     renamable $d1 = LDRDui renamable $x1, 1 :: (load (s64))
     STRDui killed renamable $d0, renamable $x1, 0 :: (store (s64))
     STRDui killed renamable $d1, renamable $x1, 1 :: (store (s64))
     RET undef $lr
 ...
 
bb.0:
     liveins: $s0, $s1, $x0, $x1
     ; CHECK-LABEL: name: 10-ldrspre-ldrsui-used-base-reg-no-merge
     ; CHECK: liveins: $s0, $s1, $x0, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1 :: (load (s32))
     ; CHECK-NEXT: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
     ; CHECK-NEXT: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
     ; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
-    ; CHECK-NEXT: STRSui renamable $s0, renamable $x1, 0 :: (store (s32))
-    ; CHECK-NEXT: STRSui renamable $s1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s32))
+    ; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $s0 = LDRSpre killed renamable $x1, 12 :: (load (s32))
     renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
     STRXui killed renamable $x0, renamable $x0, 1 :: (store (s64))
     renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
bb.0:
     ; The offset of the second load is not equal to the
     ; size of the destination register,  and hence can’t be merged.
 
     ; CHECK-LABEL: name: 12-ldrspre-ldrsui-no-merge
     ; CHECK: liveins: $s0, $s1, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1 :: (load (s32))
     ; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 2 :: (load (s32))
-    ; CHECK-NEXT: STRSui renamable $s0, renamable $x1, 0 :: (store (s32))
-    ; CHECK-NEXT: STRSui renamable $s1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s32))
+    ; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $s0 = LDRSpre killed renamable $x1, 12 :: (load (s32))
     renamable $s1 = LDRSui renamable $x1, 2 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
 ...
 
machineFunctionInfo:
   hasRedZone:      false
 body:             |
   bb.0:
     liveins: $s0, $s1, $x1
     ; CHECK-LABEL: name: 19-ldrspre-ldrsui-max-merge
     ; CHECK: liveins: $s0, $s1, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber $x1, renamable $s0, renamable $s1 = LDPSpre renamable $x1, 63 :: (load (s32))
-    ; CHECK-NEXT: STRSui renamable $s0, renamable $x1, 0 :: (store (s32))
-    ; CHECK-NEXT: STRSui renamable $s1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s32))
+    ; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $s0 = LDRSpre killed renamable $x1, 252 :: (load (s32))
     renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
 ...
 

 body:             |
   bb.0:
     liveins: $s0, $s1, $x1
     ; CHECK-LABEL: name: 20-ldrspre-ldrsui-unaligned-no-merge
     ; CHECK: liveins: $s0, $s1, $x1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 251, implicit $w1 :: (load (s32))
     ; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
-    ; CHECK-NEXT: STRSui renamable $s0, renamable $x1, 0 :: (store (s32))
-    ; CHECK-NEXT: STRSui renamable $s1, renamable $x1, 1 :: ("aarch64-suppress-pair" store (s32))
+    ; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
     ; CHECK-NEXT: RET undef $lr
     early-clobber renamable $x1, renamable $s0 = LDRSpre killed renamable $x1, 251 :: (load (s32))
     renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
     STRSui killed renamable $s0, renamable $x1, 0 :: (store (s32))
     STRSui killed renamable $s1, renamable $x1, 1 :: (store (s32))
     RET undef $lr
 ...

llvm/test/CodeGen/AArch64/storepairsuppress_minsize.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-eabi -mcpu=cortex-a55 -mattr=+store-pair-suppress -o - %s | FileCheck %s
 
 ; Check that stp are not suppressed at minsize.
 
 %T_IN_BLOCK = type [ 2 x { double, { double, double } } ]
 declare %T_IN_BLOCK @return_in_block()
 @in_block_store = dso_local global %T_IN_BLOCK zeroinitializer, align 8
 
 define void @test_default() uwtable {